lib/Target/ARM/ARMBaseInfo.h

   1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains small standalone helper functions and enum definitions for
  11 // the ARM target useful for the compiler back-end and the MC libraries.
  12 // As such, it deliberately does not include references to LLVM core
  13 // code gen types, passes, etc..
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #ifndef ARMBASEINFO_H
  18 #define ARMBASEINFO_H
  19
  20 #include "MCTargetDesc/ARMMCTargetDesc.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22
  23 // Note that the following auto-generated files only defined enum types, and
  24 // so are safe to include here.
  25
  26 namespace llvm {
  27
  28 // Enums corresponding to ARM condition codes
  29 namespace ARMCC {
  30   // The CondCodes constants map directly to the 4-bit encoding of the
  31   // condition field for predicated instructions.
  32   enum CondCodes { // Meaning (integer)          Meaning (floating-point)
  33     EQ,            // Equal                      Equal
  34     NE,            // Not equal                  Not equal, or unordered
  35     HS,            // Carry set                  >, ==, or unordered
  36     LO,            // Carry clear                Less than
  37     MI,            // Minus, negative            Less than
  38     PL,            // Plus, positive or zero     >, ==, or unordered
  39     VS,            // Overflow                   Unordered
  40     VC,            // No overflow                Not unordered
  41     HI,            // Unsigned higher            Greater than, or unordered
  42     LS,            // Unsigned lower or same     Less than or equal
  43     GE,            // Greater than or equal      Greater than or equal
  44     LT,            // Less than                  Less than, or unordered
  45     GT,            // Greater than               Greater than
  46     LE,            // Less than or equal         <, ==, or unordered
  47     AL             // Always (unconditional)     Always (unconditional)
  48   };
  49
  50   inline static CondCodes getOppositeCondition(CondCodes CC) {
  51     switch (CC) {
  52     default: llvm_unreachable("Unknown condition code");
  53     case EQ: return NE;
  54     case NE: return EQ;
  55     case HS: return LO;
  56     case LO: return HS;
  57     case MI: return PL;
  58     case PL: return MI;
  59     case VS: return VC;
  60     case VC: return VS;
  61     case HI: return LS;
  62     case LS: return HI;
  63     case GE: return LT;
  64     case LT: return GE;
  65     case GT: return LE;
  66     case LE: return GT;
  67     }
  68   }
  69 } // namespace ARMCC
  70
  71 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
  72   switch (CC) {
  73   default: llvm_unreachable("Unknown condition code");
  74   case ARMCC::EQ:  return "eq";
  75   case ARMCC::NE:  return "ne";
  76   case ARMCC::HS:  return "hs";
  77   case ARMCC::LO:  return "lo";
  78   case ARMCC::MI:  return "mi";
  79   case ARMCC::PL:  return "pl";
  80   case ARMCC::VS:  return "vs";
  81   case ARMCC::VC:  return "vc";
  82   case ARMCC::HI:  return "hi";
  83   case ARMCC::LS:  return "ls";
  84   case ARMCC::GE:  return "ge";
  85   case ARMCC::LT:  return "lt";
  86   case ARMCC::GT:  return "gt";
  87   case ARMCC::LE:  return "le";
  88   case ARMCC::AL:  return "al";
  89   }
  90 }
  91
  92 namespace ARM_PROC {
  93   enum IMod {
  94     IE = 2,
  95     ID = 3
  96   };
  97
  98   enum IFlags {
  99     F = 1,
 100     I = 2,
 101     A = 4
 102   };
 103
 104   inline static const char *IFlagsToString(unsigned val) {
 105     switch (val) {
 106     default: llvm_unreachable("Unknown iflags operand");
 107     case F: return "f";
 108     case I: return "i";
 109     case A: return "a";
 110     }
 111   }
 112
 113   inline static const char *IModToString(unsigned val) {
 114     switch (val) {
 115     default: llvm_unreachable("Unknown imod operand");
 116     case IE: return "ie";
 117     case ID: return "id";
 118     }
 119   }
 120 }
 121
 122 namespace ARM_MB {
 123   // The Memory Barrier Option constants map directly to the 4-bit encoding of
 124   // the option field for memory barrier operations.
 125   enum MemBOpt {
 126     SY    = 15,
 127     ST    = 14,
 128     ISH   = 11,
 129     ISHST = 10,
 130     NSH   = 7,
 131     NSHST = 6,
 132     OSH   = 3,
 133     OSHST = 2
 134   };
 135
 136   inline static const char *MemBOptToString(unsigned val) {
 137     switch (val) {
 138     default: llvm_unreachable("Unknown memory operation");
 139     case SY:    return "sy";
 140     case ST:    return "st";
 141     case ISH:   return "ish";
 142     case ISHST: return "ishst";
 143     case NSH:   return "nsh";
 144     case NSHST: return "nshst";
 145     case OSH:   return "osh";
 146     case OSHST: return "oshst";
 147     }
 148   }
 149 } // namespace ARM_MB
 150
 151 /// getARMRegisterNumbering - Given the enum value for some register, e.g.
 152 /// ARM::LR, return the number that it corresponds to (e.g. 14).
 153 inline static unsigned getARMRegisterNumbering(unsigned Reg) {
 154   using namespace ARM;
 155   switch (Reg) {
 156   default:
 157     llvm_unreachable("Unknown ARM register!");
 158   case R0:  case S0:  case D0:  case Q0:  return 0;
 159   case R1:  case S1:  case D1:  case Q1:  return 1;
 160   case R2:  case S2:  case D2:  case Q2:  return 2;
 161   case R3:  case S3:  case D3:  case Q3:  return 3;
 162   case R4:  case S4:  case D4:  case Q4:  return 4;
 163   case R5:  case S5:  case D5:  case Q5:  return 5;
 164   case R6:  case S6:  case D6:  case Q6:  return 6;
 165   case R7:  case S7:  case D7:  case Q7:  return 7;
 166   case R8:  case S8:  case D8:  case Q8:  return 8;
 167   case R9:  case S9:  case D9:  case Q9:  return 9;
 168   case R10: case S10: case D10: case Q10: return 10;
 169   case R11: case S11: case D11: case Q11: return 11;
 170   case R12: case S12: case D12: case Q12: return 12;
 171   case SP:  case S13: case D13: case Q13: return 13;
 172   case LR:  case S14: case D14: case Q14: return 14;
 173   case PC:  case S15: case D15: case Q15: return 15;
 174
 175   case S16: case D16: return 16;
 176   case S17: case D17: return 17;
 177   case S18: case D18: return 18;
 178   case S19: case D19: return 19;
 179   case S20: case D20: return 20;
 180   case S21: case D21: return 21;
 181   case S22: case D22: return 22;
 182   case S23: case D23: return 23;
 183   case S24: case D24: return 24;
 184   case S25: case D25: return 25;
 185   case S26: case D26: return 26;
 186   case S27: case D27: return 27;
 187   case S28: case D28: return 28;
 188   case S29: case D29: return 29;
 189   case S30: case D30: return 30;
 190   case S31: case D31: return 31;
 191   }
 192 }
 193
 194 namespace ARMII {
 195
 196   /// ARM Index Modes
 197   enum IndexMode {
 198     IndexModeNone  = 0,
 199     IndexModePre   = 1,
 200     IndexModePost  = 2,
 201     IndexModeUpd   = 3
 202   };
 203
 204   /// ARM Addressing Modes
 205   enum AddrMode {
 206     AddrModeNone    = 0,
 207     AddrMode1       = 1,
 208     AddrMode2       = 2,
 209     AddrMode3       = 3,
 210     AddrMode4       = 4,
 211     AddrMode5       = 5,
 212     AddrMode6       = 6,
 213     AddrModeT1_1    = 7,
 214     AddrModeT1_2    = 8,
 215     AddrModeT1_4    = 9,
 216     AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
 217     AddrModeT2_i12  = 11,
 218     AddrModeT2_i8   = 12,
 219     AddrModeT2_so   = 13,
 220     AddrModeT2_pc   = 14, // +/- i12 for pc relative data
 221     AddrModeT2_i8s4 = 15, // i8 * 4
 222     AddrMode_i12    = 16
 223   };
 224
 225   inline static const char *AddrModeToString(AddrMode addrmode) {
 226     switch (addrmode) {
 227     default: llvm_unreachable("Unknown memory operation");
 228     case AddrModeNone:    return "AddrModeNone";
 229     case AddrMode1:       return "AddrMode1";
 230     case AddrMode2:       return "AddrMode2";
 231     case AddrMode3:       return "AddrMode3";
 232     case AddrMode4:       return "AddrMode4";
 233     case AddrMode5:       return "AddrMode5";
 234     case AddrMode6:       return "AddrMode6";
 235     case AddrModeT1_1:    return "AddrModeT1_1";
 236     case AddrModeT1_2:    return "AddrModeT1_2";
 237     case AddrModeT1_4:    return "AddrModeT1_4";
 238     case AddrModeT1_s:    return "AddrModeT1_s";
 239     case AddrModeT2_i12:  return "AddrModeT2_i12";
 240     case AddrModeT2_i8:   return "AddrModeT2_i8";
 241     case AddrModeT2_so:   return "AddrModeT2_so";
 242     case AddrModeT2_pc:   return "AddrModeT2_pc";
 243     case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
 244     case AddrMode_i12:    return "AddrMode_i12";
 245     }
 246   }
 247
 248   /// Target Operand Flag enum.
 249   enum TOF {
 250     //===------------------------------------------------------------------===//
 251     // ARM Specific MachineOperand flags.
 252
 253     MO_NO_FLAG,
 254
 255     /// MO_LO16 - On a symbol operand, this represents a relocation containing
 256     /// lower 16 bit of the address. Used only via movw instruction.
 257     MO_LO16,
 258
 259     /// MO_HI16 - On a symbol operand, this represents a relocation containing
 260     /// higher 16 bit of the address. Used only via movt instruction.
 261     MO_HI16,
 262
 263     /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
 264     /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
 265     /// i.e. "FOO$non_lazy_ptr".
 266     /// Used only via movw instruction.
 267     MO_LO16_NONLAZY,
 268
 269     /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
 270     /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
 271     /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
 272     MO_HI16_NONLAZY,
 273
 274     /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
 275     /// relocation containing lower 16 bit of the PC relative address of the
 276     /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
 277     /// Used only via movw instruction.
 278     MO_LO16_NONLAZY_PIC,
 279
 280     /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
 281     /// relocation containing lower 16 bit of the PC relative address of the
 282     /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
 283     /// Used only via movt instruction.
 284     MO_HI16_NONLAZY_PIC,
 285
 286     /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
 287     /// call operand.
 288     MO_PLT
 289   };
 290 } // end namespace ARMII
 291
 292 } // end namespace llvm;
 293
 294 #endif