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Use BranchProbability instead of floating points in IfConverter.
[llvm/stm8.git] / lib / Target / ARM / ARMBaseInstrInfo.cpp
blobb1aa7ce4b6c0f17c1094392fb6c33093e8e17d90
1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARMBaseInstrInfo.h"
15 #include "ARM.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
38
39 #define GET_INSTRINFO_MC_DESC
40 #define GET_INSTRINFO_CTOR
41 #include "ARMGenInstrInfo.inc"
42
43 using namespace llvm;
44
45 static cl::opt<bool>
46 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
47 cl::desc("Enable ARM 2-addr to 3-addr conv"));
48
49 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
50 struct ARM_MLxEntry {
51 unsigned MLxOpc; // MLA / MLS opcode
52 unsigned MulOpc; // Expanded multiplication opcode
53 unsigned AddSubOpc; // Expanded add / sub opcode
54 bool NegAcc; // True if the acc is negated before the add / sub.
55 bool HasLane; // True if instruction has an extra "lane" operand.
56 };
57
58 static const ARM_MLxEntry ARM_MLxTable[] = {
59 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
60 // fp scalar ops
61 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
62 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
63 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
64 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
65 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
66 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
67 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
68 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
69
70 // fp SIMD ops
71 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
72 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
73 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
74 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
75 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
76 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
77 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
78 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
79 };
80
81 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
82 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
83 Subtarget(STI) {
84 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
85 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
86 assert(false && "Duplicated entries?");
87 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
88 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
89 }
90 }
91
92 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
93 // currently defaults to no prepass hazard recognizer.
94 ScheduleHazardRecognizer *ARMBaseInstrInfo::
95 CreateTargetHazardRecognizer(const TargetMachine *TM,
96 const ScheduleDAG *DAG) const {
97 if (usePreRAHazardRecognizer()) {
98 const InstrItineraryData *II = TM->getInstrItineraryData();
99 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
100 }
101 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
102 }
103
104 ScheduleHazardRecognizer *ARMBaseInstrInfo::
105 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
106 const ScheduleDAG *DAG) const {
107 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
108 return (ScheduleHazardRecognizer *)
109 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
110 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
111 }
112
113 MachineInstr *
114 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
115 MachineBasicBlock::iterator &MBBI,
116 LiveVariables *LV) const {
117 // FIXME: Thumb2 support.
118
119 if (!EnableARM3Addr)
120 return NULL;
121
122 MachineInstr *MI = MBBI;
123 MachineFunction &MF = *MI->getParent()->getParent();
124 uint64_t TSFlags = MI->getDesc().TSFlags;
125 bool isPre = false;
126 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
127 default: return NULL;
128 case ARMII::IndexModePre:
129 isPre = true;
130 break;
131 case ARMII::IndexModePost:
132 break;
133 }
134
135 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
136 // operation.
137 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
138 if (MemOpc == 0)
139 return NULL;
140
141 MachineInstr *UpdateMI = NULL;
142 MachineInstr *MemMI = NULL;
143 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
144 const MCInstrDesc &MCID = MI->getDesc();
145 unsigned NumOps = MCID.getNumOperands();
146 bool isLoad = !MCID.mayStore();
147 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
148 const MachineOperand &Base = MI->getOperand(2);
149 const MachineOperand &Offset = MI->getOperand(NumOps-3);
150 unsigned WBReg = WB.getReg();
151 unsigned BaseReg = Base.getReg();
152 unsigned OffReg = Offset.getReg();
153 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
154 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
155 switch (AddrMode) {
156 default:
157 assert(false && "Unknown indexed op!");
158 return NULL;
159 case ARMII::AddrMode2: {
160 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
161 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
162 if (OffReg == 0) {
163 if (ARM_AM::getSOImmVal(Amt) == -1)
164 // Can't encode it in a so_imm operand. This transformation will
165 // add more than 1 instruction. Abandon!
166 return NULL;
167 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
168 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
169 .addReg(BaseReg).addImm(Amt)
170 .addImm(Pred).addReg(0).addReg(0);
171 } else if (Amt != 0) {
172 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
173 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
174 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
175 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
176 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
177 .addImm(Pred).addReg(0).addReg(0);
178 } else
179 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
180 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
181 .addReg(BaseReg).addReg(OffReg)
182 .addImm(Pred).addReg(0).addReg(0);
183 break;
184 }
185 case ARMII::AddrMode3 : {
186 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
187 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
188 if (OffReg == 0)
189 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
190 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
191 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
192 .addReg(BaseReg).addImm(Amt)
193 .addImm(Pred).addReg(0).addReg(0);
194 else
195 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
196 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
197 .addReg(BaseReg).addReg(OffReg)
198 .addImm(Pred).addReg(0).addReg(0);
199 break;
200 }
201 }
202
203 std::vector<MachineInstr*> NewMIs;
204 if (isPre) {
205 if (isLoad)
206 MemMI = BuildMI(MF, MI->getDebugLoc(),
207 get(MemOpc), MI->getOperand(0).getReg())
208 .addReg(WBReg).addImm(0).addImm(Pred);
209 else
210 MemMI = BuildMI(MF, MI->getDebugLoc(),
211 get(MemOpc)).addReg(MI->getOperand(1).getReg())
212 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
213 NewMIs.push_back(MemMI);
214 NewMIs.push_back(UpdateMI);
215 } else {
216 if (isLoad)
217 MemMI = BuildMI(MF, MI->getDebugLoc(),
218 get(MemOpc), MI->getOperand(0).getReg())
219 .addReg(BaseReg).addImm(0).addImm(Pred);
220 else
221 MemMI = BuildMI(MF, MI->getDebugLoc(),
222 get(MemOpc)).addReg(MI->getOperand(1).getReg())
223 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
224 if (WB.isDead())
225 UpdateMI->getOperand(0).setIsDead();
226 NewMIs.push_back(UpdateMI);
227 NewMIs.push_back(MemMI);
228 }
229
230 // Transfer LiveVariables states, kill / dead info.
231 if (LV) {
232 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
233 MachineOperand &MO = MI->getOperand(i);
234 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
235 unsigned Reg = MO.getReg();
236
237 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
238 if (MO.isDef()) {
239 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
240 if (MO.isDead())
241 LV->addVirtualRegisterDead(Reg, NewMI);
242 }
243 if (MO.isUse() && MO.isKill()) {
244 for (unsigned j = 0; j < 2; ++j) {
245 // Look at the two new MI's in reverse order.
246 MachineInstr *NewMI = NewMIs[j];
247 if (!NewMI->readsRegister(Reg))
248 continue;
249 LV->addVirtualRegisterKilled(Reg, NewMI);
250 if (VI.removeKill(MI))
251 VI.Kills.push_back(NewMI);
252 break;
253 }
254 }
255 }
256 }
257 }
258
259 MFI->insert(MBBI, NewMIs[1]);
260 MFI->insert(MBBI, NewMIs[0]);
261 return NewMIs[0];
262 }
263
264 // Branch analysis.
265 bool
266 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
267 MachineBasicBlock *&FBB,
268 SmallVectorImpl<MachineOperand> &Cond,
269 bool AllowModify) const {
270 // If the block has no terminators, it just falls into the block after it.
271 MachineBasicBlock::iterator I = MBB.end();
272 if (I == MBB.begin())
273 return false;
274 --I;
275 while (I->isDebugValue()) {
276 if (I == MBB.begin())
277 return false;
278 --I;
279 }
280 if (!isUnpredicatedTerminator(I))
281 return false;
282
283 // Get the last instruction in the block.
284 MachineInstr *LastInst = I;
285
286 // If there is only one terminator instruction, process it.
287 unsigned LastOpc = LastInst->getOpcode();
288 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
289 if (isUncondBranchOpcode(LastOpc)) {
290 TBB = LastInst->getOperand(0).getMBB();
291 return false;
292 }
293 if (isCondBranchOpcode(LastOpc)) {
294 // Block ends with fall-through condbranch.
295 TBB = LastInst->getOperand(0).getMBB();
296 Cond.push_back(LastInst->getOperand(1));
297 Cond.push_back(LastInst->getOperand(2));
298 return false;
299 }
300 return true; // Can't handle indirect branch.
301 }
302
303 // Get the instruction before it if it is a terminator.
304 MachineInstr *SecondLastInst = I;
305 unsigned SecondLastOpc = SecondLastInst->getOpcode();
306
307 // If AllowModify is true and the block ends with two or more unconditional
308 // branches, delete all but the first unconditional branch.
309 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
310 while (isUncondBranchOpcode(SecondLastOpc)) {
311 LastInst->eraseFromParent();
312 LastInst = SecondLastInst;
313 LastOpc = LastInst->getOpcode();
314 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
315 // Return now the only terminator is an unconditional branch.
316 TBB = LastInst->getOperand(0).getMBB();
317 return false;
318 } else {
319 SecondLastInst = I;
320 SecondLastOpc = SecondLastInst->getOpcode();
321 }
322 }
323 }
324
325 // If there are three terminators, we don't know what sort of block this is.
326 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
327 return true;
328
329 // If the block ends with a B and a Bcc, handle it.
330 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
331 TBB = SecondLastInst->getOperand(0).getMBB();
332 Cond.push_back(SecondLastInst->getOperand(1));
333 Cond.push_back(SecondLastInst->getOperand(2));
334 FBB = LastInst->getOperand(0).getMBB();
335 return false;
336 }
337
338 // If the block ends with two unconditional branches, handle it. The second
339 // one is not executed, so remove it.
340 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
341 TBB = SecondLastInst->getOperand(0).getMBB();
342 I = LastInst;
343 if (AllowModify)
344 I->eraseFromParent();
345 return false;
346 }
347
348 // ...likewise if it ends with a branch table followed by an unconditional
349 // branch. The branch folder can create these, and we must get rid of them for
350 // correctness of Thumb constant islands.
351 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
352 isIndirectBranchOpcode(SecondLastOpc)) &&
353 isUncondBranchOpcode(LastOpc)) {
354 I = LastInst;
355 if (AllowModify)
356 I->eraseFromParent();
357 return true;
358 }
359
360 // Otherwise, can't handle this.
361 return true;
362 }
363
364
365 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
366 MachineBasicBlock::iterator I = MBB.end();
367 if (I == MBB.begin()) return 0;
368 --I;
369 while (I->isDebugValue()) {
370 if (I == MBB.begin())
371 return 0;
372 --I;
373 }
374 if (!isUncondBranchOpcode(I->getOpcode()) &&
375 !isCondBranchOpcode(I->getOpcode()))
376 return 0;
377
378 // Remove the branch.
379 I->eraseFromParent();
380
381 I = MBB.end();
382
383 if (I == MBB.begin()) return 1;
384 --I;
385 if (!isCondBranchOpcode(I->getOpcode()))
386 return 1;
387
388 // Remove the branch.
389 I->eraseFromParent();
390 return 2;
391 }
392
393 unsigned
394 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
395 MachineBasicBlock *FBB,
396 const SmallVectorImpl<MachineOperand> &Cond,
397 DebugLoc DL) const {
398 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
399 int BOpc = !AFI->isThumbFunction()
400 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
401 int BccOpc = !AFI->isThumbFunction()
402 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
403
404 // Shouldn't be a fall through.
405 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
406 assert((Cond.size() == 2 || Cond.size() == 0) &&
407 "ARM branch conditions have two components!");
408
409 if (FBB == 0) {
410 if (Cond.empty()) // Unconditional branch?
411 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
412 else
413 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
414 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
415 return 1;
416 }
417
418 // Two-way conditional branch.
419 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
421 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
422 return 2;
423 }
424
425 bool ARMBaseInstrInfo::
426 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
427 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
428 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
429 return false;
430 }
431
432 bool ARMBaseInstrInfo::
433 PredicateInstruction(MachineInstr *MI,
434 const SmallVectorImpl<MachineOperand> &Pred) const {
435 unsigned Opc = MI->getOpcode();
436 if (isUncondBranchOpcode(Opc)) {
437 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
438 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
439 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
440 return true;
441 }
442
443 int PIdx = MI->findFirstPredOperandIdx();
444 if (PIdx != -1) {
445 MachineOperand &PMO = MI->getOperand(PIdx);
446 PMO.setImm(Pred[0].getImm());
447 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
448 return true;
449 }
450 return false;
451 }
452
453 bool ARMBaseInstrInfo::
454 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
455 const SmallVectorImpl<MachineOperand> &Pred2) const {
456 if (Pred1.size() > 2 || Pred2.size() > 2)
457 return false;
458
459 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
460 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
461 if (CC1 == CC2)
462 return true;
463
464 switch (CC1) {
465 default:
466 return false;
467 case ARMCC::AL:
468 return true;
469 case ARMCC::HS:
470 return CC2 == ARMCC::HI;
471 case ARMCC::LS:
472 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
473 case ARMCC::GE:
474 return CC2 == ARMCC::GT;
475 case ARMCC::LE:
476 return CC2 == ARMCC::LT;
477 }
478 }
479
480 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
481 std::vector<MachineOperand> &Pred) const {
482 // FIXME: This confuses implicit_def with optional CPSR def.
483 const MCInstrDesc &MCID = MI->getDesc();
484 if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef())
485 return false;
486
487 bool Found = false;
488 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
489 const MachineOperand &MO = MI->getOperand(i);
490 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
491 Pred.push_back(MO);
492 Found = true;
493 }
494 }
495
496 return Found;
497 }
498
499 /// isPredicable - Return true if the specified instruction can be predicated.
500 /// By default, this returns true for every instruction with a
501 /// PredicateOperand.
502 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
503 const MCInstrDesc &MCID = MI->getDesc();
504 if (!MCID.isPredicable())
505 return false;
506
507 if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
508 ARMFunctionInfo *AFI =
509 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
510 return AFI->isThumb2Function();
511 }
512 return true;
513 }
514
515 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
516 LLVM_ATTRIBUTE_NOINLINE
517 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
518 unsigned JTI);
519 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
520 unsigned JTI) {
521 assert(JTI < JT.size());
522 return JT[JTI].MBBs.size();
523 }
524
525 /// GetInstSize - Return the size of the specified MachineInstr.
526 ///
527 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
528 const MachineBasicBlock &MBB = *MI->getParent();
529 const MachineFunction *MF = MBB.getParent();
530 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
531
532 // Basic size info comes from the TSFlags field.
533 const MCInstrDesc &MCID = MI->getDesc();
534 uint64_t TSFlags = MCID.TSFlags;
535
536 unsigned Opc = MI->getOpcode();
537 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
538 default: {
539 // If this machine instr is an inline asm, measure it.
540 if (MI->getOpcode() == ARM::INLINEASM)
541 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
542 if (MI->isLabel())
543 return 0;
544 switch (Opc) {
545 default:
546 llvm_unreachable("Unknown or unset size field for instr!");
547 case TargetOpcode::IMPLICIT_DEF:
548 case TargetOpcode::KILL:
549 case TargetOpcode::PROLOG_LABEL:
550 case TargetOpcode::EH_LABEL:
551 case TargetOpcode::DBG_VALUE:
552 return 0;
553 }
554 break;
555 }
556 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
557 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
558 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
559 case ARMII::SizeSpecial: {
560 switch (Opc) {
561 case ARM::MOVi16_ga_pcrel:
562 case ARM::MOVTi16_ga_pcrel:
563 case ARM::t2MOVi16_ga_pcrel:
564 case ARM::t2MOVTi16_ga_pcrel:
565 return 4;
566 case ARM::MOVi32imm:
567 case ARM::t2MOVi32imm:
568 return 8;
569 case ARM::CONSTPOOL_ENTRY:
570 // If this machine instr is a constant pool entry, its size is recorded as
571 // operand #2.
572 return MI->getOperand(2).getImm();
573 case ARM::Int_eh_sjlj_longjmp:
574 return 16;
575 case ARM::tInt_eh_sjlj_longjmp:
576 return 10;
577 case ARM::Int_eh_sjlj_setjmp:
578 case ARM::Int_eh_sjlj_setjmp_nofp:
579 return 20;
580 case ARM::tInt_eh_sjlj_setjmp:
581 case ARM::t2Int_eh_sjlj_setjmp:
582 case ARM::t2Int_eh_sjlj_setjmp_nofp:
583 return 12;
584 case ARM::BR_JTr:
585 case ARM::BR_JTm:
586 case ARM::BR_JTadd:
587 case ARM::tBR_JTr:
588 case ARM::t2BR_JT:
589 case ARM::t2TBB_JT:
590 case ARM::t2TBH_JT: {
591 // These are jumptable branches, i.e. a branch followed by an inlined
592 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
593 // entry is one byte; TBH two byte each.
594 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
595 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
596 unsigned NumOps = MCID.getNumOperands();
597 MachineOperand JTOP =
598 MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2));
599 unsigned JTI = JTOP.getIndex();
600 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
601 assert(MJTI != 0);
602 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
603 assert(JTI < JT.size());
604 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
605 // 4 aligned. The assembler / linker may add 2 byte padding just before
606 // the JT entries. The size does not include this padding; the
607 // constant islands pass does separate bookkeeping for it.
608 // FIXME: If we know the size of the function is less than (1 << 16) *2
609 // bytes, we can use 16-bit entries instead. Then there won't be an
610 // alignment issue.
611 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
612 unsigned NumEntries = getNumJTEntries(JT, JTI);
613 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
614 // Make sure the instruction that follows TBB is 2-byte aligned.
615 // FIXME: Constant island pass should insert an "ALIGN" instruction
616 // instead.
617 ++NumEntries;
618 return NumEntries * EntrySize + InstSize;
619 }
620 default:
621 // Otherwise, pseudo-instruction sizes are zero.
622 return 0;
623 }
624 }
625 }
626 return 0; // Not reached
627 }
628
629 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
630 MachineBasicBlock::iterator I, DebugLoc DL,
631 unsigned DestReg, unsigned SrcReg,
632 bool KillSrc) const {
633 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
634 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
635
636 if (GPRDest && GPRSrc) {
637 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
638 .addReg(SrcReg, getKillRegState(KillSrc))));
639 return;
640 }
641
642 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
643 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
644
645 unsigned Opc;
646 if (SPRDest && SPRSrc)
647 Opc = ARM::VMOVS;
648 else if (GPRDest && SPRSrc)
649 Opc = ARM::VMOVRS;
650 else if (SPRDest && GPRSrc)
651 Opc = ARM::VMOVSR;
652 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
653 Opc = ARM::VMOVD;
654 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
655 Opc = ARM::VMOVQ;
656 else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
657 Opc = ARM::VMOVQQ;
658 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
659 Opc = ARM::VMOVQQQQ;
660 else
661 llvm_unreachable("Impossible reg-to-reg copy");
662
663 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
664 MIB.addReg(SrcReg, getKillRegState(KillSrc));
665 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
666 AddDefaultPred(MIB);
667 }
668
669 static const
670 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
671 unsigned Reg, unsigned SubIdx, unsigned State,
672 const TargetRegisterInfo *TRI) {
673 if (!SubIdx)
674 return MIB.addReg(Reg, State);
675
676 if (TargetRegisterInfo::isPhysicalRegister(Reg))
677 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
678 return MIB.addReg(Reg, State, SubIdx);
679 }
680
681 void ARMBaseInstrInfo::
682 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
683 unsigned SrcReg, bool isKill, int FI,
684 const TargetRegisterClass *RC,
685 const TargetRegisterInfo *TRI) const {
686 DebugLoc DL;
687 if (I != MBB.end()) DL = I->getDebugLoc();
688 MachineFunction &MF = *MBB.getParent();
689 MachineFrameInfo &MFI = *MF.getFrameInfo();
690 unsigned Align = MFI.getObjectAlignment(FI);
691
692 MachineMemOperand *MMO =
693 MF.getMachineMemOperand(MachinePointerInfo(
694 PseudoSourceValue::getFixedStack(FI)),
695 MachineMemOperand::MOStore,
696 MFI.getObjectSize(FI),
697 Align);
698
699 // tGPR is used sometimes in ARM instructions that need to avoid using
700 // certain registers. Just treat it as GPR here. Likewise, rGPR.
701 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
702 || RC == ARM::rGPRRegisterClass)
703 RC = ARM::GPRRegisterClass;
704
705 switch (RC->getID()) {
706 case ARM::GPRRegClassID:
707 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
708 .addReg(SrcReg, getKillRegState(isKill))
709 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
710 break;
711 case ARM::SPRRegClassID:
712 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
713 .addReg(SrcReg, getKillRegState(isKill))
714 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
715 break;
716 case ARM::DPRRegClassID:
717 case ARM::DPR_VFP2RegClassID:
718 case ARM::DPR_8RegClassID:
719 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
720 .addReg(SrcReg, getKillRegState(isKill))
721 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
722 break;
723 case ARM::QPRRegClassID:
724 case ARM::QPR_VFP2RegClassID:
725 case ARM::QPR_8RegClassID:
726 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
727 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
728 .addFrameIndex(FI).addImm(16)
729 .addReg(SrcReg, getKillRegState(isKill))
730 .addMemOperand(MMO));
731 } else {
732 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
733 .addReg(SrcReg, getKillRegState(isKill))
734 .addFrameIndex(FI)
735 .addMemOperand(MMO));
736 }
737 break;
738 case ARM::QQPRRegClassID:
739 case ARM::QQPR_VFP2RegClassID:
740 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
741 // FIXME: It's possible to only store part of the QQ register if the
742 // spilled def has a sub-register index.
743 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
744 .addFrameIndex(FI).addImm(16)
745 .addReg(SrcReg, getKillRegState(isKill))
746 .addMemOperand(MMO));
747 } else {
748 MachineInstrBuilder MIB =
749 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
750 .addFrameIndex(FI))
751 .addMemOperand(MMO);
752 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
753 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
754 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
755 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
756 }
757 break;
758 case ARM::QQQQPRRegClassID: {
759 MachineInstrBuilder MIB =
760 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
761 .addFrameIndex(FI))
762 .addMemOperand(MMO);
763 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
764 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
765 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
766 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
767 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
768 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
769 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
770 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
771 break;
772 }
773 default:
774 llvm_unreachable("Unknown regclass!");
775 }
776 }
777
778 unsigned
779 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
780 int &FrameIndex) const {
781 switch (MI->getOpcode()) {
782 default: break;
783 case ARM::STRrs:
784 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
785 if (MI->getOperand(1).isFI() &&
786 MI->getOperand(2).isReg() &&
787 MI->getOperand(3).isImm() &&
788 MI->getOperand(2).getReg() == 0 &&
789 MI->getOperand(3).getImm() == 0) {
790 FrameIndex = MI->getOperand(1).getIndex();
791 return MI->getOperand(0).getReg();
792 }
793 break;
794 case ARM::STRi12:
795 case ARM::t2STRi12:
796 case ARM::tSTRspi:
797 case ARM::VSTRD:
798 case ARM::VSTRS:
799 if (MI->getOperand(1).isFI() &&
800 MI->getOperand(2).isImm() &&
801 MI->getOperand(2).getImm() == 0) {
802 FrameIndex = MI->getOperand(1).getIndex();
803 return MI->getOperand(0).getReg();
804 }
805 break;
806 case ARM::VST1q64Pseudo:
807 if (MI->getOperand(0).isFI() &&
808 MI->getOperand(2).getSubReg() == 0) {
809 FrameIndex = MI->getOperand(0).getIndex();
810 return MI->getOperand(2).getReg();
811 }
812 break;
813 case ARM::VSTMQIA:
814 if (MI->getOperand(1).isFI() &&
815 MI->getOperand(0).getSubReg() == 0) {
816 FrameIndex = MI->getOperand(1).getIndex();
817 return MI->getOperand(0).getReg();
818 }
819 break;
820 }
821
822 return 0;
823 }
824
825 void ARMBaseInstrInfo::
826 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
827 unsigned DestReg, int FI,
828 const TargetRegisterClass *RC,
829 const TargetRegisterInfo *TRI) const {
830 DebugLoc DL;
831 if (I != MBB.end()) DL = I->getDebugLoc();
832 MachineFunction &MF = *MBB.getParent();
833 MachineFrameInfo &MFI = *MF.getFrameInfo();
834 unsigned Align = MFI.getObjectAlignment(FI);
835 MachineMemOperand *MMO =
836 MF.getMachineMemOperand(
837 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
838 MachineMemOperand::MOLoad,
839 MFI.getObjectSize(FI),
840 Align);
841
842 // tGPR is used sometimes in ARM instructions that need to avoid using
843 // certain registers. Just treat it as GPR here.
844 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
845 || RC == ARM::rGPRRegisterClass)
846 RC = ARM::GPRRegisterClass;
847
848 switch (RC->getID()) {
849 case ARM::GPRRegClassID:
850 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
851 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
852 break;
853 case ARM::SPRRegClassID:
854 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
855 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
856 break;
857 case ARM::DPRRegClassID:
858 case ARM::DPR_VFP2RegClassID:
859 case ARM::DPR_8RegClassID:
860 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
861 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
862 break;
863 case ARM::QPRRegClassID:
864 case ARM::QPR_VFP2RegClassID:
865 case ARM::QPR_8RegClassID:
866 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
867 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
868 .addFrameIndex(FI).addImm(16)
869 .addMemOperand(MMO));
870 } else {
871 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
872 .addFrameIndex(FI)
873 .addMemOperand(MMO));
874 }
875 break;
876 case ARM::QQPRRegClassID:
877 case ARM::QQPR_VFP2RegClassID:
878 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
879 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
880 .addFrameIndex(FI).addImm(16)
881 .addMemOperand(MMO));
882 } else {
883 MachineInstrBuilder MIB =
884 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
885 .addFrameIndex(FI))
886 .addMemOperand(MMO);
887 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
888 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
889 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
890 AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
891 }
892 break;
893 case ARM::QQQQPRRegClassID: {
894 MachineInstrBuilder MIB =
895 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
896 .addFrameIndex(FI))
897 .addMemOperand(MMO);
898 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
899 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
900 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
901 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
902 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
903 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
904 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
905 AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
906 break;
907 }
908 default:
909 llvm_unreachable("Unknown regclass!");
910 }
911 }
912
913 unsigned
914 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
915 int &FrameIndex) const {
916 switch (MI->getOpcode()) {
917 default: break;
918 case ARM::LDRrs:
919 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
920 if (MI->getOperand(1).isFI() &&
921 MI->getOperand(2).isReg() &&
922 MI->getOperand(3).isImm() &&
923 MI->getOperand(2).getReg() == 0 &&
924 MI->getOperand(3).getImm() == 0) {
925 FrameIndex = MI->getOperand(1).getIndex();
926 return MI->getOperand(0).getReg();
927 }
928 break;
929 case ARM::LDRi12:
930 case ARM::t2LDRi12:
931 case ARM::tLDRspi:
932 case ARM::VLDRD:
933 case ARM::VLDRS:
934 if (MI->getOperand(1).isFI() &&
935 MI->getOperand(2).isImm() &&
936 MI->getOperand(2).getImm() == 0) {
937 FrameIndex = MI->getOperand(1).getIndex();
938 return MI->getOperand(0).getReg();
939 }
940 break;
941 case ARM::VLD1q64Pseudo:
942 if (MI->getOperand(1).isFI() &&
943 MI->getOperand(0).getSubReg() == 0) {
944 FrameIndex = MI->getOperand(1).getIndex();
945 return MI->getOperand(0).getReg();
946 }
947 break;
948 case ARM::VLDMQIA:
949 if (MI->getOperand(1).isFI() &&
950 MI->getOperand(0).getSubReg() == 0) {
951 FrameIndex = MI->getOperand(1).getIndex();
952 return MI->getOperand(0).getReg();
953 }
954 break;
955 }
956
957 return 0;
958 }
959
960 MachineInstr*
961 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
962 int FrameIx, uint64_t Offset,
963 const MDNode *MDPtr,
964 DebugLoc DL) const {
965 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
966 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
967 return &*MIB;
968 }
969
970 /// Create a copy of a const pool value. Update CPI to the new index and return
971 /// the label UID.
972 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
973 MachineConstantPool *MCP = MF.getConstantPool();
974 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
975
976 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
977 assert(MCPE.isMachineConstantPoolEntry() &&
978 "Expecting a machine constantpool entry!");
979 ARMConstantPoolValue *ACPV =
980 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
981
982 unsigned PCLabelId = AFI->createPICLabelUId();
983 ARMConstantPoolValue *NewCPV = 0;
984 // FIXME: The below assumes PIC relocation model and that the function
985 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
986 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
987 // instructions, so that's probably OK, but is PIC always correct when
988 // we get here?
989 if (ACPV->isGlobalValue())
990 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
991 ARMCP::CPValue, 4);
992 else if (ACPV->isExtSymbol())
993 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
994 ACPV->getSymbol(), PCLabelId, 4);
995 else if (ACPV->isBlockAddress())
996 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
997 ARMCP::CPBlockAddress, 4);
998 else if (ACPV->isLSDA())
999 NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
1000 ARMCP::CPLSDA, 4);
1001 else
1002 llvm_unreachable("Unexpected ARM constantpool value type!!");
1003 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1004 return PCLabelId;
1005 }
1006
1007 void ARMBaseInstrInfo::
1008 reMaterialize(MachineBasicBlock &MBB,
1009 MachineBasicBlock::iterator I,
1010 unsigned DestReg, unsigned SubIdx,
1011 const MachineInstr *Orig,
1012 const TargetRegisterInfo &TRI) const {
1013 unsigned Opcode = Orig->getOpcode();
1014 switch (Opcode) {
1015 default: {
1016 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1017 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1018 MBB.insert(I, MI);
1019 break;
1020 }
1021 case ARM::tLDRpci_pic:
1022 case ARM::t2LDRpci_pic: {
1023 MachineFunction &MF = *MBB.getParent();
1024 unsigned CPI = Orig->getOperand(1).getIndex();
1025 unsigned PCLabelId = duplicateCPV(MF, CPI);
1026 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1027 DestReg)
1028 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1029 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1030 break;
1031 }
1032 }
1033 }
1034
1035 MachineInstr *
1036 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1037 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1038 switch(Orig->getOpcode()) {
1039 case ARM::tLDRpci_pic:
1040 case ARM::t2LDRpci_pic: {
1041 unsigned CPI = Orig->getOperand(1).getIndex();
1042 unsigned PCLabelId = duplicateCPV(MF, CPI);
1043 Orig->getOperand(1).setIndex(CPI);
1044 Orig->getOperand(2).setImm(PCLabelId);
1045 break;
1046 }
1047 }
1048 return MI;
1049 }
1050
1051 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1052 const MachineInstr *MI1,
1053 const MachineRegisterInfo *MRI) const {
1054 int Opcode = MI0->getOpcode();
1055 if (Opcode == ARM::t2LDRpci ||
1056 Opcode == ARM::t2LDRpci_pic ||
1057 Opcode == ARM::tLDRpci ||
1058 Opcode == ARM::tLDRpci_pic ||
1059 Opcode == ARM::MOV_ga_dyn ||
1060 Opcode == ARM::MOV_ga_pcrel ||
1061 Opcode == ARM::MOV_ga_pcrel_ldr ||
1062 Opcode == ARM::t2MOV_ga_dyn ||
1063 Opcode == ARM::t2MOV_ga_pcrel) {
1064 if (MI1->getOpcode() != Opcode)
1065 return false;
1066 if (MI0->getNumOperands() != MI1->getNumOperands())
1067 return false;
1068
1069 const MachineOperand &MO0 = MI0->getOperand(1);
1070 const MachineOperand &MO1 = MI1->getOperand(1);
1071 if (MO0.getOffset() != MO1.getOffset())
1072 return false;
1073
1074 if (Opcode == ARM::MOV_ga_dyn ||
1075 Opcode == ARM::MOV_ga_pcrel ||
1076 Opcode == ARM::MOV_ga_pcrel_ldr ||
1077 Opcode == ARM::t2MOV_ga_dyn ||
1078 Opcode == ARM::t2MOV_ga_pcrel)
1079 // Ignore the PC labels.
1080 return MO0.getGlobal() == MO1.getGlobal();
1081
1082 const MachineFunction *MF = MI0->getParent()->getParent();
1083 const MachineConstantPool *MCP = MF->getConstantPool();
1084 int CPI0 = MO0.getIndex();
1085 int CPI1 = MO1.getIndex();
1086 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1087 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1088 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1089 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1090 if (isARMCP0 && isARMCP1) {
1091 ARMConstantPoolValue *ACPV0 =
1092 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1093 ARMConstantPoolValue *ACPV1 =
1094 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1095 return ACPV0->hasSameValue(ACPV1);
1096 } else if (!isARMCP0 && !isARMCP1) {
1097 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1098 }
1099 return false;
1100 } else if (Opcode == ARM::PICLDR) {
1101 if (MI1->getOpcode() != Opcode)
1102 return false;
1103 if (MI0->getNumOperands() != MI1->getNumOperands())
1104 return false;
1105
1106 unsigned Addr0 = MI0->getOperand(1).getReg();
1107 unsigned Addr1 = MI1->getOperand(1).getReg();
1108 if (Addr0 != Addr1) {
1109 if (!MRI ||
1110 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1111 !TargetRegisterInfo::isVirtualRegister(Addr1))
1112 return false;
1113
1114 // This assumes SSA form.
1115 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1116 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1117 // Check if the loaded value, e.g. a constantpool of a global address, are
1118 // the same.
1119 if (!produceSameValue(Def0, Def1, MRI))
1120 return false;
1121 }
1122
1123 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1124 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1125 const MachineOperand &MO0 = MI0->getOperand(i);
1126 const MachineOperand &MO1 = MI1->getOperand(i);
1127 if (!MO0.isIdenticalTo(MO1))
1128 return false;
1129 }
1130 return true;
1131 }
1132
1133 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1134 }
1135
1136 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1137 /// determine if two loads are loading from the same base address. It should
1138 /// only return true if the base pointers are the same and the only differences
1139 /// between the two addresses is the offset. It also returns the offsets by
1140 /// reference.
1141 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1142 int64_t &Offset1,
1143 int64_t &Offset2) const {
1144 // Don't worry about Thumb: just ARM and Thumb2.
1145 if (Subtarget.isThumb1Only()) return false;
1146
1147 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1148 return false;
1149
1150 switch (Load1->getMachineOpcode()) {
1151 default:
1152 return false;
1153 case ARM::LDRi12:
1154 case ARM::LDRBi12:
1155 case ARM::LDRD:
1156 case ARM::LDRH:
1157 case ARM::LDRSB:
1158 case ARM::LDRSH:
1159 case ARM::VLDRD:
1160 case ARM::VLDRS:
1161 case ARM::t2LDRi8:
1162 case ARM::t2LDRDi8:
1163 case ARM::t2LDRSHi8:
1164 case ARM::t2LDRi12:
1165 case ARM::t2LDRSHi12:
1166 break;
1167 }
1168
1169 switch (Load2->getMachineOpcode()) {
1170 default:
1171 return false;
1172 case ARM::LDRi12:
1173 case ARM::LDRBi12:
1174 case ARM::LDRD:
1175 case ARM::LDRH:
1176 case ARM::LDRSB:
1177 case ARM::LDRSH:
1178 case ARM::VLDRD:
1179 case ARM::VLDRS:
1180 case ARM::t2LDRi8:
1181 case ARM::t2LDRDi8:
1182 case ARM::t2LDRSHi8:
1183 case ARM::t2LDRi12:
1184 case ARM::t2LDRSHi12:
1185 break;
1186 }
1187
1188 // Check if base addresses and chain operands match.
1189 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1190 Load1->getOperand(4) != Load2->getOperand(4))
1191 return false;
1192
1193 // Index should be Reg0.
1194 if (Load1->getOperand(3) != Load2->getOperand(3))
1195 return false;
1196
1197 // Determine the offsets.
1198 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1199 isa<ConstantSDNode>(Load2->getOperand(1))) {
1200 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1201 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1202 return true;
1203 }
1204
1205 return false;
1206 }
1207
1208 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1209 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1210 /// be scheduled togther. On some targets if two loads are loading from
1211 /// addresses in the same cache line, it's better if they are scheduled
1212 /// together. This function takes two integers that represent the load offsets
1213 /// from the common base address. It returns true if it decides it's desirable
1214 /// to schedule the two loads together. "NumLoads" is the number of loads that
1215 /// have already been scheduled after Load1.
1216 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1217 int64_t Offset1, int64_t Offset2,
1218 unsigned NumLoads) const {
1219 // Don't worry about Thumb: just ARM and Thumb2.
1220 if (Subtarget.isThumb1Only()) return false;
1221
1222 assert(Offset2 > Offset1);
1223
1224 if ((Offset2 - Offset1) / 8 > 64)
1225 return false;
1226
1227 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1228 return false; // FIXME: overly conservative?
1229
1230 // Four loads in a row should be sufficient.
1231 if (NumLoads >= 3)
1232 return false;
1233
1234 return true;
1235 }
1236
1237 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1238 const MachineBasicBlock *MBB,
1239 const MachineFunction &MF) const {
1240 // Debug info is never a scheduling boundary. It's necessary to be explicit
1241 // due to the special treatment of IT instructions below, otherwise a
1242 // dbg_value followed by an IT will result in the IT instruction being
1243 // considered a scheduling hazard, which is wrong. It should be the actual
1244 // instruction preceding the dbg_value instruction(s), just like it is
1245 // when debug info is not present.
1246 if (MI->isDebugValue())
1247 return false;
1248
1249 // Terminators and labels can't be scheduled around.
1250 if (MI->getDesc().isTerminator() || MI->isLabel())
1251 return true;
1252
1253 // Treat the start of the IT block as a scheduling boundary, but schedule
1254 // t2IT along with all instructions following it.
1255 // FIXME: This is a big hammer. But the alternative is to add all potential
1256 // true and anti dependencies to IT block instructions as implicit operands
1257 // to the t2IT instruction. The added compile time and complexity does not
1258 // seem worth it.
1259 MachineBasicBlock::const_iterator I = MI;
1260 // Make sure to skip any dbg_value instructions
1261 while (++I != MBB->end() && I->isDebugValue())
1262 ;
1263 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1264 return true;
1265
1266 // Don't attempt to schedule around any instruction that defines
1267 // a stack-oriented pointer, as it's unlikely to be profitable. This
1268 // saves compile time, because it doesn't require every single
1269 // stack slot reference to depend on the instruction that does the
1270 // modification.
1271 if (MI->definesRegister(ARM::SP))
1272 return true;
1273
1274 return false;
1275 }
1276
1277 bool ARMBaseInstrInfo::
1278 isProfitableToIfCvt(MachineBasicBlock &MBB,
1279 unsigned NumCycles, unsigned ExtraPredCycles,
1280 const BranchProbability &Probability) const {
1281 if (!NumCycles)
1282 return false;
1283
1284 // Attempt to estimate the relative costs of predication versus branching.
1285 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1286 UnpredCost /= Probability.getDenominator();
1287 UnpredCost += 1; // The branch itself
1288 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1289
1290 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1291 }
1292
1293 bool ARMBaseInstrInfo::
1294 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1295 unsigned TCycles, unsigned TExtra,
1296 MachineBasicBlock &FMBB,
1297 unsigned FCycles, unsigned FExtra,
1298 const BranchProbability &Probability) const {
1299 if (!TCycles || !FCycles)
1300 return false;
1301
1302 // Attempt to estimate the relative costs of predication versus branching.
1303 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1304 TUnpredCost /= Probability.getDenominator();
1305
1306 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1307 unsigned FUnpredCost = Comp * FCycles;
1308 FUnpredCost /= Probability.getDenominator();
1309
1310 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1311 UnpredCost += 1; // The branch itself
1312 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1313
1314 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1315 }
1316
1317 /// getInstrPredicate - If instruction is predicated, returns its predicate
1318 /// condition, otherwise returns AL. It also returns the condition code
1319 /// register by reference.
1320 ARMCC::CondCodes
1321 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1322 int PIdx = MI->findFirstPredOperandIdx();
1323 if (PIdx == -1) {
1324 PredReg = 0;
1325 return ARMCC::AL;
1326 }
1327
1328 PredReg = MI->getOperand(PIdx+1).getReg();
1329 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1330 }
1331
1332
1333 int llvm::getMatchingCondBranchOpcode(int Opc) {
1334 if (Opc == ARM::B)
1335 return ARM::Bcc;
1336 else if (Opc == ARM::tB)
1337 return ARM::tBcc;
1338 else if (Opc == ARM::t2B)
1339 return ARM::t2Bcc;
1340
1341 llvm_unreachable("Unknown unconditional branch opcode!");
1342 return 0;
1343 }
1344
1345
1346 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1347 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1348 unsigned DestReg, unsigned BaseReg, int NumBytes,
1349 ARMCC::CondCodes Pred, unsigned PredReg,
1350 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1351 bool isSub = NumBytes < 0;
1352 if (isSub) NumBytes = -NumBytes;
1353
1354 while (NumBytes) {
1355 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1356 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1357 assert(ThisVal && "Didn't extract field correctly");
1358
1359 // We will handle these bits from offset, clear them.
1360 NumBytes &= ~ThisVal;
1361
1362 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1363
1364 // Build the new ADD / SUB.
1365 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1366 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1367 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1368 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1369 .setMIFlags(MIFlags);
1370 BaseReg = DestReg;
1371 }
1372 }
1373
1374 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1375 unsigned FrameReg, int &Offset,
1376 const ARMBaseInstrInfo &TII) {
1377 unsigned Opcode = MI.getOpcode();
1378 const MCInstrDesc &Desc = MI.getDesc();
1379 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1380 bool isSub = false;
1381
1382 // Memory operands in inline assembly always use AddrMode2.
1383 if (Opcode == ARM::INLINEASM)
1384 AddrMode = ARMII::AddrMode2;
1385
1386 if (Opcode == ARM::ADDri) {
1387 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1388 if (Offset == 0) {
1389 // Turn it into a move.
1390 MI.setDesc(TII.get(ARM::MOVr));
1391 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1392 MI.RemoveOperand(FrameRegIdx+1);
1393 Offset = 0;
1394 return true;
1395 } else if (Offset < 0) {
1396 Offset = -Offset;
1397 isSub = true;
1398 MI.setDesc(TII.get(ARM::SUBri));
1399 }
1400
1401 // Common case: small offset, fits into instruction.
1402 if (ARM_AM::getSOImmVal(Offset) != -1) {
1403 // Replace the FrameIndex with sp / fp
1404 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1405 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1406 Offset = 0;
1407 return true;
1408 }
1409
1410 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1411 // as possible.
1412 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1413 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1414
1415 // We will handle these bits from offset, clear them.
1416 Offset &= ~ThisImmVal;
1417
1418 // Get the properly encoded SOImmVal field.
1419 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1420 "Bit extraction didn't work?");
1421 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1422 } else {
1423 unsigned ImmIdx = 0;
1424 int InstrOffs = 0;
1425 unsigned NumBits = 0;
1426 unsigned Scale = 1;
1427 switch (AddrMode) {
1428 case ARMII::AddrMode_i12: {
1429 ImmIdx = FrameRegIdx + 1;
1430 InstrOffs = MI.getOperand(ImmIdx).getImm();
1431 NumBits = 12;
1432 break;
1433 }
1434 case ARMII::AddrMode2: {
1435 ImmIdx = FrameRegIdx+2;
1436 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1437 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1438 InstrOffs *= -1;
1439 NumBits = 12;
1440 break;
1441 }
1442 case ARMII::AddrMode3: {
1443 ImmIdx = FrameRegIdx+2;
1444 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1445 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1446 InstrOffs *= -1;
1447 NumBits = 8;
1448 break;
1449 }
1450 case ARMII::AddrMode4:
1451 case ARMII::AddrMode6:
1452 // Can't fold any offset even if it's zero.
1453 return false;
1454 case ARMII::AddrMode5: {
1455 ImmIdx = FrameRegIdx+1;
1456 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1457 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1458 InstrOffs *= -1;
1459 NumBits = 8;
1460 Scale = 4;
1461 break;
1462 }
1463 default:
1464 llvm_unreachable("Unsupported addressing mode!");
1465 break;
1466 }
1467
1468 Offset += InstrOffs * Scale;
1469 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1470 if (Offset < 0) {
1471 Offset = -Offset;
1472 isSub = true;
1473 }
1474
1475 // Attempt to fold address comp. if opcode has offset bits
1476 if (NumBits > 0) {
1477 // Common case: small offset, fits into instruction.
1478 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1479 int ImmedOffset = Offset / Scale;
1480 unsigned Mask = (1 << NumBits) - 1;
1481 if ((unsigned)Offset <= Mask * Scale) {
1482 // Replace the FrameIndex with sp
1483 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1484 // FIXME: When addrmode2 goes away, this will simplify (like the
1485 // T2 version), as the LDR.i12 versions don't need the encoding
1486 // tricks for the offset value.
1487 if (isSub) {
1488 if (AddrMode == ARMII::AddrMode_i12)
1489 ImmedOffset = -ImmedOffset;
1490 else
1491 ImmedOffset |= 1 << NumBits;
1492 }
1493 ImmOp.ChangeToImmediate(ImmedOffset);
1494 Offset = 0;
1495 return true;
1496 }
1497
1498 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1499 ImmedOffset = ImmedOffset & Mask;
1500 if (isSub) {
1501 if (AddrMode == ARMII::AddrMode_i12)
1502 ImmedOffset = -ImmedOffset;
1503 else
1504 ImmedOffset |= 1 << NumBits;
1505 }
1506 ImmOp.ChangeToImmediate(ImmedOffset);
1507 Offset &= ~(Mask*Scale);
1508 }
1509 }
1510
1511 Offset = (isSub) ? -Offset : Offset;
1512 return Offset == 0;
1513 }
1514
1515 bool ARMBaseInstrInfo::
1516 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1517 int &CmpValue) const {
1518 switch (MI->getOpcode()) {
1519 default: break;
1520 case ARM::CMPri:
1521 case ARM::t2CMPri:
1522 SrcReg = MI->getOperand(0).getReg();
1523 CmpMask = ~0;
1524 CmpValue = MI->getOperand(1).getImm();
1525 return true;
1526 case ARM::TSTri:
1527 case ARM::t2TSTri:
1528 SrcReg = MI->getOperand(0).getReg();
1529 CmpMask = MI->getOperand(1).getImm();
1530 CmpValue = 0;
1531 return true;
1532 }
1533
1534 return false;
1535 }
1536
1537 /// isSuitableForMask - Identify a suitable 'and' instruction that
1538 /// operates on the given source register and applies the same mask
1539 /// as a 'tst' instruction. Provide a limited look-through for copies.
1540 /// When successful, MI will hold the found instruction.
1541 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1542 int CmpMask, bool CommonUse) {
1543 switch (MI->getOpcode()) {
1544 case ARM::ANDri:
1545 case ARM::t2ANDri:
1546 if (CmpMask != MI->getOperand(2).getImm())
1547 return false;
1548 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1549 return true;
1550 break;
1551 case ARM::COPY: {
1552 // Walk down one instruction which is potentially an 'and'.
1553 const MachineInstr &Copy = *MI;
1554 MachineBasicBlock::iterator AND(
1555 llvm::next(MachineBasicBlock::iterator(MI)));
1556 if (AND == MI->getParent()->end()) return false;
1557 MI = AND;
1558 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1559 CmpMask, true);
1560 }
1561 }
1562
1563 return false;
1564 }
1565
1566 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1567 /// comparison into one that sets the zero bit in the flags register.
1568 bool ARMBaseInstrInfo::
1569 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1570 int CmpValue, const MachineRegisterInfo *MRI) const {
1571 if (CmpValue != 0)
1572 return false;
1573
1574 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1575 if (llvm::next(DI) != MRI->def_end())
1576 // Only support one definition.
1577 return false;
1578
1579 MachineInstr *MI = &*DI;
1580
1581 // Masked compares sometimes use the same register as the corresponding 'and'.
1582 if (CmpMask != ~0) {
1583 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1584 MI = 0;
1585 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1586 UE = MRI->use_end(); UI != UE; ++UI) {
1587 if (UI->getParent() != CmpInstr->getParent()) continue;
1588 MachineInstr *PotentialAND = &*UI;
1589 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1590 continue;
1591 MI = PotentialAND;
1592 break;
1593 }
1594 if (!MI) return false;
1595 }
1596 }
1597
1598 // Conservatively refuse to convert an instruction which isn't in the same BB
1599 // as the comparison.
1600 if (MI->getParent() != CmpInstr->getParent())
1601 return false;
1602
1603 // Check that CPSR isn't set between the comparison instruction and the one we
1604 // want to change.
1605 MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1606 B = MI->getParent()->begin();
1607
1608 // Early exit if CmpInstr is at the beginning of the BB.
1609 if (I == B) return false;
1610
1611 --I;
1612 for (; I != E; --I) {
1613 const MachineInstr &Instr = *I;
1614
1615 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1616 const MachineOperand &MO = Instr.getOperand(IO);
1617 if (!MO.isReg()) continue;
1618
1619 // This instruction modifies or uses CPSR after the one we want to
1620 // change. We can't do this transformation.
1621 if (MO.getReg() == ARM::CPSR)
1622 return false;
1623 }
1624
1625 if (I == B)
1626 // The 'and' is below the comparison instruction.
1627 return false;
1628 }
1629
1630 // Set the "zero" bit in CPSR.
1631 switch (MI->getOpcode()) {
1632 default: break;
1633 case ARM::RSBrr:
1634 case ARM::RSBri:
1635 case ARM::RSCrr:
1636 case ARM::RSCri:
1637 case ARM::ADDrr:
1638 case ARM::ADDri:
1639 case ARM::ADCrr:
1640 case ARM::ADCri:
1641 case ARM::SUBrr:
1642 case ARM::SUBri:
1643 case ARM::SBCrr:
1644 case ARM::SBCri:
1645 case ARM::t2RSBri:
1646 case ARM::t2ADDrr:
1647 case ARM::t2ADDri:
1648 case ARM::t2ADCrr:
1649 case ARM::t2ADCri:
1650 case ARM::t2SUBrr:
1651 case ARM::t2SUBri:
1652 case ARM::t2SBCrr:
1653 case ARM::t2SBCri:
1654 case ARM::ANDrr:
1655 case ARM::ANDri:
1656 case ARM::t2ANDrr:
1657 case ARM::t2ANDri:
1658 case ARM::ORRrr:
1659 case ARM::ORRri:
1660 case ARM::t2ORRrr:
1661 case ARM::t2ORRri:
1662 case ARM::EORrr:
1663 case ARM::EORri:
1664 case ARM::t2EORrr:
1665 case ARM::t2EORri: {
1666 // Scan forward for the use of CPSR, if it's a conditional code requires
1667 // checking of V bit, then this is not safe to do. If we can't find the
1668 // CPSR use (i.e. used in another block), then it's not safe to perform
1669 // the optimization.
1670 bool isSafe = false;
1671 I = CmpInstr;
1672 E = MI->getParent()->end();
1673 while (!isSafe && ++I != E) {
1674 const MachineInstr &Instr = *I;
1675 for (unsigned IO = 0, EO = Instr.getNumOperands();
1676 !isSafe && IO != EO; ++IO) {
1677 const MachineOperand &MO = Instr.getOperand(IO);
1678 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1679 continue;
1680 if (MO.isDef()) {
1681 isSafe = true;
1682 break;
1683 }
1684 // Condition code is after the operand before CPSR.
1685 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1686 switch (CC) {
1687 default:
1688 isSafe = true;
1689 break;
1690 case ARMCC::VS:
1691 case ARMCC::VC:
1692 case ARMCC::GE:
1693 case ARMCC::LT:
1694 case ARMCC::GT:
1695 case ARMCC::LE:
1696 return false;
1697 }
1698 }
1699 }
1700
1701 if (!isSafe)
1702 return false;
1703
1704 // Toggle the optional operand to CPSR.
1705 MI->getOperand(5).setReg(ARM::CPSR);
1706 MI->getOperand(5).setIsDef(true);
1707 CmpInstr->eraseFromParent();
1708 return true;
1709 }
1710 }
1711
1712 return false;
1713 }
1714
1715 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1716 MachineInstr *DefMI, unsigned Reg,
1717 MachineRegisterInfo *MRI) const {
1718 // Fold large immediates into add, sub, or, xor.
1719 unsigned DefOpc = DefMI->getOpcode();
1720 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1721 return false;
1722 if (!DefMI->getOperand(1).isImm())
1723 // Could be t2MOVi32imm <ga:xx>
1724 return false;
1725
1726 if (!MRI->hasOneNonDBGUse(Reg))
1727 return false;
1728
1729 unsigned UseOpc = UseMI->getOpcode();
1730 unsigned NewUseOpc = 0;
1731 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1732 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1733 bool Commute = false;
1734 switch (UseOpc) {
1735 default: return false;
1736 case ARM::SUBrr:
1737 case ARM::ADDrr:
1738 case ARM::ORRrr:
1739 case ARM::EORrr:
1740 case ARM::t2SUBrr:
1741 case ARM::t2ADDrr:
1742 case ARM::t2ORRrr:
1743 case ARM::t2EORrr: {
1744 Commute = UseMI->getOperand(2).getReg() != Reg;
1745 switch (UseOpc) {
1746 default: break;
1747 case ARM::SUBrr: {
1748 if (Commute)
1749 return false;
1750 ImmVal = -ImmVal;
1751 NewUseOpc = ARM::SUBri;
1752 // Fallthrough
1753 }
1754 case ARM::ADDrr:
1755 case ARM::ORRrr:
1756 case ARM::EORrr: {
1757 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1758 return false;
1759 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1760 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1761 switch (UseOpc) {
1762 default: break;
1763 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1764 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1765 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1766 }
1767 break;
1768 }
1769 case ARM::t2SUBrr: {
1770 if (Commute)
1771 return false;
1772 ImmVal = -ImmVal;
1773 NewUseOpc = ARM::t2SUBri;
1774 // Fallthrough
1775 }
1776 case ARM::t2ADDrr:
1777 case ARM::t2ORRrr:
1778 case ARM::t2EORrr: {
1779 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1780 return false;
1781 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1782 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1783 switch (UseOpc) {
1784 default: break;
1785 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1786 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1787 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1788 }
1789 break;
1790 }
1791 }
1792 }
1793 }
1794
1795 unsigned OpIdx = Commute ? 2 : 1;
1796 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1797 bool isKill = UseMI->getOperand(OpIdx).isKill();
1798 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1799 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1800 *UseMI, UseMI->getDebugLoc(),
1801 get(NewUseOpc), NewReg)
1802 .addReg(Reg1, getKillRegState(isKill))
1803 .addImm(SOImmValV1)));
1804 UseMI->setDesc(get(NewUseOpc));
1805 UseMI->getOperand(1).setReg(NewReg);
1806 UseMI->getOperand(1).setIsKill();
1807 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1808 DefMI->eraseFromParent();
1809 return true;
1810 }
1811
1812 unsigned
1813 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1814 const MachineInstr *MI) const {
1815 if (!ItinData || ItinData->isEmpty())
1816 return 1;
1817
1818 const MCInstrDesc &Desc = MI->getDesc();
1819 unsigned Class = Desc.getSchedClass();
1820 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1821 if (UOps)
1822 return UOps;
1823
1824 unsigned Opc = MI->getOpcode();
1825 switch (Opc) {
1826 default:
1827 llvm_unreachable("Unexpected multi-uops instruction!");
1828 break;
1829 case ARM::VLDMQIA:
1830 case ARM::VSTMQIA:
1831 return 2;
1832
1833 // The number of uOps for load / store multiple are determined by the number
1834 // registers.
1835 //
1836 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1837 // same cycle. The scheduling for the first load / store must be done
1838 // separately by assuming the the address is not 64-bit aligned.
1839 //
1840 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1841 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
1842 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
1843 case ARM::VLDMDIA:
1844 case ARM::VLDMDIA_UPD:
1845 case ARM::VLDMDDB_UPD:
1846 case ARM::VLDMSIA:
1847 case ARM::VLDMSIA_UPD:
1848 case ARM::VLDMSDB_UPD:
1849 case ARM::VSTMDIA:
1850 case ARM::VSTMDIA_UPD:
1851 case ARM::VSTMDDB_UPD:
1852 case ARM::VSTMSIA:
1853 case ARM::VSTMSIA_UPD:
1854 case ARM::VSTMSDB_UPD: {
1855 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1856 return (NumRegs / 2) + (NumRegs % 2) + 1;
1857 }
1858
1859 case ARM::LDMIA_RET:
1860 case ARM::LDMIA:
1861 case ARM::LDMDA:
1862 case ARM::LDMDB:
1863 case ARM::LDMIB:
1864 case ARM::LDMIA_UPD:
1865 case ARM::LDMDA_UPD:
1866 case ARM::LDMDB_UPD:
1867 case ARM::LDMIB_UPD:
1868 case ARM::STMIA:
1869 case ARM::STMDA:
1870 case ARM::STMDB:
1871 case ARM::STMIB:
1872 case ARM::STMIA_UPD:
1873 case ARM::STMDA_UPD:
1874 case ARM::STMDB_UPD:
1875 case ARM::STMIB_UPD:
1876 case ARM::tLDMIA:
1877 case ARM::tLDMIA_UPD:
1878 case ARM::tSTMIA:
1879 case ARM::tSTMIA_UPD:
1880 case ARM::tPOP_RET:
1881 case ARM::tPOP:
1882 case ARM::tPUSH:
1883 case ARM::t2LDMIA_RET:
1884 case ARM::t2LDMIA:
1885 case ARM::t2LDMDB:
1886 case ARM::t2LDMIA_UPD:
1887 case ARM::t2LDMDB_UPD:
1888 case ARM::t2STMIA:
1889 case ARM::t2STMDB:
1890 case ARM::t2STMIA_UPD:
1891 case ARM::t2STMDB_UPD: {
1892 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
1893 if (Subtarget.isCortexA8()) {
1894 if (NumRegs < 4)
1895 return 2;
1896 // 4 registers would be issued: 2, 2.
1897 // 5 registers would be issued: 2, 2, 1.
1898 UOps = (NumRegs / 2);
1899 if (NumRegs % 2)
1900 ++UOps;
1901 return UOps;
1902 } else if (Subtarget.isCortexA9()) {
1903 UOps = (NumRegs / 2);
1904 // If there are odd number of registers or if it's not 64-bit aligned,
1905 // then it takes an extra AGU (Address Generation Unit) cycle.
1906 if ((NumRegs % 2) ||
1907 !MI->hasOneMemOperand() ||
1908 (*MI->memoperands_begin())->getAlignment() < 8)
1909 ++UOps;
1910 return UOps;
1911 } else {
1912 // Assume the worst.
1913 return NumRegs;
1914 }
1915 }
1916 }
1917 }
1918
1919 int
1920 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
1921 const MCInstrDesc &DefMCID,
1922 unsigned DefClass,
1923 unsigned DefIdx, unsigned DefAlign) const {
1924 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
1925 if (RegNo <= 0)
1926 // Def is the address writeback.
1927 return ItinData->getOperandCycle(DefClass, DefIdx);
1928
1929 int DefCycle;
1930 if (Subtarget.isCortexA8()) {
1931 // (regno / 2) + (regno % 2) + 1
1932 DefCycle = RegNo / 2 + 1;
1933 if (RegNo % 2)
1934 ++DefCycle;
1935 } else if (Subtarget.isCortexA9()) {
1936 DefCycle = RegNo;
1937 bool isSLoad = false;
1938
1939 switch (DefMCID.getOpcode()) {
1940 default: break;
1941 case ARM::VLDMSIA:
1942 case ARM::VLDMSIA_UPD:
1943 case ARM::VLDMSDB_UPD:
1944 isSLoad = true;
1945 break;
1946 }
1947
1948 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1949 // then it takes an extra cycle.
1950 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
1951 ++DefCycle;
1952 } else {
1953 // Assume the worst.
1954 DefCycle = RegNo + 2;
1955 }
1956
1957 return DefCycle;
1958 }
1959
1960 int
1961 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
1962 const MCInstrDesc &DefMCID,
1963 unsigned DefClass,
1964 unsigned DefIdx, unsigned DefAlign) const {
1965 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
1966 if (RegNo <= 0)
1967 // Def is the address writeback.
1968 return ItinData->getOperandCycle(DefClass, DefIdx);
1969
1970 int DefCycle;
1971 if (Subtarget.isCortexA8()) {
1972 // 4 registers would be issued: 1, 2, 1.
1973 // 5 registers would be issued: 1, 2, 2.
1974 DefCycle = RegNo / 2;
1975 if (DefCycle < 1)
1976 DefCycle = 1;
1977 // Result latency is issue cycle + 2: E2.
1978 DefCycle += 2;
1979 } else if (Subtarget.isCortexA9()) {
1980 DefCycle = (RegNo / 2);
1981 // If there are odd number of registers or if it's not 64-bit aligned,
1982 // then it takes an extra AGU (Address Generation Unit) cycle.
1983 if ((RegNo % 2) || DefAlign < 8)
1984 ++DefCycle;
1985 // Result latency is AGU cycles + 2.
1986 DefCycle += 2;
1987 } else {
1988 // Assume the worst.
1989 DefCycle = RegNo + 2;
1990 }
1991
1992 return DefCycle;
1993 }
1994
1995 int
1996 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
1997 const MCInstrDesc &UseMCID,
1998 unsigned UseClass,
1999 unsigned UseIdx, unsigned UseAlign) const {
2000 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2001 if (RegNo <= 0)
2002 return ItinData->getOperandCycle(UseClass, UseIdx);
2003
2004 int UseCycle;
2005 if (Subtarget.isCortexA8()) {
2006 // (regno / 2) + (regno % 2) + 1
2007 UseCycle = RegNo / 2 + 1;
2008 if (RegNo % 2)
2009 ++UseCycle;
2010 } else if (Subtarget.isCortexA9()) {
2011 UseCycle = RegNo;
2012 bool isSStore = false;
2013
2014 switch (UseMCID.getOpcode()) {
2015 default: break;
2016 case ARM::VSTMSIA:
2017 case ARM::VSTMSIA_UPD:
2018 case ARM::VSTMSDB_UPD:
2019 isSStore = true;
2020 break;
2021 }
2022
2023 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2024 // then it takes an extra cycle.
2025 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2026 ++UseCycle;
2027 } else {
2028 // Assume the worst.
2029 UseCycle = RegNo + 2;
2030 }
2031
2032 return UseCycle;
2033 }
2034
2035 int
2036 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2037 const MCInstrDesc &UseMCID,
2038 unsigned UseClass,
2039 unsigned UseIdx, unsigned UseAlign) const {
2040 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2041 if (RegNo <= 0)
2042 return ItinData->getOperandCycle(UseClass, UseIdx);
2043
2044 int UseCycle;
2045 if (Subtarget.isCortexA8()) {
2046 UseCycle = RegNo / 2;
2047 if (UseCycle < 2)
2048 UseCycle = 2;
2049 // Read in E3.
2050 UseCycle += 2;
2051 } else if (Subtarget.isCortexA9()) {
2052 UseCycle = (RegNo / 2);
2053 // If there are odd number of registers or if it's not 64-bit aligned,
2054 // then it takes an extra AGU (Address Generation Unit) cycle.
2055 if ((RegNo % 2) || UseAlign < 8)
2056 ++UseCycle;
2057 } else {
2058 // Assume the worst.
2059 UseCycle = 1;
2060 }
2061 return UseCycle;
2062 }
2063
2064 int
2065 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2066 const MCInstrDesc &DefMCID,
2067 unsigned DefIdx, unsigned DefAlign,
2068 const MCInstrDesc &UseMCID,
2069 unsigned UseIdx, unsigned UseAlign) const {
2070 unsigned DefClass = DefMCID.getSchedClass();
2071 unsigned UseClass = UseMCID.getSchedClass();
2072
2073 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2074 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2075
2076 // This may be a def / use of a variable_ops instruction, the operand
2077 // latency might be determinable dynamically. Let the target try to
2078 // figure it out.
2079 int DefCycle = -1;
2080 bool LdmBypass = false;
2081 switch (DefMCID.getOpcode()) {
2082 default:
2083 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2084 break;
2085
2086 case ARM::VLDMDIA:
2087 case ARM::VLDMDIA_UPD:
2088 case ARM::VLDMDDB_UPD:
2089 case ARM::VLDMSIA:
2090 case ARM::VLDMSIA_UPD:
2091 case ARM::VLDMSDB_UPD:
2092 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2093 break;
2094
2095 case ARM::LDMIA_RET:
2096 case ARM::LDMIA:
2097 case ARM::LDMDA:
2098 case ARM::LDMDB:
2099 case ARM::LDMIB:
2100 case ARM::LDMIA_UPD:
2101 case ARM::LDMDA_UPD:
2102 case ARM::LDMDB_UPD:
2103 case ARM::LDMIB_UPD:
2104 case ARM::tLDMIA:
2105 case ARM::tLDMIA_UPD:
2106 case ARM::tPUSH:
2107 case ARM::t2LDMIA_RET:
2108 case ARM::t2LDMIA:
2109 case ARM::t2LDMDB:
2110 case ARM::t2LDMIA_UPD:
2111 case ARM::t2LDMDB_UPD:
2112 LdmBypass = 1;
2113 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2114 break;
2115 }
2116
2117 if (DefCycle == -1)
2118 // We can't seem to determine the result latency of the def, assume it's 2.
2119 DefCycle = 2;
2120
2121 int UseCycle = -1;
2122 switch (UseMCID.getOpcode()) {
2123 default:
2124 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2125 break;
2126
2127 case ARM::VSTMDIA:
2128 case ARM::VSTMDIA_UPD:
2129 case ARM::VSTMDDB_UPD:
2130 case ARM::VSTMSIA:
2131 case ARM::VSTMSIA_UPD:
2132 case ARM::VSTMSDB_UPD:
2133 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2134 break;
2135
2136 case ARM::STMIA:
2137 case ARM::STMDA:
2138 case ARM::STMDB:
2139 case ARM::STMIB:
2140 case ARM::STMIA_UPD:
2141 case ARM::STMDA_UPD:
2142 case ARM::STMDB_UPD:
2143 case ARM::STMIB_UPD:
2144 case ARM::tSTMIA:
2145 case ARM::tSTMIA_UPD:
2146 case ARM::tPOP_RET:
2147 case ARM::tPOP:
2148 case ARM::t2STMIA:
2149 case ARM::t2STMDB:
2150 case ARM::t2STMIA_UPD:
2151 case ARM::t2STMDB_UPD:
2152 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2153 break;
2154 }
2155
2156 if (UseCycle == -1)
2157 // Assume it's read in the first stage.
2158 UseCycle = 1;
2159
2160 UseCycle = DefCycle - UseCycle + 1;
2161 if (UseCycle > 0) {
2162 if (LdmBypass) {
2163 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2164 // first def operand.
2165 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2166 UseClass, UseIdx))
2167 --UseCycle;
2168 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2169 UseClass, UseIdx)) {
2170 --UseCycle;
2171 }
2172 }
2173
2174 return UseCycle;
2175 }
2176
2177 int
2178 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2179 const MachineInstr *DefMI, unsigned DefIdx,
2180 const MachineInstr *UseMI, unsigned UseIdx) const {
2181 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2182 DefMI->isRegSequence() || DefMI->isImplicitDef())
2183 return 1;
2184
2185 const MCInstrDesc &DefMCID = DefMI->getDesc();
2186 if (!ItinData || ItinData->isEmpty())
2187 return DefMCID.mayLoad() ? 3 : 1;
2188
2189 const MCInstrDesc &UseMCID = UseMI->getDesc();
2190 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2191 if (DefMO.getReg() == ARM::CPSR) {
2192 if (DefMI->getOpcode() == ARM::FMSTAT) {
2193 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2194 return Subtarget.isCortexA9() ? 1 : 20;
2195 }
2196
2197 // CPSR set and branch can be paired in the same cycle.
2198 if (UseMCID.isBranch())
2199 return 0;
2200 }
2201
2202 unsigned DefAlign = DefMI->hasOneMemOperand()
2203 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2204 unsigned UseAlign = UseMI->hasOneMemOperand()
2205 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2206 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2207 UseMCID, UseIdx, UseAlign);
2208
2209 if (Latency > 1 &&
2210 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2211 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2212 // variants are one cycle cheaper.
2213 switch (DefMCID.getOpcode()) {
2214 default: break;
2215 case ARM::LDRrs:
2216 case ARM::LDRBrs: {
2217 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2218 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2219 if (ShImm == 0 ||
2220 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2221 --Latency;
2222 break;
2223 }
2224 case ARM::t2LDRs:
2225 case ARM::t2LDRBs:
2226 case ARM::t2LDRHs:
2227 case ARM::t2LDRSHs: {
2228 // Thumb2 mode: lsl only.
2229 unsigned ShAmt = DefMI->getOperand(3).getImm();
2230 if (ShAmt == 0 || ShAmt == 2)
2231 --Latency;
2232 break;
2233 }
2234 }
2235 }
2236
2237 if (DefAlign < 8 && Subtarget.isCortexA9())
2238 switch (DefMCID.getOpcode()) {
2239 default: break;
2240 case ARM::VLD1q8:
2241 case ARM::VLD1q16:
2242 case ARM::VLD1q32:
2243 case ARM::VLD1q64:
2244 case ARM::VLD1q8_UPD:
2245 case ARM::VLD1q16_UPD:
2246 case ARM::VLD1q32_UPD:
2247 case ARM::VLD1q64_UPD:
2248 case ARM::VLD2d8:
2249 case ARM::VLD2d16:
2250 case ARM::VLD2d32:
2251 case ARM::VLD2q8:
2252 case ARM::VLD2q16:
2253 case ARM::VLD2q32:
2254 case ARM::VLD2d8_UPD:
2255 case ARM::VLD2d16_UPD:
2256 case ARM::VLD2d32_UPD:
2257 case ARM::VLD2q8_UPD:
2258 case ARM::VLD2q16_UPD:
2259 case ARM::VLD2q32_UPD:
2260 case ARM::VLD3d8:
2261 case ARM::VLD3d16:
2262 case ARM::VLD3d32:
2263 case ARM::VLD1d64T:
2264 case ARM::VLD3d8_UPD:
2265 case ARM::VLD3d16_UPD:
2266 case ARM::VLD3d32_UPD:
2267 case ARM::VLD1d64T_UPD:
2268 case ARM::VLD3q8_UPD:
2269 case ARM::VLD3q16_UPD:
2270 case ARM::VLD3q32_UPD:
2271 case ARM::VLD4d8:
2272 case ARM::VLD4d16:
2273 case ARM::VLD4d32:
2274 case ARM::VLD1d64Q:
2275 case ARM::VLD4d8_UPD:
2276 case ARM::VLD4d16_UPD:
2277 case ARM::VLD4d32_UPD:
2278 case ARM::VLD1d64Q_UPD:
2279 case ARM::VLD4q8_UPD:
2280 case ARM::VLD4q16_UPD:
2281 case ARM::VLD4q32_UPD:
2282 case ARM::VLD1DUPq8:
2283 case ARM::VLD1DUPq16:
2284 case ARM::VLD1DUPq32:
2285 case ARM::VLD1DUPq8_UPD:
2286 case ARM::VLD1DUPq16_UPD:
2287 case ARM::VLD1DUPq32_UPD:
2288 case ARM::VLD2DUPd8:
2289 case ARM::VLD2DUPd16:
2290 case ARM::VLD2DUPd32:
2291 case ARM::VLD2DUPd8_UPD:
2292 case ARM::VLD2DUPd16_UPD:
2293 case ARM::VLD2DUPd32_UPD:
2294 case ARM::VLD4DUPd8:
2295 case ARM::VLD4DUPd16:
2296 case ARM::VLD4DUPd32:
2297 case ARM::VLD4DUPd8_UPD:
2298 case ARM::VLD4DUPd16_UPD:
2299 case ARM::VLD4DUPd32_UPD:
2300 case ARM::VLD1LNd8:
2301 case ARM::VLD1LNd16:
2302 case ARM::VLD1LNd32:
2303 case ARM::VLD1LNd8_UPD:
2304 case ARM::VLD1LNd16_UPD:
2305 case ARM::VLD1LNd32_UPD:
2306 case ARM::VLD2LNd8:
2307 case ARM::VLD2LNd16:
2308 case ARM::VLD2LNd32:
2309 case ARM::VLD2LNq16:
2310 case ARM::VLD2LNq32:
2311 case ARM::VLD2LNd8_UPD:
2312 case ARM::VLD2LNd16_UPD:
2313 case ARM::VLD2LNd32_UPD:
2314 case ARM::VLD2LNq16_UPD:
2315 case ARM::VLD2LNq32_UPD:
2316 case ARM::VLD4LNd8:
2317 case ARM::VLD4LNd16:
2318 case ARM::VLD4LNd32:
2319 case ARM::VLD4LNq16:
2320 case ARM::VLD4LNq32:
2321 case ARM::VLD4LNd8_UPD:
2322 case ARM::VLD4LNd16_UPD:
2323 case ARM::VLD4LNd32_UPD:
2324 case ARM::VLD4LNq16_UPD:
2325 case ARM::VLD4LNq32_UPD:
2326 // If the address is not 64-bit aligned, the latencies of these
2327 // instructions increases by one.
2328 ++Latency;
2329 break;
2330 }
2331
2332 return Latency;
2333 }
2334
2335 int
2336 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2337 SDNode *DefNode, unsigned DefIdx,
2338 SDNode *UseNode, unsigned UseIdx) const {
2339 if (!DefNode->isMachineOpcode())
2340 return 1;
2341
2342 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2343
2344 if (isZeroCost(DefMCID.Opcode))
2345 return 0;
2346
2347 if (!ItinData || ItinData->isEmpty())
2348 return DefMCID.mayLoad() ? 3 : 1;
2349
2350 if (!UseNode->isMachineOpcode()) {
2351 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2352 if (Subtarget.isCortexA9())
2353 return Latency <= 2 ? 1 : Latency - 1;
2354 else
2355 return Latency <= 3 ? 1 : Latency - 2;
2356 }
2357
2358 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2359 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2360 unsigned DefAlign = !DefMN->memoperands_empty()
2361 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2362 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2363 unsigned UseAlign = !UseMN->memoperands_empty()
2364 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2365 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2366 UseMCID, UseIdx, UseAlign);
2367
2368 if (Latency > 1 &&
2369 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2370 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2371 // variants are one cycle cheaper.
2372 switch (DefMCID.getOpcode()) {
2373 default: break;
2374 case ARM::LDRrs:
2375 case ARM::LDRBrs: {
2376 unsigned ShOpVal =
2377 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2378 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2379 if (ShImm == 0 ||
2380 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2381 --Latency;
2382 break;
2383 }
2384 case ARM::t2LDRs:
2385 case ARM::t2LDRBs:
2386 case ARM::t2LDRHs:
2387 case ARM::t2LDRSHs: {
2388 // Thumb2 mode: lsl only.
2389 unsigned ShAmt =
2390 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2391 if (ShAmt == 0 || ShAmt == 2)
2392 --Latency;
2393 break;
2394 }
2395 }
2396 }
2397
2398 if (DefAlign < 8 && Subtarget.isCortexA9())
2399 switch (DefMCID.getOpcode()) {
2400 default: break;
2401 case ARM::VLD1q8Pseudo:
2402 case ARM::VLD1q16Pseudo:
2403 case ARM::VLD1q32Pseudo:
2404 case ARM::VLD1q64Pseudo:
2405 case ARM::VLD1q8Pseudo_UPD:
2406 case ARM::VLD1q16Pseudo_UPD:
2407 case ARM::VLD1q32Pseudo_UPD:
2408 case ARM::VLD1q64Pseudo_UPD:
2409 case ARM::VLD2d8Pseudo:
2410 case ARM::VLD2d16Pseudo:
2411 case ARM::VLD2d32Pseudo:
2412 case ARM::VLD2q8Pseudo:
2413 case ARM::VLD2q16Pseudo:
2414 case ARM::VLD2q32Pseudo:
2415 case ARM::VLD2d8Pseudo_UPD:
2416 case ARM::VLD2d16Pseudo_UPD:
2417 case ARM::VLD2d32Pseudo_UPD:
2418 case ARM::VLD2q8Pseudo_UPD:
2419 case ARM::VLD2q16Pseudo_UPD:
2420 case ARM::VLD2q32Pseudo_UPD:
2421 case ARM::VLD3d8Pseudo:
2422 case ARM::VLD3d16Pseudo:
2423 case ARM::VLD3d32Pseudo:
2424 case ARM::VLD1d64TPseudo:
2425 case ARM::VLD3d8Pseudo_UPD:
2426 case ARM::VLD3d16Pseudo_UPD:
2427 case ARM::VLD3d32Pseudo_UPD:
2428 case ARM::VLD1d64TPseudo_UPD:
2429 case ARM::VLD3q8Pseudo_UPD:
2430 case ARM::VLD3q16Pseudo_UPD:
2431 case ARM::VLD3q32Pseudo_UPD:
2432 case ARM::VLD3q8oddPseudo:
2433 case ARM::VLD3q16oddPseudo:
2434 case ARM::VLD3q32oddPseudo:
2435 case ARM::VLD3q8oddPseudo_UPD:
2436 case ARM::VLD3q16oddPseudo_UPD:
2437 case ARM::VLD3q32oddPseudo_UPD:
2438 case ARM::VLD4d8Pseudo:
2439 case ARM::VLD4d16Pseudo:
2440 case ARM::VLD4d32Pseudo:
2441 case ARM::VLD1d64QPseudo:
2442 case ARM::VLD4d8Pseudo_UPD:
2443 case ARM::VLD4d16Pseudo_UPD:
2444 case ARM::VLD4d32Pseudo_UPD:
2445 case ARM::VLD1d64QPseudo_UPD:
2446 case ARM::VLD4q8Pseudo_UPD:
2447 case ARM::VLD4q16Pseudo_UPD:
2448 case ARM::VLD4q32Pseudo_UPD:
2449 case ARM::VLD4q8oddPseudo:
2450 case ARM::VLD4q16oddPseudo:
2451 case ARM::VLD4q32oddPseudo:
2452 case ARM::VLD4q8oddPseudo_UPD:
2453 case ARM::VLD4q16oddPseudo_UPD:
2454 case ARM::VLD4q32oddPseudo_UPD:
2455 case ARM::VLD1DUPq8Pseudo:
2456 case ARM::VLD1DUPq16Pseudo:
2457 case ARM::VLD1DUPq32Pseudo:
2458 case ARM::VLD1DUPq8Pseudo_UPD:
2459 case ARM::VLD1DUPq16Pseudo_UPD:
2460 case ARM::VLD1DUPq32Pseudo_UPD:
2461 case ARM::VLD2DUPd8Pseudo:
2462 case ARM::VLD2DUPd16Pseudo:
2463 case ARM::VLD2DUPd32Pseudo:
2464 case ARM::VLD2DUPd8Pseudo_UPD:
2465 case ARM::VLD2DUPd16Pseudo_UPD:
2466 case ARM::VLD2DUPd32Pseudo_UPD:
2467 case ARM::VLD4DUPd8Pseudo:
2468 case ARM::VLD4DUPd16Pseudo:
2469 case ARM::VLD4DUPd32Pseudo:
2470 case ARM::VLD4DUPd8Pseudo_UPD:
2471 case ARM::VLD4DUPd16Pseudo_UPD:
2472 case ARM::VLD4DUPd32Pseudo_UPD:
2473 case ARM::VLD1LNq8Pseudo:
2474 case ARM::VLD1LNq16Pseudo:
2475 case ARM::VLD1LNq32Pseudo:
2476 case ARM::VLD1LNq8Pseudo_UPD:
2477 case ARM::VLD1LNq16Pseudo_UPD:
2478 case ARM::VLD1LNq32Pseudo_UPD:
2479 case ARM::VLD2LNd8Pseudo:
2480 case ARM::VLD2LNd16Pseudo:
2481 case ARM::VLD2LNd32Pseudo:
2482 case ARM::VLD2LNq16Pseudo:
2483 case ARM::VLD2LNq32Pseudo:
2484 case ARM::VLD2LNd8Pseudo_UPD:
2485 case ARM::VLD2LNd16Pseudo_UPD:
2486 case ARM::VLD2LNd32Pseudo_UPD:
2487 case ARM::VLD2LNq16Pseudo_UPD:
2488 case ARM::VLD2LNq32Pseudo_UPD:
2489 case ARM::VLD4LNd8Pseudo:
2490 case ARM::VLD4LNd16Pseudo:
2491 case ARM::VLD4LNd32Pseudo:
2492 case ARM::VLD4LNq16Pseudo:
2493 case ARM::VLD4LNq32Pseudo:
2494 case ARM::VLD4LNd8Pseudo_UPD:
2495 case ARM::VLD4LNd16Pseudo_UPD:
2496 case ARM::VLD4LNd32Pseudo_UPD:
2497 case ARM::VLD4LNq16Pseudo_UPD:
2498 case ARM::VLD4LNq32Pseudo_UPD:
2499 // If the address is not 64-bit aligned, the latencies of these
2500 // instructions increases by one.
2501 ++Latency;
2502 break;
2503 }
2504
2505 return Latency;
2506 }
2507
2508 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2509 const MachineInstr *MI,
2510 unsigned *PredCost) const {
2511 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2512 MI->isRegSequence() || MI->isImplicitDef())
2513 return 1;
2514
2515 if (!ItinData || ItinData->isEmpty())
2516 return 1;
2517
2518 const MCInstrDesc &MCID = MI->getDesc();
2519 unsigned Class = MCID.getSchedClass();
2520 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2521 if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR))
2522 // When predicated, CPSR is an additional source operand for CPSR updating
2523 // instructions, this apparently increases their latencies.
2524 *PredCost = 1;
2525 if (UOps)
2526 return ItinData->getStageLatency(Class);
2527 return getNumMicroOps(ItinData, MI);
2528 }
2529
2530 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2531 SDNode *Node) const {
2532 if (!Node->isMachineOpcode())
2533 return 1;
2534
2535 if (!ItinData || ItinData->isEmpty())
2536 return 1;
2537
2538 unsigned Opcode = Node->getMachineOpcode();
2539 switch (Opcode) {
2540 default:
2541 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2542 case ARM::VLDMQIA:
2543 case ARM::VSTMQIA:
2544 return 2;
2545 }
2546 }
2547
2548 bool ARMBaseInstrInfo::
2549 hasHighOperandLatency(const InstrItineraryData *ItinData,
2550 const MachineRegisterInfo *MRI,
2551 const MachineInstr *DefMI, unsigned DefIdx,
2552 const MachineInstr *UseMI, unsigned UseIdx) const {
2553 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2554 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2555 if (Subtarget.isCortexA8() &&
2556 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2557 // CortexA8 VFP instructions are not pipelined.
2558 return true;
2559
2560 // Hoist VFP / NEON instructions with 4 or higher latency.
2561 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2562 if (Latency <= 3)
2563 return false;
2564 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2565 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2566 }
2567
2568 bool ARMBaseInstrInfo::
2569 hasLowDefLatency(const InstrItineraryData *ItinData,
2570 const MachineInstr *DefMI, unsigned DefIdx) const {
2571 if (!ItinData || ItinData->isEmpty())
2572 return false;
2573
2574 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2575 if (DDomain == ARMII::DomainGeneral) {
2576 unsigned DefClass = DefMI->getDesc().getSchedClass();
2577 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2578 return (DefCycle != -1 && DefCycle <= 2);
2579 }
2580 return false;
2581 }
2582
2583 bool
2584 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2585 unsigned &AddSubOpc,
2586 bool &NegAcc, bool &HasLane) const {
2587 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2588 if (I == MLxEntryMap.end())
2589 return false;
2590
2591 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2592 MulOpc = Entry.MulOpc;
2593 AddSubOpc = Entry.AddSubOpc;
2594 NegAcc = Entry.NegAcc;
2595 HasLane = Entry.HasLane;
2596 return true;
2597 }
STM8 backend for LLVM