lib/Target/ARM/ARMBaseInstrInfo.h

   1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMBASEINSTRUCTIONINFO_H
  15 #define ARMBASEINSTRUCTIONINFO_H
  16
  17 #include "ARM.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/Target/TargetInstrInfo.h"
  20 #include "llvm/ADT/DenseMap.h"
  21 #include "llvm/ADT/SmallSet.h"
  22
  23 #define GET_INSTRINFO_HEADER
  24 #include "ARMGenInstrInfo.inc"
  25
  26 namespace llvm {
  27   class ARMSubtarget;
  28   class ARMBaseRegisterInfo;
  29
  30 /// ARMII - This namespace holds all of the target specific flags that
  31 /// instruction info tracks.
  32 ///
  33 namespace ARMII {
  34   enum {
  35     //===------------------------------------------------------------------===//
  36     // Instruction Flags.
  37
  38     //===------------------------------------------------------------------===//
  39     // This four-bit field describes the addressing mode used.
  40     AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
  41
  42     // Size* - Flags to keep track of the size of an instruction.
  43     SizeShift     = 5,
  44     SizeMask      = 7 << SizeShift,
  45     SizeSpecial   = 1,   // 0 byte pseudo or special case.
  46     Size8Bytes    = 2,
  47     Size4Bytes    = 3,
  48     Size2Bytes    = 4,
  49
  50     // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
  51     // and store ops only.  Generic "updating" flag is used for ld/st multiple.
  52     // The index mode enums are declared in ARMBaseInfo.h
  53     IndexModeShift = 8,
  54     IndexModeMask  = 3 << IndexModeShift,
  55
  56     //===------------------------------------------------------------------===//
  57     // Instruction encoding formats.
  58     //
  59     FormShift     = 10,
  60     FormMask      = 0x3f << FormShift,
  61
  62     // Pseudo instructions
  63     Pseudo        = 0  << FormShift,
  64
  65     // Multiply instructions
  66     MulFrm        = 1  << FormShift,
  67
  68     // Branch instructions
  69     BrFrm         = 2  << FormShift,
  70     BrMiscFrm     = 3  << FormShift,
  71
  72     // Data Processing instructions
  73     DPFrm         = 4  << FormShift,
  74     DPSoRegFrm    = 5  << FormShift,
  75
  76     // Load and Store
  77     LdFrm         = 6  << FormShift,
  78     StFrm         = 7  << FormShift,
  79     LdMiscFrm     = 8  << FormShift,
  80     StMiscFrm     = 9  << FormShift,
  81     LdStMulFrm    = 10 << FormShift,
  82
  83     LdStExFrm     = 11 << FormShift,
  84
  85     // Miscellaneous arithmetic instructions
  86     ArithMiscFrm  = 12 << FormShift,
  87     SatFrm        = 13 << FormShift,
  88
  89     // Extend instructions
  90     ExtFrm        = 14 << FormShift,
  91
  92     // VFP formats
  93     VFPUnaryFrm   = 15 << FormShift,
  94     VFPBinaryFrm  = 16 << FormShift,
  95     VFPConv1Frm   = 17 << FormShift,
  96     VFPConv2Frm   = 18 << FormShift,
  97     VFPConv3Frm   = 19 << FormShift,
  98     VFPConv4Frm   = 20 << FormShift,
  99     VFPConv5Frm   = 21 << FormShift,
 100     VFPLdStFrm    = 22 << FormShift,
 101     VFPLdStMulFrm = 23 << FormShift,
 102     VFPMiscFrm    = 24 << FormShift,
 103
 104     // Thumb format
 105     ThumbFrm      = 25 << FormShift,
 106
 107     // Miscelleaneous format
 108     MiscFrm       = 26 << FormShift,
 109
 110     // NEON formats
 111     NGetLnFrm     = 27 << FormShift,
 112     NSetLnFrm     = 28 << FormShift,
 113     NDupFrm       = 29 << FormShift,
 114     NLdStFrm      = 30 << FormShift,
 115     N1RegModImmFrm= 31 << FormShift,
 116     N2RegFrm      = 32 << FormShift,
 117     NVCVTFrm      = 33 << FormShift,
 118     NVDupLnFrm    = 34 << FormShift,
 119     N2RegVShLFrm  = 35 << FormShift,
 120     N2RegVShRFrm  = 36 << FormShift,
 121     N3RegFrm      = 37 << FormShift,
 122     N3RegVShFrm   = 38 << FormShift,
 123     NVExtFrm      = 39 << FormShift,
 124     NVMulSLFrm    = 40 << FormShift,
 125     NVTBLFrm      = 41 << FormShift,
 126
 127     //===------------------------------------------------------------------===//
 128     // Misc flags.
 129
 130     // UnaryDP - Indicates this is a unary data processing instruction, i.e.
 131     // it doesn't have a Rn operand.
 132     UnaryDP       = 1 << 16,
 133
 134     // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
 135     // a 16-bit Thumb instruction if certain conditions are met.
 136     Xform16Bit    = 1 << 17,
 137
 138     //===------------------------------------------------------------------===//
 139     // Code domain.
 140     DomainShift   = 18,
 141     DomainMask    = 7 << DomainShift,
 142     DomainGeneral = 0 << DomainShift,
 143     DomainVFP     = 1 << DomainShift,
 144     DomainNEON    = 2 << DomainShift,
 145     DomainNEONA8  = 4 << DomainShift,
 146
 147     //===------------------------------------------------------------------===//
 148     // Field shifts - such shifts are used to set field while generating
 149     // machine instructions.
 150     //
 151     // FIXME: This list will need adjusting/fixing as the MC code emitter
 152     // takes shape and the ARMCodeEmitter.cpp bits go away.
 153     ShiftTypeShift = 4,
 154
 155     M_BitShift     = 5,
 156     ShiftImmShift  = 5,
 157     ShiftShift     = 7,
 158     N_BitShift     = 7,
 159     ImmHiShift     = 8,
 160     SoRotImmShift  = 8,
 161     RegRsShift     = 8,
 162     ExtRotImmShift = 10,
 163     RegRdLoShift   = 12,
 164     RegRdShift     = 12,
 165     RegRdHiShift   = 16,
 166     RegRnShift     = 16,
 167     S_BitShift     = 20,
 168     W_BitShift     = 21,
 169     AM3_I_BitShift = 22,
 170     D_BitShift     = 22,
 171     U_BitShift     = 23,
 172     P_BitShift     = 24,
 173     I_BitShift     = 25,
 174     CondShift      = 28
 175   };
 176 }
 177
 178 class ARMBaseInstrInfo : public ARMGenInstrInfo {
 179   const ARMSubtarget &Subtarget;
 180
 181 protected:
 182   // Can be only subclassed.
 183   explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
 184
 185 public:
 186   // Return the non-pre/post incrementing version of 'Opc'. Return 0
 187   // if there is not such an opcode.
 188   virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
 189
 190   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
 191                                               MachineBasicBlock::iterator &MBBI,
 192                                               LiveVariables *LV) const;
 193
 194   virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
 195   const ARMSubtarget &getSubtarget() const { return Subtarget; }
 196
 197   ScheduleHazardRecognizer *
 198   CreateTargetHazardRecognizer(const TargetMachine *TM,
 199                                const ScheduleDAG *DAG) const;
 200
 201   ScheduleHazardRecognizer *
 202   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
 203                                      const ScheduleDAG *DAG) const;
 204
 205   // Branch analysis.
 206   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 207                              MachineBasicBlock *&FBB,
 208                              SmallVectorImpl<MachineOperand> &Cond,
 209                              bool AllowModify = false) const;
 210   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
 211   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 212                                 MachineBasicBlock *FBB,
 213                                 const SmallVectorImpl<MachineOperand> &Cond,
 214                                 DebugLoc DL) const;
 215
 216   virtual
 217   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 218
 219   // Predication support.
 220   bool isPredicated(const MachineInstr *MI) const {
 221     int PIdx = MI->findFirstPredOperandIdx();
 222     return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
 223   }
 224
 225   ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
 226     int PIdx = MI->findFirstPredOperandIdx();
 227     return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
 228                       : ARMCC::AL;
 229   }
 230
 231   virtual
 232   bool PredicateInstruction(MachineInstr *MI,
 233                             const SmallVectorImpl<MachineOperand> &Pred) const;
 234
 235   virtual
 236   bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
 237                          const SmallVectorImpl<MachineOperand> &Pred2) const;
 238
 239   virtual bool DefinesPredicate(MachineInstr *MI,
 240                                 std::vector<MachineOperand> &Pred) const;
 241
 242   virtual bool isPredicable(MachineInstr *MI) const;
 243
 244   /// GetInstSize - Returns the size of the specified MachineInstr.
 245   ///
 246   virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
 247
 248   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
 249                                        int &FrameIndex) const;
 250   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
 251                                       int &FrameIndex) const;
 252
 253   virtual void copyPhysReg(MachineBasicBlock &MBB,
 254                            MachineBasicBlock::iterator I, DebugLoc DL,
 255                            unsigned DestReg, unsigned SrcReg,
 256                            bool KillSrc) const;
 257
 258   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
 259                                    MachineBasicBlock::iterator MBBI,
 260                                    unsigned SrcReg, bool isKill, int FrameIndex,
 261                                    const TargetRegisterClass *RC,
 262                                    const TargetRegisterInfo *TRI) const;
 263
 264   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
 265                                     MachineBasicBlock::iterator MBBI,
 266                                     unsigned DestReg, int FrameIndex,
 267                                     const TargetRegisterClass *RC,
 268                                     const TargetRegisterInfo *TRI) const;
 269
 270   virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
 271                                                  int FrameIx,
 272                                                  uint64_t Offset,
 273                                                  const MDNode *MDPtr,
 274                                                  DebugLoc DL) const;
 275
 276   virtual void reMaterialize(MachineBasicBlock &MBB,
 277                              MachineBasicBlock::iterator MI,
 278                              unsigned DestReg, unsigned SubIdx,
 279                              const MachineInstr *Orig,
 280                              const TargetRegisterInfo &TRI) const;
 281
 282   MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
 283
 284   virtual bool produceSameValue(const MachineInstr *MI0,
 285                                 const MachineInstr *MI1,
 286                                 const MachineRegisterInfo *MRI) const;
 287
 288   /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
 289   /// determine if two loads are loading from the same base address. It should
 290   /// only return true if the base pointers are the same and the only
 291   /// differences between the two addresses is the offset. It also returns the
 292   /// offsets by reference.
 293   virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
 294                                        int64_t &Offset1, int64_t &Offset2)const;
 295
 296   /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
 297   /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
 298   /// should be scheduled togther. On some targets if two loads are loading from
 299   /// addresses in the same cache line, it's better if they are scheduled
 300   /// together. This function takes two integers that represent the load offsets
 301   /// from the common base address. It returns true if it decides it's desirable
 302   /// to schedule the two loads together. "NumLoads" is the number of loads that
 303   /// have already been scheduled after Load1.
 304   virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
 305                                        int64_t Offset1, int64_t Offset2,
 306                                        unsigned NumLoads) const;
 307
 308   virtual bool isSchedulingBoundary(const MachineInstr *MI,
 309                                     const MachineBasicBlock *MBB,
 310                                     const MachineFunction &MF) const;
 311
 312   virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
 313                                    unsigned NumCycles, unsigned ExtraPredCycles,
 314                                    const BranchProbability &Probability) const;
 315
 316   virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
 317                                    unsigned NumT, unsigned ExtraT,
 318                                    MachineBasicBlock &FMBB,
 319                                    unsigned NumF, unsigned ExtraF,
 320                                    const BranchProbability &Probability) const;
 321
 322   virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
 323                                          unsigned NumCycles,
 324                                          const BranchProbability
 325                                            &Probability) const {
 326     return NumCycles == 1;
 327   }
 328
 329   /// AnalyzeCompare - For a comparison instruction, return the source register
 330   /// in SrcReg and the value it compares against in CmpValue. Return true if
 331   /// the comparison instruction can be analyzed.
 332   virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
 333                               int &CmpMask, int &CmpValue) const;
 334
 335   /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
 336   /// that we can remove a "comparison with zero".
 337   virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
 338                                     int CmpMask, int CmpValue,
 339                                     const MachineRegisterInfo *MRI) const;
 340
 341   /// FoldImmediate - 'Reg' is known to be defined by a move immediate
 342   /// instruction, try to fold the immediate into the use instruction.
 343   virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
 344                              unsigned Reg, MachineRegisterInfo *MRI) const;
 345
 346   virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
 347                                   const MachineInstr *MI) const;
 348
 349   virtual
 350   int getOperandLatency(const InstrItineraryData *ItinData,
 351                         const MachineInstr *DefMI, unsigned DefIdx,
 352                         const MachineInstr *UseMI, unsigned UseIdx) const;
 353   virtual
 354   int getOperandLatency(const InstrItineraryData *ItinData,
 355                         SDNode *DefNode, unsigned DefIdx,
 356                         SDNode *UseNode, unsigned UseIdx) const;
 357 private:
 358   int getVLDMDefCycle(const InstrItineraryData *ItinData,
 359                       const MCInstrDesc &DefMCID,
 360                       unsigned DefClass,
 361                       unsigned DefIdx, unsigned DefAlign) const;
 362   int getLDMDefCycle(const InstrItineraryData *ItinData,
 363                      const MCInstrDesc &DefMCID,
 364                      unsigned DefClass,
 365                      unsigned DefIdx, unsigned DefAlign) const;
 366   int getVSTMUseCycle(const InstrItineraryData *ItinData,
 367                       const MCInstrDesc &UseMCID,
 368                       unsigned UseClass,
 369                       unsigned UseIdx, unsigned UseAlign) const;
 370   int getSTMUseCycle(const InstrItineraryData *ItinData,
 371                      const MCInstrDesc &UseMCID,
 372                      unsigned UseClass,
 373                      unsigned UseIdx, unsigned UseAlign) const;
 374   int getOperandLatency(const InstrItineraryData *ItinData,
 375                         const MCInstrDesc &DefMCID,
 376                         unsigned DefIdx, unsigned DefAlign,
 377                         const MCInstrDesc &UseMCID,
 378                         unsigned UseIdx, unsigned UseAlign) const;
 379
 380   int getInstrLatency(const InstrItineraryData *ItinData,
 381                       const MachineInstr *MI, unsigned *PredCost = 0) const;
 382
 383   int getInstrLatency(const InstrItineraryData *ItinData,
 384                       SDNode *Node) const;
 385
 386   bool hasHighOperandLatency(const InstrItineraryData *ItinData,
 387                              const MachineRegisterInfo *MRI,
 388                              const MachineInstr *DefMI, unsigned DefIdx,
 389                              const MachineInstr *UseMI, unsigned UseIdx) const;
 390   bool hasLowDefLatency(const InstrItineraryData *ItinData,
 391                         const MachineInstr *DefMI, unsigned DefIdx) const;
 392
 393 private:
 394   /// Modeling special VFP / NEON fp MLA / MLS hazards.
 395
 396   /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
 397   /// MLx table.
 398   DenseMap<unsigned, unsigned> MLxEntryMap;
 399
 400   /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
 401   /// stalls when scheduled together with fp MLA / MLS opcodes.
 402   SmallSet<unsigned, 16> MLxHazardOpcodes;
 403
 404 public:
 405   /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
 406   /// instruction.
 407   bool isFpMLxInstruction(unsigned Opcode) const {
 408     return MLxEntryMap.count(Opcode);
 409   }
 410
 411   /// isFpMLxInstruction - This version also returns the multiply opcode and the
 412   /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
 413   /// the MLX instructions with an extra lane operand.
 414   bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
 415                           unsigned &AddSubOpc, bool &NegAcc,
 416                           bool &HasLane) const;
 417
 418   /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
 419   /// will cause stalls when scheduled after (within 4-cycle window) a fp
 420   /// MLA / MLS instruction.
 421   bool canCauseFpMLxStall(unsigned Opcode) const {
 422     return MLxHazardOpcodes.count(Opcode);
 423   }
 424 };
 425
 426 static inline
 427 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
 428   return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
 429 }
 430
 431 static inline
 432 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
 433   return MIB.addReg(0);
 434 }
 435
 436 static inline
 437 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
 438                                           bool isDead = false) {
 439   return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
 440 }
 441
 442 static inline
 443 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
 444   return MIB.addReg(0);
 445 }
 446
 447 static inline
 448 bool isUncondBranchOpcode(int Opc) {
 449   return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
 450 }
 451
 452 static inline
 453 bool isCondBranchOpcode(int Opc) {
 454   return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
 455 }
 456
 457 static inline
 458 bool isJumpTableBranchOpcode(int Opc) {
 459   return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
 460     Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
 461 }
 462
 463 static inline
 464 bool isIndirectBranchOpcode(int Opc) {
 465   return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
 466 }
 467
 468 /// getInstrPredicate - If instruction is predicated, returns its predicate
 469 /// condition, otherwise returns AL. It also returns the condition code
 470 /// register by reference.
 471 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
 472
 473 int getMatchingCondBranchOpcode(int Opc);
 474
 475 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
 476 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
 477 /// code.
 478 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
 479                              MachineBasicBlock::iterator &MBBI, DebugLoc dl,
 480                              unsigned DestReg, unsigned BaseReg, int NumBytes,
 481                              ARMCC::CondCodes Pred, unsigned PredReg,
 482                              const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
 483
 484 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
 485                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
 486                             unsigned DestReg, unsigned BaseReg, int NumBytes,
 487                             ARMCC::CondCodes Pred, unsigned PredReg,
 488                             const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
 489 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
 490                                MachineBasicBlock::iterator &MBBI, DebugLoc dl,
 491                                unsigned DestReg, unsigned BaseReg,
 492                                int NumBytes, const TargetInstrInfo &TII,
 493                                const ARMBaseRegisterInfo& MRI,
 494                                unsigned MIFlags = 0);
 495
 496
 497 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
 498 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
 499 /// offset could not be handled directly in MI, and return the left-over
 500 /// portion by reference.
 501 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
 502                           unsigned FrameReg, int &Offset,
 503                           const ARMBaseInstrInfo &TII);
 504
 505 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
 506                          unsigned FrameReg, int &Offset,
 507                          const ARMBaseInstrInfo &TII);
 508
 509 } // End llvm namespace
 510
 511 #endif