lib/Target/ARM/ARMFixupKinds.h

   1 //===-- ARM/ARMFixupKinds.h - ARM Specific Fixup Entries --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #ifndef LLVM_ARM_ARMFIXUPKINDS_H
  11 #define LLVM_ARM_ARMFIXUPKINDS_H
  12
  13 #include "llvm/MC/MCFixup.h"
  14
  15 namespace llvm {
  16 namespace ARM {
  17 enum Fixups {
  18   // fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
  19   // addresses
  20   fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
  21
  22   // fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with
  23   // the 16-bit halfwords reordered.
  24   fixup_t2_ldst_pcrel_12,
  25
  26   // fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
  27   // used in VFP instructions where the lower 2 bits are not encoded
  28   // (so it's encoded as an 8-bit immediate).
  29   fixup_arm_pcrel_10,
  30   // fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
  31   // the short-swapped encoding of Thumb2 instructions.
  32   fixup_t2_pcrel_10,
  33   // fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
  34   // addresses where the lower 2 bits are not encoded (so it's encoded as an
  35   // 8-bit immediate).
  36   fixup_thumb_adr_pcrel_10,
  37   // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
  38   // instruction.
  39   fixup_arm_adr_pcrel_12,
  40   // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
  41   // instruction.
  42   fixup_t2_adr_pcrel_12,
  43   // fixup_arm_condbranch - 24-bit PC relative relocation for conditional branch
  44   // instructions.
  45   fixup_arm_condbranch,
  46   // fixup_arm_uncondbranch - 24-bit PC relative relocation for
  47   // branch instructions. (unconditional)
  48   fixup_arm_uncondbranch,
  49   // fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct
  50   // uconditional branch instructions.
  51   fixup_t2_condbranch,
  52   // fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct
  53   // branch unconditional branch instructions.
  54   fixup_t2_uncondbranch,
  55
  56   // fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
  57   fixup_arm_thumb_br,
  58
  59   // fixup_arm_thumb_bl - Fixup for Thumb BL instructions.
  60   fixup_arm_thumb_bl,
  61
  62   // fixup_arm_thumb_blx - Fixup for Thumb BLX instructions.
  63   fixup_arm_thumb_blx,
  64
  65   // fixup_arm_thumb_cb - Fixup for Thumb branch instructions.
  66   fixup_arm_thumb_cb,
  67
  68   // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
  69   fixup_arm_thumb_cp,
  70
  71   // fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
  72   fixup_arm_thumb_bcc,
  73
  74   // The next two are for the movt/movw pair
  75   // the 16bit imm field are split into imm{15-12} and imm{11-0}
  76   fixup_arm_movt_hi16, // :upper16:
  77   fixup_arm_movw_lo16, // :lower16:
  78   fixup_t2_movt_hi16, // :upper16:
  79   fixup_t2_movw_lo16, // :lower16:
  80
  81   // It is possible to create an "immediate" that happens to be pcrel.
  82   // movw r0, :lower16:Foo-(Bar+8) and movt  r0, :upper16:Foo-(Bar+8)
  83   // result in different reloc tags than the above two.
  84   // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC
  85   fixup_arm_movt_hi16_pcrel, // :upper16:
  86   fixup_arm_movw_lo16_pcrel, // :lower16:
  87   fixup_t2_movt_hi16_pcrel, // :upper16:
  88   fixup_t2_movw_lo16_pcrel, // :lower16:
  89
  90   // Marker
  91   LastTargetFixupKind,
  92   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
  93 };
  94 }
  95 }
  96
  97 #endif