lib/Target/ARM/NEONMoveFix.cpp

   1 //===-- NEONMoveFix.cpp - Convert vfp reg-reg moves into neon ---*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #define DEBUG_TYPE "neon-mov-fix"
  11 #include "ARM.h"
  12 #include "ARMMachineFunctionInfo.h"
  13 #include "ARMInstrInfo.h"
  14 #include "llvm/CodeGen/MachineInstr.h"
  15 #include "llvm/CodeGen/MachineInstrBuilder.h"
  16 #include "llvm/CodeGen/MachineFunctionPass.h"
  17 #include "llvm/ADT/Statistic.h"
  18 #include "llvm/Support/Debug.h"
  19 #include "llvm/Support/raw_ostream.h"
  20 using namespace llvm;
  21
  22 STATISTIC(NumVMovs, "Number of reg-reg moves converted");
  23
  24 namespace {
  25   struct NEONMoveFixPass : public MachineFunctionPass {
  26     static char ID;
  27     NEONMoveFixPass() : MachineFunctionPass(ID) {}
  28
  29     virtual bool runOnMachineFunction(MachineFunction &Fn);
  30
  31     virtual const char *getPassName() const {
  32       return "NEON reg-reg move conversion";
  33     }
  34
  35   private:
  36     const TargetRegisterInfo *TRI;
  37     const ARMBaseInstrInfo *TII;
  38     bool isA8;
  39
  40     typedef DenseMap<unsigned, const MachineInstr*> RegMap;
  41
  42     bool InsertMoves(MachineBasicBlock &MBB);
  43   };
  44   char NEONMoveFixPass::ID = 0;
  45 }
  46
  47 static bool inNEONDomain(unsigned Domain, bool isA8) {
  48   return (Domain & ARMII::DomainNEON) ||
  49     (isA8 && (Domain & ARMII::DomainNEONA8));
  50 }
  51
  52 bool NEONMoveFixPass::InsertMoves(MachineBasicBlock &MBB) {
  53   RegMap Defs;
  54   bool Modified = false;
  55
  56   // Walk over MBB tracking the def points of the registers.
  57   MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
  58   MachineBasicBlock::iterator NextMII;
  59   for (; MII != E; MII = NextMII) {
  60     NextMII = llvm::next(MII);
  61     MachineInstr *MI = &*MII;
  62
  63     if (MI->getOpcode() == ARM::VMOVD &&
  64         !TII->isPredicated(MI)) {
  65       unsigned SrcReg = MI->getOperand(1).getReg();
  66       // If we do not find an instruction defining the reg, this means the
  67       // register should be live-in for this BB. It's always to better to use
  68       // NEON reg-reg moves.
  69       unsigned Domain = ARMII::DomainNEON;
  70       RegMap::iterator DefMI = Defs.find(SrcReg);
  71       if (DefMI != Defs.end()) {
  72         Domain = DefMI->second->getDesc().TSFlags & ARMII::DomainMask;
  73         // Instructions in general domain are subreg accesses.
  74         // Map them to NEON reg-reg moves.
  75         if (Domain == ARMII::DomainGeneral)
  76           Domain = ARMII::DomainNEON;
  77       }
  78
  79       if (inNEONDomain(Domain, isA8)) {
  80         // Convert VMOVD to VMOVDneon
  81         unsigned DestReg = MI->getOperand(0).getReg();
  82
  83         DEBUG({errs() << "vmov convert: "; MI->dump();});
  84
  85         // It's safe to ignore imp-defs / imp-uses here, since:
  86         //  - We're running late, no intelligent condegen passes should be run
  87         //    afterwards
  88         //  - The imp-defs / imp-uses are superregs only, we don't care about
  89         //    them.
  90         AddDefaultPred(BuildMI(MBB, *MI, MI->getDebugLoc(),
  91                              TII->get(ARM::VMOVDneon), DestReg).addReg(SrcReg));
  92         MBB.erase(MI);
  93         MachineBasicBlock::iterator I = prior(NextMII);
  94         MI = &*I;
  95
  96         DEBUG({errs() << "        into: "; MI->dump();});
  97
  98         Modified = true;
  99         ++NumVMovs;
 100       } else {
 101         assert((Domain & ARMII::DomainVFP) && "Invalid domain!");
 102         // Do nothing.
 103       }
 104     }
 105
 106     // Update def information.
 107     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 108       const MachineOperand& MO = MI->getOperand(i);
 109       if (!MO.isReg() || !MO.isDef())
 110         continue;
 111       unsigned MOReg = MO.getReg();
 112
 113       Defs[MOReg] = MI;
 114       // Catch aliases as well.
 115       for (const unsigned *R = TRI->getAliasSet(MOReg); *R; ++R)
 116         Defs[*R] = MI;
 117     }
 118   }
 119
 120   return Modified;
 121 }
 122
 123 bool NEONMoveFixPass::runOnMachineFunction(MachineFunction &Fn) {
 124   ARMFunctionInfo *AFI = Fn.getInfo<ARMFunctionInfo>();
 125   const TargetMachine &TM = Fn.getTarget();
 126
 127   if (AFI->isThumb1OnlyFunction())
 128     return false;
 129
 130   TRI = TM.getRegisterInfo();
 131   TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
 132   isA8 = TM.getSubtarget<ARMSubtarget>().isCortexA8();
 133
 134   bool Modified = false;
 135   for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
 136        ++MFI) {
 137     MachineBasicBlock &MBB = *MFI;
 138     Modified |= InsertMoves(MBB);
 139   }
 140
 141   return Modified;
 142 }
 143
 144 /// createNEONMoveFixPass - Returns an instance of the NEON reg-reg moves fix
 145 /// pass.
 146 FunctionPass *llvm::createNEONMoveFixPass() {
 147   return new NEONMoveFixPass();
 148 }