lib/Target/Blackfin/BlackfinInstrInfo.h

   1 //===- BlackfinInstrInfo.h - Blackfin Instruction Information ---*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Blackfin implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef BLACKFININSTRUCTIONINFO_H
  15 #define BLACKFININSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "BlackfinRegisterInfo.h"
  19
  20 #define GET_INSTRINFO_HEADER
  21 #include "BlackfinGenInstrInfo.inc"
  22
  23 namespace llvm {
  24
  25   class BlackfinInstrInfo : public BlackfinGenInstrInfo {
  26     const BlackfinRegisterInfo RI;
  27     const BlackfinSubtarget& Subtarget;
  28   public:
  29     explicit BlackfinInstrInfo(BlackfinSubtarget &ST);
  30
  31     /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  32     /// such, whenever a client has an instance of instruction info, it should
  33     /// always be able to get register info as well (through this method).
  34     virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; }
  35
  36     virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
  37                                          int &FrameIndex) const;
  38
  39     virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
  40                                         int &FrameIndex) const;
  41
  42     virtual unsigned
  43     InsertBranch(MachineBasicBlock &MBB,
  44                  MachineBasicBlock *TBB,
  45                  MachineBasicBlock *FBB,
  46                  const SmallVectorImpl<MachineOperand> &Cond,
  47                  DebugLoc DL) const;
  48
  49     virtual void copyPhysReg(MachineBasicBlock &MBB,
  50                              MachineBasicBlock::iterator MI, DebugLoc DL,
  51                              unsigned DestReg, unsigned SrcReg,
  52                              bool KillSrc) const;
  53
  54     virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  55                                      MachineBasicBlock::iterator MBBI,
  56                                      unsigned SrcReg, bool isKill,
  57                                      int FrameIndex,
  58                                      const TargetRegisterClass *RC,
  59                                      const TargetRegisterInfo *TRI) const;
  60
  61     virtual void storeRegToAddr(MachineFunction &MF,
  62                                 unsigned SrcReg, bool isKill,
  63                                 SmallVectorImpl<MachineOperand> &Addr,
  64                                 const TargetRegisterClass *RC,
  65                                 SmallVectorImpl<MachineInstr*> &NewMIs) const;
  66
  67     virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  68                                       MachineBasicBlock::iterator MBBI,
  69                                       unsigned DestReg, int FrameIndex,
  70                                       const TargetRegisterClass *RC,
  71                                       const TargetRegisterInfo *TRI) const;
  72
  73     virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
  74                                  SmallVectorImpl<MachineOperand> &Addr,
  75                                  const TargetRegisterClass *RC,
  76                                  SmallVectorImpl<MachineInstr*> &NewMIs) const;
  77   };
  78
  79 } // end namespace llvm
  80
  81 #endif