lib/Target/CellSPU/SPUInstrInfo.h

   1 //===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the CellSPU implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef SPU_INSTRUCTIONINFO_H
  15 #define SPU_INSTRUCTIONINFO_H
  16
  17 #include "SPU.h"
  18 #include "llvm/Target/TargetInstrInfo.h"
  19 #include "SPURegisterInfo.h"
  20
  21 #define GET_INSTRINFO_HEADER
  22 #include "SPUGenInstrInfo.inc"
  23
  24 namespace llvm {
  25   //! Cell SPU instruction information class
  26   class SPUInstrInfo : public SPUGenInstrInfo {
  27     SPUTargetMachine &TM;
  28     const SPURegisterInfo RI;
  29   public:
  30     explicit SPUInstrInfo(SPUTargetMachine &tm);
  31
  32     /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  33     /// such, whenever a client has an instance of instruction info, it should
  34     /// always be able to get register info as well (through this method).
  35     ///
  36     virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
  37
  38     ScheduleHazardRecognizer *
  39     CreateTargetHazardRecognizer(const TargetMachine *TM,
  40                                  const ScheduleDAG *DAG) const;
  41
  42     unsigned isLoadFromStackSlot(const MachineInstr *MI,
  43                                  int &FrameIndex) const;
  44     unsigned isStoreToStackSlot(const MachineInstr *MI,
  45                                 int &FrameIndex) const;
  46
  47     virtual void copyPhysReg(MachineBasicBlock &MBB,
  48                              MachineBasicBlock::iterator I, DebugLoc DL,
  49                              unsigned DestReg, unsigned SrcReg,
  50                              bool KillSrc) const;
  51
  52     //! Store a register to a stack slot, based on its register class.
  53     virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  54                                      MachineBasicBlock::iterator MBBI,
  55                                      unsigned SrcReg, bool isKill, int FrameIndex,
  56                                      const TargetRegisterClass *RC,
  57                                      const TargetRegisterInfo *TRI) const;
  58
  59     //! Load a register from a stack slot, based on its register class.
  60     virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  61                                       MachineBasicBlock::iterator MBBI,
  62                                       unsigned DestReg, int FrameIndex,
  63                                       const TargetRegisterClass *RC,
  64                                       const TargetRegisterInfo *TRI) const;
  65
  66     //! Reverses a branch's condition, returning false on success.
  67     virtual
  68     bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
  69
  70     virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  71                                MachineBasicBlock *&FBB,
  72                                SmallVectorImpl<MachineOperand> &Cond,
  73                                bool AllowModify) const;
  74
  75     virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  76
  77     virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  78                                   MachineBasicBlock *FBB,
  79                                   const SmallVectorImpl<MachineOperand> &Cond,
  80                                   DebugLoc DL) const;
  81    };
  82 }
  83
  84 #endif