?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Use BranchProbability instead of floating points in IfConverter.
[llvm/stm8.git] / lib / Target / MSP430 / MSP430ISelLowering.cpp
blob0a3eab1f7a6699f74d2ca0d960011dd685077422
1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MSP430TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "msp430-lower"
15
16 #include "MSP430ISelLowering.h"
17 #include "MSP430.h"
18 #include "MSP430MachineFunctionInfo.h"
19 #include "MSP430TargetMachine.h"
20 #include "MSP430Subtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/GlobalAlias.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/CodeGen/SelectionDAGISel.h"
34 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/ADT/VectorExtras.h"
41 using namespace llvm;
42
43 typedef enum {
44 NoHWMult,
45 HWMultIntr,
46 HWMultNoIntr
47 } HWMultUseMode;
48
49 static cl::opt<HWMultUseMode>
50 HWMultMode("msp430-hwmult-mode",
51 cl::desc("Hardware multiplier use mode"),
52 cl::init(HWMultNoIntr),
53 cl::values(
54 clEnumValN(NoHWMult, "no",
55 "Do not use hardware multiplier"),
56 clEnumValN(HWMultIntr, "interrupts",
57 "Assume hardware multiplier can be used inside interrupts"),
58 clEnumValN(HWMultNoIntr, "use",
59 "Assume hardware multiplier cannot be used inside interrupts"),
60 clEnumValEnd));
61
62 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63 TargetLowering(tm, new TargetLoweringObjectFileELF()),
64 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
65
66 TD = getTargetData();
67
68 // Set up the register classes.
69 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
70 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
71
72 // Compute derived properties from the register classes
73 computeRegisterProperties();
74
75 // Provide all sorts of operation actions
76
77 // Division is expensive
78 setIntDivIsCheap(false);
79
80 setStackPointerRegisterToSaveRestore(MSP430::SPW);
81 setBooleanContents(ZeroOrOneBooleanContent);
82 setSchedulingPreference(Sched::Latency);
83
84 // We have post-incremented loads / stores.
85 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
86 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
87
88 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
90 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
93
94 // We don't have any truncstores
95 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
96
97 setOperationAction(ISD::SRA, MVT::i8, Custom);
98 setOperationAction(ISD::SHL, MVT::i8, Custom);
99 setOperationAction(ISD::SRL, MVT::i8, Custom);
100 setOperationAction(ISD::SRA, MVT::i16, Custom);
101 setOperationAction(ISD::SHL, MVT::i16, Custom);
102 setOperationAction(ISD::SRL, MVT::i16, Custom);
103 setOperationAction(ISD::ROTL, MVT::i8, Expand);
104 setOperationAction(ISD::ROTR, MVT::i8, Expand);
105 setOperationAction(ISD::ROTL, MVT::i16, Expand);
106 setOperationAction(ISD::ROTR, MVT::i16, Expand);
107 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
108 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
109 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
110 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
111 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
112 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
113 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
114 setOperationAction(ISD::SETCC, MVT::i8, Custom);
115 setOperationAction(ISD::SETCC, MVT::i16, Custom);
116 setOperationAction(ISD::SELECT, MVT::i8, Expand);
117 setOperationAction(ISD::SELECT, MVT::i16, Expand);
118 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
119 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
120 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
121 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
122 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
123
124 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
125 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
126 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
127 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
128 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
129 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
130
131 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
132 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
133 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
134 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
135 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
136 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
137
138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
139
140 // FIXME: Implement efficiently multiplication by a constant
141 setOperationAction(ISD::MUL, MVT::i8, Expand);
142 setOperationAction(ISD::MULHS, MVT::i8, Expand);
143 setOperationAction(ISD::MULHU, MVT::i8, Expand);
144 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
145 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
146 setOperationAction(ISD::MUL, MVT::i16, Expand);
147 setOperationAction(ISD::MULHS, MVT::i16, Expand);
148 setOperationAction(ISD::MULHU, MVT::i16, Expand);
149 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
150 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
151
152 setOperationAction(ISD::UDIV, MVT::i8, Expand);
153 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
154 setOperationAction(ISD::UREM, MVT::i8, Expand);
155 setOperationAction(ISD::SDIV, MVT::i8, Expand);
156 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
157 setOperationAction(ISD::SREM, MVT::i8, Expand);
158 setOperationAction(ISD::UDIV, MVT::i16, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
160 setOperationAction(ISD::UREM, MVT::i16, Expand);
161 setOperationAction(ISD::SDIV, MVT::i16, Expand);
162 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
163 setOperationAction(ISD::SREM, MVT::i16, Expand);
164
165 // Libcalls names.
166 if (HWMultMode == HWMultIntr) {
167 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw");
168 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
169 } else if (HWMultMode == HWMultNoIntr) {
170 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint");
171 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
172 }
173
174 setMinFunctionAlignment(1);
175 setPrefFunctionAlignment(2);
176 }
177
178 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
179 SelectionDAG &DAG) const {
180 switch (Op.getOpcode()) {
181 case ISD::SHL: // FALLTHROUGH
182 case ISD::SRL:
183 case ISD::SRA: return LowerShifts(Op, DAG);
184 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
185 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
186 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
187 case ISD::SETCC: return LowerSETCC(Op, DAG);
188 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
189 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
190 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
191 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
192 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
193 default:
194 llvm_unreachable("unimplemented operand");
195 return SDValue();
196 }
197 }
198
199 //===----------------------------------------------------------------------===//
200 // MSP430 Inline Assembly Support
201 //===----------------------------------------------------------------------===//
202
203 /// getConstraintType - Given a constraint letter, return the type of
204 /// constraint it is for this target.
205 TargetLowering::ConstraintType
206 MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
207 if (Constraint.size() == 1) {
208 switch (Constraint[0]) {
209 case 'r':
210 return C_RegisterClass;
211 default:
212 break;
213 }
214 }
215 return TargetLowering::getConstraintType(Constraint);
216 }
217
218 std::pair<unsigned, const TargetRegisterClass*>
219 MSP430TargetLowering::
220 getRegForInlineAsmConstraint(const std::string &Constraint,
221 EVT VT) const {
222 if (Constraint.size() == 1) {
223 // GCC Constraint Letters
224 switch (Constraint[0]) {
225 default: break;
226 case 'r': // GENERAL_REGS
227 if (VT == MVT::i8)
228 return std::make_pair(0U, MSP430::GR8RegisterClass);
229
230 return std::make_pair(0U, MSP430::GR16RegisterClass);
231 }
232 }
233
234 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
235 }
236
237 //===----------------------------------------------------------------------===//
238 // Calling Convention Implementation
239 //===----------------------------------------------------------------------===//
240
241 #include "MSP430GenCallingConv.inc"
242
243 SDValue
244 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
245 CallingConv::ID CallConv,
246 bool isVarArg,
247 const SmallVectorImpl<ISD::InputArg>
248 &Ins,
249 DebugLoc dl,
250 SelectionDAG &DAG,
251 SmallVectorImpl<SDValue> &InVals)
252 const {
253
254 switch (CallConv) {
255 default:
256 llvm_unreachable("Unsupported calling convention");
257 case CallingConv::C:
258 case CallingConv::Fast:
259 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
260 case CallingConv::MSP430_INTR:
261 if (Ins.empty())
262 return Chain;
263 else {
264 report_fatal_error("ISRs cannot have arguments");
265 return SDValue();
266 }
267 }
268 }
269
270 SDValue
271 MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
272 CallingConv::ID CallConv, bool isVarArg,
273 bool &isTailCall,
274 const SmallVectorImpl<ISD::OutputArg> &Outs,
275 const SmallVectorImpl<SDValue> &OutVals,
276 const SmallVectorImpl<ISD::InputArg> &Ins,
277 DebugLoc dl, SelectionDAG &DAG,
278 SmallVectorImpl<SDValue> &InVals) const {
279 // MSP430 target does not yet support tail call optimization.
280 isTailCall = false;
281
282 switch (CallConv) {
283 default:
284 llvm_unreachable("Unsupported calling convention");
285 case CallingConv::Fast:
286 case CallingConv::C:
287 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
288 Outs, OutVals, Ins, dl, DAG, InVals);
289 case CallingConv::MSP430_INTR:
290 report_fatal_error("ISRs cannot be called directly");
291 return SDValue();
292 }
293 }
294
295 /// LowerCCCArguments - transform physical registers into virtual registers and
296 /// generate load operations for arguments places on the stack.
297 // FIXME: struct return stuff
298 // FIXME: varargs
299 SDValue
300 MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
301 CallingConv::ID CallConv,
302 bool isVarArg,
303 const SmallVectorImpl<ISD::InputArg>
304 &Ins,
305 DebugLoc dl,
306 SelectionDAG &DAG,
307 SmallVectorImpl<SDValue> &InVals)
308 const {
309 MachineFunction &MF = DAG.getMachineFunction();
310 MachineFrameInfo *MFI = MF.getFrameInfo();
311 MachineRegisterInfo &RegInfo = MF.getRegInfo();
312
313 // Assign locations to all of the incoming arguments.
314 SmallVector<CCValAssign, 16> ArgLocs;
315 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
316 getTargetMachine(), ArgLocs, *DAG.getContext());
317 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
318
319 assert(!isVarArg && "Varargs not supported yet");
320
321 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
322 CCValAssign &VA = ArgLocs[i];
323 if (VA.isRegLoc()) {
324 // Arguments passed in registers
325 EVT RegVT = VA.getLocVT();
326 switch (RegVT.getSimpleVT().SimpleTy) {
327 default:
328 {
329 #ifndef NDEBUG
330 errs() << "LowerFormalArguments Unhandled argument type: "
331 << RegVT.getSimpleVT().SimpleTy << "\n";
332 #endif
333 llvm_unreachable(0);
334 }
335 case MVT::i16:
336 unsigned VReg =
337 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
338 RegInfo.addLiveIn(VA.getLocReg(), VReg);
339 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
340
341 // If this is an 8-bit value, it is really passed promoted to 16
342 // bits. Insert an assert[sz]ext to capture this, then truncate to the
343 // right size.
344 if (VA.getLocInfo() == CCValAssign::SExt)
345 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
346 DAG.getValueType(VA.getValVT()));
347 else if (VA.getLocInfo() == CCValAssign::ZExt)
348 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
349 DAG.getValueType(VA.getValVT()));
350
351 if (VA.getLocInfo() != CCValAssign::Full)
352 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
353
354 InVals.push_back(ArgValue);
355 }
356 } else {
357 // Sanity check
358 assert(VA.isMemLoc());
359 // Load the argument to a virtual register
360 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
361 if (ObjSize > 2) {
362 errs() << "LowerFormalArguments Unhandled argument type: "
363 << EVT(VA.getLocVT()).getEVTString()
364 << "\n";
365 }
366 // Create the frame index object for this incoming parameter...
367 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
368
369 // Create the SelectionDAG nodes corresponding to a load
370 //from this parameter
371 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
372 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
373 MachinePointerInfo::getFixedStack(FI),
374 false, false, 0));
375 }
376 }
377
378 return Chain;
379 }
380
381 SDValue
382 MSP430TargetLowering::LowerReturn(SDValue Chain,
383 CallingConv::ID CallConv, bool isVarArg,
384 const SmallVectorImpl<ISD::OutputArg> &Outs,
385 const SmallVectorImpl<SDValue> &OutVals,
386 DebugLoc dl, SelectionDAG &DAG) const {
387
388 // CCValAssign - represent the assignment of the return value to a location
389 SmallVector<CCValAssign, 16> RVLocs;
390
391 // ISRs cannot return any value.
392 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
393 report_fatal_error("ISRs cannot return any value");
394 return SDValue();
395 }
396
397 // CCState - Info about the registers and stack slot.
398 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
399 getTargetMachine(), RVLocs, *DAG.getContext());
400
401 // Analize return values.
402 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
403
404 // If this is the first return lowered for this function, add the regs to the
405 // liveout set for the function.
406 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
407 for (unsigned i = 0; i != RVLocs.size(); ++i)
408 if (RVLocs[i].isRegLoc())
409 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
410 }
411
412 SDValue Flag;
413
414 // Copy the result values into the output registers.
415 for (unsigned i = 0; i != RVLocs.size(); ++i) {
416 CCValAssign &VA = RVLocs[i];
417 assert(VA.isRegLoc() && "Can only return in registers!");
418
419 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
420 OutVals[i], Flag);
421
422 // Guarantee that all emitted copies are stuck together,
423 // avoiding something bad.
424 Flag = Chain.getValue(1);
425 }
426
427 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
428 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
429
430 if (Flag.getNode())
431 return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
432
433 // Return Void
434 return DAG.getNode(Opc, dl, MVT::Other, Chain);
435 }
436
437 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
438 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
439 /// TODO: sret.
440 SDValue
441 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
442 CallingConv::ID CallConv, bool isVarArg,
443 bool isTailCall,
444 const SmallVectorImpl<ISD::OutputArg>
445 &Outs,
446 const SmallVectorImpl<SDValue> &OutVals,
447 const SmallVectorImpl<ISD::InputArg> &Ins,
448 DebugLoc dl, SelectionDAG &DAG,
449 SmallVectorImpl<SDValue> &InVals) const {
450 // Analyze operands of the call, assigning locations to each operand.
451 SmallVector<CCValAssign, 16> ArgLocs;
452 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
453 getTargetMachine(), ArgLocs, *DAG.getContext());
454
455 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
456
457 // Get a count of how many bytes are to be pushed on the stack.
458 unsigned NumBytes = CCInfo.getNextStackOffset();
459
460 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
461 getPointerTy(), true));
462
463 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
464 SmallVector<SDValue, 12> MemOpChains;
465 SDValue StackPtr;
466
467 // Walk the register/memloc assignments, inserting copies/loads.
468 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
469 CCValAssign &VA = ArgLocs[i];
470
471 SDValue Arg = OutVals[i];
472
473 // Promote the value if needed.
474 switch (VA.getLocInfo()) {
475 default: llvm_unreachable("Unknown loc info!");
476 case CCValAssign::Full: break;
477 case CCValAssign::SExt:
478 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
479 break;
480 case CCValAssign::ZExt:
481 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
482 break;
483 case CCValAssign::AExt:
484 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
485 break;
486 }
487
488 // Arguments that can be passed on register must be kept at RegsToPass
489 // vector
490 if (VA.isRegLoc()) {
491 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
492 } else {
493 assert(VA.isMemLoc());
494
495 if (StackPtr.getNode() == 0)
496 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
497
498 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
499 StackPtr,
500 DAG.getIntPtrConstant(VA.getLocMemOffset()));
501
502
503 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
504 MachinePointerInfo(),false, false, 0));
505 }
506 }
507
508 // Transform all store nodes into one single node because all store nodes are
509 // independent of each other.
510 if (!MemOpChains.empty())
511 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
512 &MemOpChains[0], MemOpChains.size());
513
514 // Build a sequence of copy-to-reg nodes chained together with token chain and
515 // flag operands which copy the outgoing args into registers. The InFlag in
516 // necessary since all emitted instructions must be stuck together.
517 SDValue InFlag;
518 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
519 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
520 RegsToPass[i].second, InFlag);
521 InFlag = Chain.getValue(1);
522 }
523
524 // If the callee is a GlobalAddress node (quite common, every direct call is)
525 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
526 // Likewise ExternalSymbol -> TargetExternalSymbol.
527 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
528 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
529 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
530 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
531
532 // Returns a chain & a flag for retval copy to use.
533 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
534 SmallVector<SDValue, 8> Ops;
535 Ops.push_back(Chain);
536 Ops.push_back(Callee);
537
538 // Add argument registers to the end of the list so that they are
539 // known live into the call.
540 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
541 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
542 RegsToPass[i].second.getValueType()));
543
544 if (InFlag.getNode())
545 Ops.push_back(InFlag);
546
547 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
548 InFlag = Chain.getValue(1);
549
550 // Create the CALLSEQ_END node.
551 Chain = DAG.getCALLSEQ_END(Chain,
552 DAG.getConstant(NumBytes, getPointerTy(), true),
553 DAG.getConstant(0, getPointerTy(), true),
554 InFlag);
555 InFlag = Chain.getValue(1);
556
557 // Handle result values, copying them out of physregs into vregs that we
558 // return.
559 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
560 DAG, InVals);
561 }
562
563 /// LowerCallResult - Lower the result values of a call into the
564 /// appropriate copies out of appropriate physical registers.
565 ///
566 SDValue
567 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
568 CallingConv::ID CallConv, bool isVarArg,
569 const SmallVectorImpl<ISD::InputArg> &Ins,
570 DebugLoc dl, SelectionDAG &DAG,
571 SmallVectorImpl<SDValue> &InVals) const {
572
573 // Assign locations to each value returned by this call.
574 SmallVector<CCValAssign, 16> RVLocs;
575 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
576 getTargetMachine(), RVLocs, *DAG.getContext());
577
578 CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
579
580 // Copy all of the result registers out of their specified physreg.
581 for (unsigned i = 0; i != RVLocs.size(); ++i) {
582 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
583 RVLocs[i].getValVT(), InFlag).getValue(1);
584 InFlag = Chain.getValue(2);
585 InVals.push_back(Chain.getValue(0));
586 }
587
588 return Chain;
589 }
590
591 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
592 SelectionDAG &DAG) const {
593 unsigned Opc = Op.getOpcode();
594 SDNode* N = Op.getNode();
595 EVT VT = Op.getValueType();
596 DebugLoc dl = N->getDebugLoc();
597
598 // Expand non-constant shifts to loops:
599 if (!isa<ConstantSDNode>(N->getOperand(1)))
600 switch (Opc) {
601 default:
602 assert(0 && "Invalid shift opcode!");
603 case ISD::SHL:
604 return DAG.getNode(MSP430ISD::SHL, dl,
605 VT, N->getOperand(0), N->getOperand(1));
606 case ISD::SRA:
607 return DAG.getNode(MSP430ISD::SRA, dl,
608 VT, N->getOperand(0), N->getOperand(1));
609 case ISD::SRL:
610 return DAG.getNode(MSP430ISD::SRL, dl,
611 VT, N->getOperand(0), N->getOperand(1));
612 }
613
614 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
615
616 // Expand the stuff into sequence of shifts.
617 // FIXME: for some shift amounts this might be done better!
618 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
619 SDValue Victim = N->getOperand(0);
620
621 if (Opc == ISD::SRL && ShiftAmount) {
622 // Emit a special goodness here:
623 // srl A, 1 => clrc; rrc A
624 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
625 ShiftAmount -= 1;
626 }
627
628 while (ShiftAmount--)
629 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
630 dl, VT, Victim);
631
632 return Victim;
633 }
634
635 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
636 SelectionDAG &DAG) const {
637 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
638 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
639
640 // Create the TargetGlobalAddress node, folding in the constant offset.
641 SDValue Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
642 getPointerTy(), Offset);
643 return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
644 getPointerTy(), Result);
645 }
646
647 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
648 SelectionDAG &DAG) const {
649 DebugLoc dl = Op.getDebugLoc();
650 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
651 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
652
653 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
654 }
655
656 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
657 SelectionDAG &DAG) const {
658 DebugLoc dl = Op.getDebugLoc();
659 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
660 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
661
662 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
663 }
664
665 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
666 ISD::CondCode CC,
667 DebugLoc dl, SelectionDAG &DAG) {
668 // FIXME: Handle bittests someday
669 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
670
671 // FIXME: Handle jump negative someday
672 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
673 switch (CC) {
674 default: llvm_unreachable("Invalid integer condition!");
675 case ISD::SETEQ:
676 TCC = MSP430CC::COND_E; // aka COND_Z
677 // Minor optimization: if LHS is a constant, swap operands, then the
678 // constant can be folded into comparison.
679 if (LHS.getOpcode() == ISD::Constant)
680 std::swap(LHS, RHS);
681 break;
682 case ISD::SETNE:
683 TCC = MSP430CC::COND_NE; // aka COND_NZ
684 // Minor optimization: if LHS is a constant, swap operands, then the
685 // constant can be folded into comparison.
686 if (LHS.getOpcode() == ISD::Constant)
687 std::swap(LHS, RHS);
688 break;
689 case ISD::SETULE:
690 std::swap(LHS, RHS); // FALLTHROUGH
691 case ISD::SETUGE:
692 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
693 // fold constant into instruction.
694 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
695 LHS = RHS;
696 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
697 TCC = MSP430CC::COND_LO;
698 break;
699 }
700 TCC = MSP430CC::COND_HS; // aka COND_C
701 break;
702 case ISD::SETUGT:
703 std::swap(LHS, RHS); // FALLTHROUGH
704 case ISD::SETULT:
705 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
706 // fold constant into instruction.
707 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
708 LHS = RHS;
709 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
710 TCC = MSP430CC::COND_HS;
711 break;
712 }
713 TCC = MSP430CC::COND_LO; // aka COND_NC
714 break;
715 case ISD::SETLE:
716 std::swap(LHS, RHS); // FALLTHROUGH
717 case ISD::SETGE:
718 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
719 // fold constant into instruction.
720 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
721 LHS = RHS;
722 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
723 TCC = MSP430CC::COND_L;
724 break;
725 }
726 TCC = MSP430CC::COND_GE;
727 break;
728 case ISD::SETGT:
729 std::swap(LHS, RHS); // FALLTHROUGH
730 case ISD::SETLT:
731 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
732 // fold constant into instruction.
733 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
734 LHS = RHS;
735 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
736 TCC = MSP430CC::COND_GE;
737 break;
738 }
739 TCC = MSP430CC::COND_L;
740 break;
741 }
742
743 TargetCC = DAG.getConstant(TCC, MVT::i8);
744 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
745 }
746
747
748 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
749 SDValue Chain = Op.getOperand(0);
750 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
751 SDValue LHS = Op.getOperand(2);
752 SDValue RHS = Op.getOperand(3);
753 SDValue Dest = Op.getOperand(4);
754 DebugLoc dl = Op.getDebugLoc();
755
756 SDValue TargetCC;
757 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
758
759 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
760 Chain, Dest, TargetCC, Flag);
761 }
762
763 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
764 SDValue LHS = Op.getOperand(0);
765 SDValue RHS = Op.getOperand(1);
766 DebugLoc dl = Op.getDebugLoc();
767
768 // If we are doing an AND and testing against zero, then the CMP
769 // will not be generated. The AND (or BIT) will generate the condition codes,
770 // but they are different from CMP.
771 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
772 // lowering & isel wouldn't diverge.
773 bool andCC = false;
774 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
775 if (RHSC->isNullValue() && LHS.hasOneUse() &&
776 (LHS.getOpcode() == ISD::AND ||
777 (LHS.getOpcode() == ISD::TRUNCATE &&
778 LHS.getOperand(0).getOpcode() == ISD::AND))) {
779 andCC = true;
780 }
781 }
782 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
783 SDValue TargetCC;
784 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
785
786 // Get the condition codes directly from the status register, if its easy.
787 // Otherwise a branch will be generated. Note that the AND and BIT
788 // instructions generate different flags than CMP, the carry bit can be used
789 // for NE/EQ.
790 bool Invert = false;
791 bool Shift = false;
792 bool Convert = true;
793 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
794 default:
795 Convert = false;
796 break;
797 case MSP430CC::COND_HS:
798 // Res = SRW & 1, no processing is required
799 break;
800 case MSP430CC::COND_LO:
801 // Res = ~(SRW & 1)
802 Invert = true;
803 break;
804 case MSP430CC::COND_NE:
805 if (andCC) {
806 // C = ~Z, thus Res = SRW & 1, no processing is required
807 } else {
808 // Res = ~((SRW >> 1) & 1)
809 Shift = true;
810 Invert = true;
811 }
812 break;
813 case MSP430CC::COND_E:
814 Shift = true;
815 // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
816 // Res = (SRW >> 1) & 1 is 1 word shorter.
817 break;
818 }
819 EVT VT = Op.getValueType();
820 SDValue One = DAG.getConstant(1, VT);
821 if (Convert) {
822 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
823 MVT::i16, Flag);
824 if (Shift)
825 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
826 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
827 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
828 if (Invert)
829 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
830 return SR;
831 } else {
832 SDValue Zero = DAG.getConstant(0, VT);
833 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
834 SmallVector<SDValue, 4> Ops;
835 Ops.push_back(One);
836 Ops.push_back(Zero);
837 Ops.push_back(TargetCC);
838 Ops.push_back(Flag);
839 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
840 }
841 }
842
843 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
844 SelectionDAG &DAG) const {
845 SDValue LHS = Op.getOperand(0);
846 SDValue RHS = Op.getOperand(1);
847 SDValue TrueV = Op.getOperand(2);
848 SDValue FalseV = Op.getOperand(3);
849 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
850 DebugLoc dl = Op.getDebugLoc();
851
852 SDValue TargetCC;
853 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
854
855 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
856 SmallVector<SDValue, 4> Ops;
857 Ops.push_back(TrueV);
858 Ops.push_back(FalseV);
859 Ops.push_back(TargetCC);
860 Ops.push_back(Flag);
861
862 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
863 }
864
865 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
866 SelectionDAG &DAG) const {
867 SDValue Val = Op.getOperand(0);
868 EVT VT = Op.getValueType();
869 DebugLoc dl = Op.getDebugLoc();
870
871 assert(VT == MVT::i16 && "Only support i16 for now!");
872
873 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
874 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
875 DAG.getValueType(Val.getValueType()));
876 }
877
878 SDValue
879 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
880 MachineFunction &MF = DAG.getMachineFunction();
881 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
882 int ReturnAddrIndex = FuncInfo->getRAIndex();
883
884 if (ReturnAddrIndex == 0) {
885 // Set up a frame object for the return address.
886 uint64_t SlotSize = TD->getPointerSize();
887 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
888 true);
889 FuncInfo->setRAIndex(ReturnAddrIndex);
890 }
891
892 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
893 }
894
895 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
896 SelectionDAG &DAG) const {
897 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
898 MFI->setReturnAddressIsTaken(true);
899
900 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
901 DebugLoc dl = Op.getDebugLoc();
902
903 if (Depth > 0) {
904 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
905 SDValue Offset =
906 DAG.getConstant(TD->getPointerSize(), MVT::i16);
907 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
908 DAG.getNode(ISD::ADD, dl, getPointerTy(),
909 FrameAddr, Offset),
910 MachinePointerInfo(), false, false, 0);
911 }
912
913 // Just load the return address.
914 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
915 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
916 RetAddrFI, MachinePointerInfo(), false, false, 0);
917 }
918
919 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
920 SelectionDAG &DAG) const {
921 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
922 MFI->setFrameAddressIsTaken(true);
923
924 EVT VT = Op.getValueType();
925 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
926 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
927 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
928 MSP430::FPW, VT);
929 while (Depth--)
930 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
931 MachinePointerInfo(),
932 false, false, 0);
933 return FrameAddr;
934 }
935
936 /// getPostIndexedAddressParts - returns true by value, base pointer and
937 /// offset pointer and addressing mode by reference if this node can be
938 /// combined with a load / store to form a post-indexed load / store.
939 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
940 SDValue &Base,
941 SDValue &Offset,
942 ISD::MemIndexedMode &AM,
943 SelectionDAG &DAG) const {
944
945 LoadSDNode *LD = cast<LoadSDNode>(N);
946 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
947 return false;
948
949 EVT VT = LD->getMemoryVT();
950 if (VT != MVT::i8 && VT != MVT::i16)
951 return false;
952
953 if (Op->getOpcode() != ISD::ADD)
954 return false;
955
956 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
957 uint64_t RHSC = RHS->getZExtValue();
958 if ((VT == MVT::i16 && RHSC != 2) ||
959 (VT == MVT::i8 && RHSC != 1))
960 return false;
961
962 Base = Op->getOperand(0);
963 Offset = DAG.getConstant(RHSC, VT);
964 AM = ISD::POST_INC;
965 return true;
966 }
967
968 return false;
969 }
970
971
972 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
973 switch (Opcode) {
974 default: return NULL;
975 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
976 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
977 case MSP430ISD::RRA: return "MSP430ISD::RRA";
978 case MSP430ISD::RLA: return "MSP430ISD::RLA";
979 case MSP430ISD::RRC: return "MSP430ISD::RRC";
980 case MSP430ISD::CALL: return "MSP430ISD::CALL";
981 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
982 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
983 case MSP430ISD::CMP: return "MSP430ISD::CMP";
984 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
985 case MSP430ISD::SHL: return "MSP430ISD::SHL";
986 case MSP430ISD::SRA: return "MSP430ISD::SRA";
987 }
988 }
989
990 bool MSP430TargetLowering::isTruncateFree(const Type *Ty1,
991 const Type *Ty2) const {
992 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
993 return false;
994
995 return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
996 }
997
998 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
999 if (!VT1.isInteger() || !VT2.isInteger())
1000 return false;
1001
1002 return (VT1.getSizeInBits() > VT2.getSizeInBits());
1003 }
1004
1005 bool MSP430TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
1006 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1007 return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1008 }
1009
1010 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1011 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1012 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1013 }
1014
1015 //===----------------------------------------------------------------------===//
1016 // Other Lowering Code
1017 //===----------------------------------------------------------------------===//
1018
1019 MachineBasicBlock*
1020 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1021 MachineBasicBlock *BB) const {
1022 MachineFunction *F = BB->getParent();
1023 MachineRegisterInfo &RI = F->getRegInfo();
1024 DebugLoc dl = MI->getDebugLoc();
1025 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1026
1027 unsigned Opc;
1028 const TargetRegisterClass * RC;
1029 switch (MI->getOpcode()) {
1030 default:
1031 assert(0 && "Invalid shift opcode!");
1032 case MSP430::Shl8:
1033 Opc = MSP430::SHL8r1;
1034 RC = MSP430::GR8RegisterClass;
1035 break;
1036 case MSP430::Shl16:
1037 Opc = MSP430::SHL16r1;
1038 RC = MSP430::GR16RegisterClass;
1039 break;
1040 case MSP430::Sra8:
1041 Opc = MSP430::SAR8r1;
1042 RC = MSP430::GR8RegisterClass;
1043 break;
1044 case MSP430::Sra16:
1045 Opc = MSP430::SAR16r1;
1046 RC = MSP430::GR16RegisterClass;
1047 break;
1048 case MSP430::Srl8:
1049 Opc = MSP430::SAR8r1c;
1050 RC = MSP430::GR8RegisterClass;
1051 break;
1052 case MSP430::Srl16:
1053 Opc = MSP430::SAR16r1c;
1054 RC = MSP430::GR16RegisterClass;
1055 break;
1056 }
1057
1058 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1059 MachineFunction::iterator I = BB;
1060 ++I;
1061
1062 // Create loop block
1063 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1064 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1065
1066 F->insert(I, LoopBB);
1067 F->insert(I, RemBB);
1068
1069 // Update machine-CFG edges by transferring all successors of the current
1070 // block to the block containing instructions after shift.
1071 RemBB->splice(RemBB->begin(), BB,
1072 llvm::next(MachineBasicBlock::iterator(MI)),
1073 BB->end());
1074 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1075
1076 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1077 BB->addSuccessor(LoopBB);
1078 BB->addSuccessor(RemBB);
1079 LoopBB->addSuccessor(RemBB);
1080 LoopBB->addSuccessor(LoopBB);
1081
1082 unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1083 unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1084 unsigned ShiftReg = RI.createVirtualRegister(RC);
1085 unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1086 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1087 unsigned SrcReg = MI->getOperand(1).getReg();
1088 unsigned DstReg = MI->getOperand(0).getReg();
1089
1090 // BB:
1091 // cmp 0, N
1092 // je RemBB
1093 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1094 .addReg(ShiftAmtSrcReg).addImm(0);
1095 BuildMI(BB, dl, TII.get(MSP430::JCC))
1096 .addMBB(RemBB)
1097 .addImm(MSP430CC::COND_E);
1098
1099 // LoopBB:
1100 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1101 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1102 // ShiftReg2 = shift ShiftReg
1103 // ShiftAmt2 = ShiftAmt - 1;
1104 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1105 .addReg(SrcReg).addMBB(BB)
1106 .addReg(ShiftReg2).addMBB(LoopBB);
1107 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1108 .addReg(ShiftAmtSrcReg).addMBB(BB)
1109 .addReg(ShiftAmtReg2).addMBB(LoopBB);
1110 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1111 .addReg(ShiftReg);
1112 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1113 .addReg(ShiftAmtReg).addImm(1);
1114 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1115 .addMBB(LoopBB)
1116 .addImm(MSP430CC::COND_NE);
1117
1118 // RemBB:
1119 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1120 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1121 .addReg(SrcReg).addMBB(BB)
1122 .addReg(ShiftReg2).addMBB(LoopBB);
1123
1124 MI->eraseFromParent(); // The pseudo instruction is gone now.
1125 return RemBB;
1126 }
1127
1128 MachineBasicBlock*
1129 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1130 MachineBasicBlock *BB) const {
1131 unsigned Opc = MI->getOpcode();
1132
1133 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1134 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1135 Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1136 return EmitShiftInstr(MI, BB);
1137
1138 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1139 DebugLoc dl = MI->getDebugLoc();
1140
1141 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1142 "Unexpected instr type to insert");
1143
1144 // To "insert" a SELECT instruction, we actually have to insert the diamond
1145 // control-flow pattern. The incoming instruction knows the destination vreg
1146 // to set, the condition code register to branch on, the true/false values to
1147 // select between, and a branch opcode to use.
1148 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1149 MachineFunction::iterator I = BB;
1150 ++I;
1151
1152 // thisMBB:
1153 // ...
1154 // TrueVal = ...
1155 // cmpTY ccX, r1, r2
1156 // jCC copy1MBB
1157 // fallthrough --> copy0MBB
1158 MachineBasicBlock *thisMBB = BB;
1159 MachineFunction *F = BB->getParent();
1160 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1161 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1162 F->insert(I, copy0MBB);
1163 F->insert(I, copy1MBB);
1164 // Update machine-CFG edges by transferring all successors of the current
1165 // block to the new block which will contain the Phi node for the select.
1166 copy1MBB->splice(copy1MBB->begin(), BB,
1167 llvm::next(MachineBasicBlock::iterator(MI)),
1168 BB->end());
1169 copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1170 // Next, add the true and fallthrough blocks as its successors.
1171 BB->addSuccessor(copy0MBB);
1172 BB->addSuccessor(copy1MBB);
1173
1174 BuildMI(BB, dl, TII.get(MSP430::JCC))
1175 .addMBB(copy1MBB)
1176 .addImm(MI->getOperand(3).getImm());
1177
1178 // copy0MBB:
1179 // %FalseValue = ...
1180 // # fallthrough to copy1MBB
1181 BB = copy0MBB;
1182
1183 // Update machine-CFG edges
1184 BB->addSuccessor(copy1MBB);
1185
1186 // copy1MBB:
1187 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1188 // ...
1189 BB = copy1MBB;
1190 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1191 MI->getOperand(0).getReg())
1192 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1193 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1194
1195 MI->eraseFromParent(); // The pseudo instruction is gone now.
1196 return BB;
1197 }
STM8 backend for LLVM