lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // SystemZ Instruction Predicate Definitions.
  16 def IsZ10 : Predicate<"Subtarget.isZ10()">;
  17
  18 include "SystemZInstrFormats.td"
  19
  20 //===----------------------------------------------------------------------===//
  21 // Type Constraints.
  22 //===----------------------------------------------------------------------===//
  23 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  24 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  25 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  26 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Type Profiles.
  30 //===----------------------------------------------------------------------===//
  31 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
  32 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  33 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  34 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  35 def SDT_BrCond              : SDTypeProfile<0, 2,
  36                                            [SDTCisVT<0, OtherVT>,
  37                                             SDTCisI8<1>]>;
  38 def SDT_SelectCC            : SDTypeProfile<1, 3,
  39                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  40                                             SDTCisI8<3>]>;
  41 def SDT_Address             : SDTypeProfile<1, 1,
  42                                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
  43
  44 //===----------------------------------------------------------------------===//
  45 // SystemZ Specific Node Definitions.
  46 //===----------------------------------------------------------------------===//
  47 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  48                      [SDNPHasChain, SDNPOptInFlag]>;
  49 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  50                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  51 def SystemZcallseq_start :
  52                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  53                         [SDNPHasChain, SDNPOutFlag]>;
  54 def SystemZcallseq_end :
  55                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  56                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  57 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
  58 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
  59 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  60                             [SDNPHasChain, SDNPInFlag]>;
  61 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
  62 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
  63
  64
  65 include "SystemZOperands.td"
  66
  67 //===----------------------------------------------------------------------===//
  68 // Instruction list..
  69
  70 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
  71                               "#ADJCALLSTACKDOWN",
  72                               [(SystemZcallseq_start timm:$amt)]>;
  73 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
  74                               "#ADJCALLSTACKUP",
  75                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
  76
  77 let usesCustomDAGSchedInserter = 1 in {
  78   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
  79                         "# Select32 PSEUDO",
  80                         [(set GR32:$dst,
  81                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
  82   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
  83                         "# Select64 PSEUDO",
  84                         [(set GR64:$dst,
  85                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
  86 }
  87
  88
  89 //===----------------------------------------------------------------------===//
  90 //  Control Flow Instructions...
  91 //
  92
  93 // FIXME: Provide proper encoding!
  94 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
  95   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
  96 }
  97
  98 let isBranch = 1, isTerminator = 1 in {
  99   let isBarrier = 1 in {
 100     def JMP  : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
 101
 102     let isIndirectBranch = 1 in
 103       def JMPr   : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
 104   }
 105
 106   let Uses = [PSW] in {
 107     def JO  : Pseudo<(outs), (ins brtarget:$dst),
 108                      "jo\t$dst",
 109                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_O)]>;
 110     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 111                      "jh\t$dst",
 112                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
 113     def JNLE: Pseudo<(outs), (ins brtarget:$dst),
 114                      "jnle\t$dst",
 115                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE)]>;
 116     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 117                      "jl\t$dst",
 118                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
 119     def JNHE: Pseudo<(outs), (ins brtarget:$dst),
 120                      "jnhe\t$dst",
 121                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE)]>;
 122     def JLH : Pseudo<(outs), (ins brtarget:$dst),
 123                      "jlh\t$dst",
 124                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH)]>;
 125     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 126                      "jne\t$dst",
 127                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
 128     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 129                      "je\t$dst",
 130                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
 131     def JNLH: Pseudo<(outs), (ins brtarget:$dst),
 132                      "jnlh\t$dst",
 133                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH)]>;
 134     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 135                      "jhe\t$dst",
 136                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
 137     def JNL : Pseudo<(outs), (ins brtarget:$dst),
 138                      "jnl\t$dst",
 139                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL)]>;
 140     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 141                      "jle\t$dst",
 142                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
 143     def JNH : Pseudo<(outs), (ins brtarget:$dst),
 144                      "jnh\t$dst",
 145                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH)]>;
 146     def JNO : Pseudo<(outs), (ins brtarget:$dst),
 147                      "jno\t$dst",
 148                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO)]>;
 149   } // Uses = [PSW]
 150 } // isBranch = 1
 151
 152 //===----------------------------------------------------------------------===//
 153 //  Call Instructions...
 154 //
 155
 156 let isCall = 1 in
 157   // All calls clobber the non-callee saved registers. Uses for argument
 158   // registers are added manually.
 159   let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
 160               F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L] in {
 161     def CALLi     : Pseudo<(outs), (ins imm_pcrel:$dst, variable_ops),
 162                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 163     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 164                            "basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 165   }
 166
 167 //===----------------------------------------------------------------------===//
 168 //  Miscellaneous Instructions.
 169 //
 170
 171 let isReMaterializable = 1 in
 172 // FIXME: Provide imm12 variant
 173 // FIXME: Address should be halfword aligned...
 174 def LA64r  : RXI<0x47,
 175                  (outs GR64:$dst), (ins laaddr:$src),
 176                  "lay\t{$dst, $src}",
 177                  [(set GR64:$dst, laaddr:$src)]>;
 178 def LA64rm : RXYI<0x71E3,
 179                   (outs GR64:$dst), (ins i64imm:$src),
 180                   "larl\t{$dst, $src}",
 181                   [(set GR64:$dst,
 182                         (SystemZpcrelwrapper tglobaladdr:$src))]>;
 183
 184 let neverHasSideEffects = 1 in
 185 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 186
 187 //===----------------------------------------------------------------------===//
 188 // Move Instructions
 189
 190 let neverHasSideEffects = 1 in {
 191 def MOV32rr : RRI<0x18,
 192                   (outs GR32:$dst), (ins GR32:$src),
 193                   "lr\t{$dst, $src}",
 194                   []>;
 195 def MOV64rr : RREI<0xB904,
 196                    (outs GR64:$dst), (ins GR64:$src),
 197                    "lgr\t{$dst, $src}",
 198                    []>;
 199 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 200                      "# MOV128 PSEUDO!\n"
 201                      "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 202                      "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
 203                      []>;
 204 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 205                      "# MOV64P PSEUDO!\n"
 206                      "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 207                      "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
 208                      []>;
 209 }
 210
 211 def MOVSX64rr32 : RREI<0xB914,
 212                        (outs GR64:$dst), (ins GR32:$src),
 213                        "lgfr\t{$dst, $src}",
 214                        [(set GR64:$dst, (sext GR32:$src))]>;
 215 def MOVZX64rr32 : RREI<0xB916,
 216                        (outs GR64:$dst), (ins GR32:$src),
 217                        "llgfr\t{$dst, $src}",
 218                        [(set GR64:$dst, (zext GR32:$src))]>;
 219
 220 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 221 def MOV32ri16 : RII<0x8A7,
 222                     (outs GR32:$dst), (ins s16imm:$src),
 223                     "lhi\t{$dst, $src}",
 224                     [(set GR32:$dst, immSExt16:$src)]>;
 225 def MOV64ri16 : RII<0x9A7,
 226                     (outs GR64:$dst), (ins s16imm64:$src),
 227                     "lghi\t{$dst, $src}",
 228                     [(set GR64:$dst, immSExt16:$src)]>;
 229
 230 def MOV64rill16 : RII<0xFA5,
 231                       (outs GR64:$dst), (ins i64imm:$src),
 232                       "llill\t{$dst, $src}",
 233                       [(set GR64:$dst, i64ll16:$src)]>;
 234 def MOV64rilh16 : RII<0xEA5,
 235                       (outs GR64:$dst), (ins i64imm:$src),
 236                       "llilh\t{$dst, $src}",
 237                       [(set GR64:$dst, i64lh16:$src)]>;
 238 def MOV64rihl16 : RII<0xDA5,
 239                       (outs GR64:$dst), (ins i64imm:$src),
 240                       "llihl\t{$dst, $src}",
 241                       [(set GR64:$dst, i64hl16:$src)]>;
 242 def MOV64rihh16 : RII<0xCA5,
 243                       (outs GR64:$dst), (ins i64imm:$src),
 244                       "llihh\t{$dst, $src}",
 245                       [(set GR64:$dst, i64hh16:$src)]>;
 246
 247 def MOV64ri32 : RILI<0x1C0,
 248                      (outs GR64:$dst), (ins s32imm64:$src),
 249                      "lgfi\t{$dst, $src}",
 250                      [(set GR64:$dst, immSExt32:$src)]>;
 251 def MOV64rilo32 : RILI<0xFC0,
 252                        (outs GR64:$dst), (ins i64imm:$src),
 253                        "llilf\t{$dst, $src}",
 254                        [(set GR64:$dst, i64lo32:$src)]>;
 255 def MOV64rihi32 : RILI<0xEC0, (outs GR64:$dst), (ins i64imm:$src),
 256                        "llihf\t{$dst, $src}",
 257                        [(set GR64:$dst, i64hi32:$src)]>;
 258 }
 259
 260 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 261 def MOV32rm  : RXI<0x58,
 262                    (outs GR32:$dst), (ins rriaddr12:$src),
 263                    "l\t{$dst, $src}",
 264                    [(set GR32:$dst, (load rriaddr12:$src))]>;
 265 def MOV32rmy : RXYI<0x58E3,
 266                     (outs GR32:$dst), (ins rriaddr:$src),
 267                     "ly\t{$dst, $src}",
 268                     [(set GR32:$dst, (load rriaddr:$src))]>;
 269 def MOV64rm  : RXYI<0x04E3,
 270                     (outs GR64:$dst), (ins rriaddr:$src),
 271                     "lg\t{$dst, $src}",
 272                     [(set GR64:$dst, (load rriaddr:$src))]>;
 273 def MOV64Prm : Pseudo<(outs GR64P:$dst), (ins rriaddr12:$src),
 274                       "# MOV64P PSEUDO!\n"
 275                       "\tl\t${dst:subreg_odd},  $src\n"
 276                       "\tl\t${dst:subreg_even}, 4+$src",
 277                       [(set GR64P:$dst, (load rriaddr12:$src))]>;
 278 def MOV64Prmy : Pseudo<(outs GR64P:$dst), (ins rriaddr:$src),
 279                        "# MOV64P PSEUDO!\n"
 280                        "\tly\t${dst:subreg_odd},  $src\n"
 281                        "\tly\t${dst:subreg_even}, 4+$src",
 282                        [(set GR64P:$dst, (load rriaddr:$src))]>;
 283 def MOV128rm : Pseudo<(outs GR128:$dst), (ins rriaddr:$src),
 284                       "# MOV128 PSEUDO!\n"
 285                       "\tlg\t${dst:subreg_odd},  $src\n"
 286                       "\tlg\t${dst:subreg_even}, 8+$src",
 287                       [(set GR128:$dst, (load rriaddr:$src))]>;
 288 }
 289
 290 def MOV32mr  : RXI<0x50,
 291                    (outs), (ins rriaddr12:$dst, GR32:$src),
 292                    "st\t{$src, $dst}",
 293                    [(store GR32:$src, rriaddr12:$dst)]>;
 294 def MOV32mry : RXYI<0x50E3,
 295                     (outs), (ins rriaddr:$dst, GR32:$src),
 296                     "sty\t{$src, $dst}",
 297                     [(store GR32:$src, rriaddr:$dst)]>;
 298 def MOV64mr  : RXYI<0x24E3,
 299                     (outs), (ins rriaddr:$dst, GR64:$src),
 300                     "stg\t{$src, $dst}",
 301                     [(store GR64:$src, rriaddr:$dst)]>;
 302 def MOV64Pmr : Pseudo<(outs), (ins rriaddr12:$dst, GR64P:$src),
 303                       "# MOV64P PSEUDO!\n"
 304                       "\tst\t${src:subreg_odd}, $dst\n"
 305                       "\tst\t${src:subreg_even}, 4+$dst",
 306                       [(store GR64P:$src, rriaddr12:$dst)]>;
 307 def MOV64Pmry : Pseudo<(outs), (ins rriaddr:$dst, GR64P:$src),
 308                        "# MOV64P PSEUDO!\n"
 309                        "\tsty\t${src:subreg_odd}, $dst\n"
 310                        "\tsty\t${src:subreg_even}, 4+$dst",
 311                        [(store GR64P:$src, rriaddr:$dst)]>;
 312 def MOV128mr : Pseudo<(outs), (ins rriaddr:$dst, GR128:$src),
 313                       "# MOV128 PSEUDO!\n"
 314                       "\tstg\t${src:subreg_odd}, $dst\n"
 315                       "\tstg\t${src:subreg_even}, 8+$dst",
 316                       [(store GR128:$src, rriaddr:$dst)]>;
 317
 318 def MOV8mi    : SII<0x92,
 319                     (outs), (ins riaddr12:$dst, i32i8imm:$src),
 320                     "mvi\t{$dst, $src}",
 321                     [(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>;
 322 def MOV8miy   : SIYI<0x52EB,
 323                      (outs), (ins riaddr:$dst, i32i8imm:$src),
 324                      "mviy\t{$dst, $src}",
 325                      [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 326
 327 def MOV16mi   : SILI<0xE544,
 328                      (outs), (ins riaddr12:$dst, s16imm:$src),
 329                      "mvhhi\t{$dst, $src}",
 330                      [(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>,
 331                      Requires<[IsZ10]>;
 332 def MOV32mi16 : SILI<0xE54C,
 333                      (outs), (ins riaddr12:$dst, s32imm:$src),
 334                      "mvhi\t{$dst, $src}",
 335                      [(store (i32 immSExt16:$src), riaddr12:$dst)]>,
 336                      Requires<[IsZ10]>;
 337 def MOV64mi16 : SILI<0xE548,
 338                      (outs), (ins riaddr12:$dst, s32imm64:$src),
 339                      "mvghi\t{$dst, $src}",
 340                      [(store (i64 immSExt16:$src), riaddr12:$dst)]>,
 341                      Requires<[IsZ10]>;
 342
 343 // sexts
 344 def MOVSX32rr8  : RREI<0xB926,
 345                        (outs GR32:$dst), (ins GR32:$src),
 346                        "lbr\t{$dst, $src}",
 347                        [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
 348 def MOVSX64rr8  : RREI<0xB906,
 349                        (outs GR64:$dst), (ins GR64:$src),
 350                        "lgbr\t{$dst, $src}",
 351                        [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
 352 def MOVSX32rr16 : RREI<0xB927,
 353                        (outs GR32:$dst), (ins GR32:$src),
 354                        "lhr\t{$dst, $src}",
 355                        [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
 356 def MOVSX64rr16 : RREI<0xB907,
 357                        (outs GR64:$dst), (ins GR64:$src),
 358                        "lghr\t{$dst, $src}",
 359                        [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
 360
 361 // extloads
 362 def MOVSX32rm8   : RXYI<0x76E3,
 363                         (outs GR32:$dst), (ins rriaddr:$src),
 364                         "lb\t{$dst, $src}",
 365                         [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 366 def MOVSX32rm16  : RXI<0x48,
 367                        (outs GR32:$dst), (ins rriaddr12:$src),
 368                        "lh\t{$dst, $src}",
 369                        [(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>;
 370 def MOVSX32rm16y : RXYI<0x78E3,
 371                         (outs GR32:$dst), (ins rriaddr:$src),
 372                         "lhy\t{$dst, $src}",
 373                         [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 374 def MOVSX64rm8   : RXYI<0x77E3,
 375                         (outs GR64:$dst), (ins rriaddr:$src),
 376                         "lgb\t{$dst, $src}",
 377                         [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 378 def MOVSX64rm16  : RXYI<0x15E3,
 379                         (outs GR64:$dst), (ins rriaddr:$src),
 380                         "lgh\t{$dst, $src}",
 381                         [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 382 def MOVSX64rm32  : RXYI<0x14E3,
 383                         (outs GR64:$dst), (ins rriaddr:$src),
 384                         "lgf\t{$dst, $src}",
 385                         [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 386
 387 def MOVZX32rm8  : RXYI<0x94E3,
 388                        (outs GR32:$dst), (ins rriaddr:$src),
 389                        "llc\t{$dst, $src}",
 390                        [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 391 def MOVZX32rm16 : RXYI<0x95E3,
 392                        (outs GR32:$dst), (ins rriaddr:$src),
 393                        "llh\t{$dst, $src}",
 394                        [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 395 def MOVZX64rm8  : RXYI<0x90E3,
 396                        (outs GR64:$dst), (ins rriaddr:$src),
 397                        "llgc\t{$dst, $src}",
 398                        [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 399 def MOVZX64rm16 : RXYI<0x91E3,
 400                        (outs GR64:$dst), (ins rriaddr:$src),
 401                        "llgh\t{$dst, $src}",
 402                        [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 403 def MOVZX64rm32 : RXYI<0x16E3,
 404                        (outs GR64:$dst), (ins rriaddr:$src),
 405                        "llgf\t{$dst, $src}",
 406                        [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 407
 408 // truncstores
 409 def MOV32m8r   : RXI<0x42,
 410                      (outs), (ins rriaddr12:$dst, GR32:$src),
 411                      "stc\t{$src, $dst}",
 412                      [(truncstorei8 GR32:$src, rriaddr12:$dst)]>;
 413
 414 def MOV32m8ry  : RXYI<0x72E3,
 415                       (outs), (ins rriaddr:$dst, GR32:$src),
 416                       "stcy\t{$src, $dst}",
 417                       [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 418
 419 def MOV32m16r  : RXI<0x40,
 420                      (outs), (ins rriaddr12:$dst, GR32:$src),
 421                      "sth\t{$src, $dst}",
 422                      [(truncstorei16 GR32:$src, rriaddr12:$dst)]>;
 423
 424 def MOV32m16ry : RXYI<0x70E3,
 425                       (outs), (ins rriaddr:$dst, GR32:$src),
 426                       "sthy\t{$src, $dst}",
 427                       [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 428
 429 def MOV64m8r   : RXI<0x42,
 430                      (outs), (ins rriaddr12:$dst, GR64:$src),
 431                      "stc\t{$src, $dst}",
 432                      [(truncstorei8 GR64:$src, rriaddr12:$dst)]>;
 433
 434 def MOV64m8ry  : RXYI<0x72E3,
 435                       (outs), (ins rriaddr:$dst, GR64:$src),
 436                       "stcy\t{$src, $dst}",
 437                       [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 438
 439 def MOV64m16r  : RXI<0x40,
 440                      (outs), (ins rriaddr12:$dst, GR64:$src),
 441                      "sth\t{$src, $dst}",
 442                      [(truncstorei16 GR64:$src, rriaddr12:$dst)]>;
 443
 444 def MOV64m16ry : RXYI<0x70E3,
 445                       (outs), (ins rriaddr:$dst, GR64:$src),
 446                       "sthy\t{$src, $dst}",
 447                       [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 448
 449 def MOV64m32r  : RXI<0x50,
 450                      (outs), (ins rriaddr12:$dst, GR64:$src),
 451                      "st\t{$src, $dst}",
 452                      [(truncstorei32 GR64:$src, rriaddr12:$dst)]>;
 453
 454 def MOV64m32ry : RXYI<0x50E3,
 455                       (outs), (ins rriaddr:$dst, GR64:$src),
 456                       "sty\t{$src, $dst}",
 457                       [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 458
 459 // multiple regs moves
 460 // FIXME: should we use multiple arg nodes?
 461 def MOV32mrm  : RSYI<0x90EB,
 462                      (outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 463                      "stmy\t{$from, $to, $dst}",
 464                      []>;
 465 def MOV64mrm  : RSYI<0x24EB,
 466                      (outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 467                      "stmg\t{$from, $to, $dst}",
 468                      []>;
 469 def MOV32rmm  : RSYI<0x90EB,
 470                      (outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 471                      "lmy\t{$from, $to, $dst}",
 472                      []>;
 473 def MOV64rmm  : RSYI<0x04EB,
 474                      (outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 475                      "lmg\t{$from, $to, $dst}",
 476                      []>;
 477
 478 let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in {
 479 def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 480                            "lhi\t${dst:subreg_even}, 0",
 481                            []>;
 482 def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 483                            "lghi\t${dst:subreg_even}, 0",
 484                            []>;
 485 }
 486
 487 // Byte swaps
 488 def BSWAP32rr : RREI<0xB91F,
 489                      (outs GR32:$dst), (ins GR32:$src),
 490                      "lrvr\t{$dst, $src}",
 491                      [(set GR32:$dst, (bswap GR32:$src))]>;
 492 def BSWAP64rr : RREI<0xB90F,
 493                      (outs GR64:$dst), (ins GR64:$src),
 494                      "lrvgr\t{$dst, $src}",
 495                      [(set GR64:$dst, (bswap GR64:$src))]>;
 496
 497 // FIXME: this is invalid pattern for big-endian
 498 //def BSWAP16rm : RXYI<0x1FE3, (outs GR32:$dst), (ins rriaddr:$src),
 499 //                     "lrvh\t{$dst, $src}",
 500 //                     [(set GR32:$dst, (bswap (extloadi32i16 rriaddr:$src)))]>;
 501 def BSWAP32rm : RXYI<0x1EE3, (outs GR32:$dst), (ins rriaddr:$src),
 502                      "lrv\t{$dst, $src}",
 503                      [(set GR32:$dst, (bswap (load rriaddr:$src)))]>;
 504 def BSWAP64rm : RXYI<0x0FE3, (outs GR64:$dst), (ins rriaddr:$src),
 505                      "lrvg\t{$dst, $src}",
 506                      [(set GR64:$dst, (bswap (load rriaddr:$src)))]>;
 507
 508 //===----------------------------------------------------------------------===//
 509 // Arithmetic Instructions
 510
 511 let Defs = [PSW] in {
 512 def NEG32rr : RRI<0x13,
 513                   (outs GR32:$dst), (ins GR32:$src),
 514                   "lcr\t{$dst, $src}",
 515                   [(set GR32:$dst, (ineg GR32:$src)),
 516                    (implicit PSW)]>;
 517 def NEG64rr : RREI<0xB903, (outs GR64:$dst), (ins GR64:$src),
 518                    "lcgr\t{$dst, $src}",
 519                    [(set GR64:$dst, (ineg GR64:$src)),
 520                     (implicit PSW)]>;
 521 def NEG64rr32 : RREI<0xB913, (outs GR64:$dst), (ins GR32:$src),
 522                      "lcgfr\t{$dst, $src}",
 523                      [(set GR64:$dst, (ineg (sext GR32:$src))),
 524                       (implicit PSW)]>;
 525 }
 526
 527 let isTwoAddress = 1 in {
 528
 529 let Defs = [PSW] in {
 530
 531 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 532 def ADD32rr : RRI<0x1A, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 533                      "ar\t{$dst, $src2}",
 534                      [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 535                       (implicit PSW)]>;
 536 def ADD64rr : RREI<0xB908, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 537                      "agr\t{$dst, $src2}",
 538                      [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 539                       (implicit PSW)]>;
 540 }
 541
 542 def ADD32ri16 : RII<0xA7A,
 543                     (outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 544                     "ahi\t{$dst, $src2}",
 545                     [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 546                      (implicit PSW)]>;
 547 def ADD32ri   : RILI<0xC29,
 548                      (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 549                      "afi\t{$dst, $src2}",
 550                      [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 551                       (implicit PSW)]>;
 552 def ADD64ri16 : RILI<0xA7B,
 553                      (outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 554                      "aghi\t{$dst, $src2}",
 555                      [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 556                       (implicit PSW)]>;
 557 def ADD64ri32 : RILI<0xC28,
 558                      (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 559                      "agfi\t{$dst, $src2}",
 560                      [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 561                       (implicit PSW)]>;
 562
 563 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 564 def AND32rr : RRI<0x14,
 565                   (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 566                   "nr\t{$dst, $src2}",
 567                   [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 568 def AND64rr : RREI<0xB980,
 569                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 570                    "ngr\t{$dst, $src2}",
 571                    [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 572 }
 573
 574 def AND32rill16 : RII<0xA57,
 575                       (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 576                       "nill\t{$dst, $src2}",
 577                       [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
 578 def AND64rill16 : RII<0xA57,
 579                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 580                       "nill\t{$dst, $src2}",
 581                       [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
 582
 583 def AND32rilh16 : RII<0xA56,
 584                       (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 585                       "nilh\t{$dst, $src2}",
 586                       [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
 587 def AND64rilh16 : RII<0xA56,
 588                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 589                       "nilh\t{$dst, $src2}",
 590                       [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
 591
 592 def AND64rihl16 : RII<0xA55,
 593                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 594                       "nihl\t{$dst, $src2}",
 595                       [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
 596 def AND64rihh16 : RII<0xA54,
 597                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 598                       "nihh\t{$dst, $src2}",
 599                       [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
 600
 601 def AND32ri     : RILI<0xC0B,
 602                        (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 603                        "nilf\t{$dst, $src2}",
 604                        [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
 605 def AND64rilo32 : RILI<0xC0B,
 606                        (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 607                        "nilf\t{$dst, $src2}",
 608                        [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
 609 def AND64rihi32 : RILI<0xC0A,
 610                        (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 611                        "nihf\t{$dst, $src2}",
 612                        [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
 613
 614 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 615 def OR32rr : RRI<0x16,
 616                  (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 617                  "or\t{$dst, $src2}",
 618                  [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 619 def OR64rr : RREI<0xB981,
 620                   (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 621                   "ogr\t{$dst, $src2}",
 622                   [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 623 }
 624
 625 def OR32ri16  : RII<0xA5B,
 626                     (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 627                     "oill\t{$dst, $src2}",
 628                     [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
 629 def OR32ri16h : RII<0xA5A,
 630                     (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 631                     "oilh\t{$dst, $src2}",
 632                     [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
 633 def OR32ri : RILI<0xC0D,
 634                   (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 635                   "oilf\t{$dst, $src2}",
 636                   [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 637
 638 def OR64rill16 : RII<0xA5B,
 639                      (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 640                      "oill\t{$dst, $src2}",
 641                      [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 642 def OR64rilh16 : RII<0xA5A,
 643                      (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 644                      "oilh\t{$dst, $src2}",
 645                      [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 646 def OR64rihl16 : RII<0xA59,
 647                      (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 648                      "oihl\t{$dst, $src2}",
 649                      [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 650 def OR64rihh16 : RII<0xA58,
 651                      (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 652                      "oihh\t{$dst, $src2}",
 653                      [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 654
 655 def OR64rilo32 : RILI<0xC0D,
 656                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 657                       "oilf\t{$dst, $src2}",
 658                       [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 659 def OR64rihi32 : RILI<0xC0C,
 660                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 661                       "oihf\t{$dst, $src2}",
 662                       [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 663
 664 def SUB32rr : RRI<0x1B,
 665                   (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 666                   "sr\t{$dst, $src2}",
 667                   [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 668 def SUB64rr : RREI<0xB909,
 669                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 670                    "sgr\t{$dst, $src2}",
 671                    [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 672
 673
 674 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 675 def XOR32rr : RRI<0x17,
 676                   (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 677                   "xr\t{$dst, $src2}",
 678                   [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 679 def XOR64rr : RREI<0xB982,
 680                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 681                    "xgr\t{$dst, $src2}",
 682                    [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 683 }
 684
 685 def XOR32ri : RILI<0xC07,
 686                    (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 687                    "xilf\t{$dst, $src2}",
 688                    [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 689
 690 } // Defs = [PSW]
 691
 692 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 693 def MUL32rr : RREI<0xB252,
 694                    (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 695                    "msr\t{$dst, $src2}",
 696                    [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 697 def MUL64rr : RREI<0xB90C,
 698                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 699                    "msgr\t{$dst, $src2}",
 700                    [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 701 }
 702
 703 def MUL64rrP   : RRI<0x1C,
 704                      (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 705                      "mr\t{$dst, $src2}",
 706                      []>;
 707 def UMUL64rrP  : RREI<0xB996,
 708                       (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 709                       "mlr\t{$dst, $src2}",
 710                       []>;
 711 def UMUL128rrP : RREI<0xB986,
 712                       (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 713                       "mlgr\t{$dst, $src2}",
 714                       []>;
 715
 716 def MUL32ri16   : RII<0xA7C,
 717                       (outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 718                       "mhi\t{$dst, $src2}",
 719                       [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 720 def MUL64ri16   : RII<0xA7D,
 721                       (outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 722                       "mghi\t{$dst, $src2}",
 723                       [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 724
 725 def MUL32ri     : RILI<0xC21,
 726                        (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 727                        "msfi\t{$dst, $src2}",
 728                        [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
 729                        Requires<[IsZ10]>;
 730 def MUL64ri32   : RILI<0xC20,
 731                        (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 732                        "msgfi\t{$dst, $src2}",
 733                        [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
 734                        Requires<[IsZ10]>;
 735
 736 def MUL32rm : RXI<0x71,
 737                   (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
 738                   "ms\t{$dst, $src2}",
 739                   [(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>;
 740 def MUL32rmy : RXYI<0xE351,
 741                     (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 742                     "msy\t{$dst, $src2}",
 743                     [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 744 def MUL64rm  : RXYI<0xE30C,
 745                     (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 746                     "msg\t{$dst, $src2}",
 747                     [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 748
 749 def MULSX64rr32 : RREI<0xB91C,
 750                        (outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 751                        "msgfr\t{$dst, $src2}",
 752                        [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 753
 754 def SDIVREM32r : RREI<0xB91D,
 755                       (outs GR128:$dst), (ins GR128:$src1, GR32:$src2),
 756                       "dsgfr\t{$dst, $src2}",
 757                       []>;
 758 def SDIVREM64r : RREI<0xB90D,
 759                       (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 760                       "dsgr\t{$dst, $src2}",
 761                       []>;
 762
 763 def UDIVREM32r : RREI<0xB997,
 764                       (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 765                       "dlr\t{$dst, $src2}",
 766                       []>;
 767 def UDIVREM64r : RREI<0xB987,
 768                       (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 769                       "dlgr\t{$dst, $src2}",
 770                       []>;
 771 let mayLoad = 1 in {
 772 def SDIVREM32m : RXYI<0xE31D,
 773                       (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 774                       "dsgf\t{$dst, $src2}",
 775                       []>;
 776 def SDIVREM64m : RXYI<0xE30D,
 777                       (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 778                       "dsg\t{$dst, $src2}",
 779                       []>;
 780
 781 def UDIVREM32m : RXYI<0xE397, (outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
 782                       "dl\t{$dst, $src2}",
 783                       []>;
 784 def UDIVREM64m : RXYI<0xE387, (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 785                       "dlg\t{$dst, $src2}",
 786                       []>;
 787 } // mayLoad
 788 } // isTwoAddress = 1
 789
 790 //===----------------------------------------------------------------------===//
 791 // Shifts
 792
 793 let isTwoAddress = 1 in
 794 def SRL32rri : RSI<0x88,
 795                    (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 796                    "srl\t{$src, $amt}",
 797                    [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 798 def SRL64rri : RSYI<0xEB0C,
 799                     (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 800                     "srlg\t{$dst, $src, $amt}",
 801                     [(set GR64:$dst, (srl GR64:$src, riaddr:$amt))]>;
 802
 803 let isTwoAddress = 1 in
 804 def SHL32rri : RSI<0x89,
 805                    (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 806                    "sll\t{$src, $amt}",
 807                    [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 808 def SHL64rri : RSYI<0xEB0D,
 809                     (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 810                     "sllg\t{$dst, $src, $amt}",
 811                     [(set GR64:$dst, (shl GR64:$src, riaddr:$amt))]>;
 812
 813 let Defs = [PSW] in {
 814 let isTwoAddress = 1 in
 815 def SRA32rri : RSI<0x8A,
 816                    (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 817                    "sra\t{$src, $amt}",
 818                    [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 819                     (implicit PSW)]>;
 820
 821 def SRA64rri : RSYI<0xEB0A,
 822                     (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 823                     "srag\t{$dst, $src, $amt}",
 824                     [(set GR64:$dst, (sra GR64:$src, riaddr:$amt)),
 825                      (implicit PSW)]>;
 826 } // Defs = [PSW]
 827
 828 def ROTL32rri : RSYI<0xEB1D,
 829                      (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 830                      "rll\t{$dst, $src, $amt}",
 831                      [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
 832 def ROTL64rri : RSYI<0xEB1C,
 833                      (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 834                      "rllg\t{$dst, $src, $amt}",
 835                      [(set GR64:$dst, (rotl GR64:$src, riaddr:$amt))]>;
 836
 837 //===----------------------------------------------------------------------===//
 838 // Test instructions (like AND but do not produce any result)
 839
 840 // Integer comparisons
 841 let Defs = [PSW] in {
 842 def CMP32rr : RRI<0x19,
 843                   (outs), (ins GR32:$src1, GR32:$src2),
 844                   "cr\t$src1, $src2",
 845                   [(SystemZcmp GR32:$src1, GR32:$src2),
 846                    (implicit PSW)]>;
 847 def CMP64rr : RREI<0xB920,
 848                    (outs), (ins GR64:$src1, GR64:$src2),
 849                    "cgr\t$src1, $src2",
 850                    [(SystemZcmp GR64:$src1, GR64:$src2),
 851                     (implicit PSW)]>;
 852
 853 def CMP32ri   : RILI<0xC2D,
 854                      (outs), (ins GR32:$src1, s32imm:$src2),
 855                      "cfi\t$src1, $src2",
 856                      [(SystemZcmp GR32:$src1, imm:$src2),
 857                       (implicit PSW)]>;
 858 def CMP64ri32 : RILI<0xC2C,
 859                      (outs), (ins GR64:$src1, s32imm64:$src2),
 860                      "cgfi\t$src1, $src2",
 861                      [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
 862                       (implicit PSW)]>;
 863
 864 def CMP32rm : RXI<0x59,
 865                   (outs), (ins GR32:$src1, rriaddr12:$src2),
 866                   "c\t$src1, $src2",
 867                   [(SystemZcmp GR32:$src1, (load rriaddr12:$src2)),
 868                    (implicit PSW)]>;
 869 def CMP32rmy : RXYI<0xE359,
 870                     (outs), (ins GR32:$src1, rriaddr:$src2),
 871                     "cy\t$src1, $src2",
 872                     [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
 873                      (implicit PSW)]>;
 874 def CMP64rm  : RXYI<0xE320,
 875                     (outs), (ins GR64:$src1, rriaddr:$src2),
 876                     "cg\t$src1, $src2",
 877                     [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
 878                      (implicit PSW)]>;
 879
 880 def UCMP32rr : RRI<0x15,
 881                    (outs), (ins GR32:$src1, GR32:$src2),
 882                    "clr\t$src1, $src2",
 883                    [(SystemZucmp GR32:$src1, GR32:$src2),
 884                     (implicit PSW)]>;
 885 def UCMP64rr : RREI<0xB921,
 886                     (outs), (ins GR64:$src1, GR64:$src2),
 887                     "clgr\t$src1, $src2",
 888                     [(SystemZucmp GR64:$src1, GR64:$src2),
 889                      (implicit PSW)]>;
 890
 891 def UCMP32ri   : RILI<0xC2F,
 892                       (outs), (ins GR32:$src1, i32imm:$src2),
 893                       "clfi\t$src1, $src2",
 894                       [(SystemZucmp GR32:$src1, imm:$src2),
 895                        (implicit PSW)]>;
 896 def UCMP64ri32 : RILI<0xC2E,
 897                       (outs), (ins GR64:$src1, i64i32imm:$src2),
 898                       "clgfi\t$src1, $src2",
 899                       [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
 900                        (implicit PSW)]>;
 901
 902 def UCMP32rm  : RXI<0x55,
 903                     (outs), (ins GR32:$src1, rriaddr12:$src2),
 904                     "cl\t$src1, $src2",
 905                     [(SystemZucmp GR32:$src1, (load rriaddr12:$src2)),
 906                      (implicit PSW)]>;
 907 def UCMP32rmy : RXYI<0xE355,
 908                      (outs), (ins GR32:$src1, rriaddr:$src2),
 909                      "cly\t$src1, $src2",
 910                      [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
 911                       (implicit PSW)]>;
 912 def UCMP64rm  : RXYI<0xE351,
 913                      (outs), (ins GR64:$src1, rriaddr:$src2),
 914                      "clg\t$src1, $src2",
 915                      [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
 916                       (implicit PSW)]>;
 917
 918 def CMPSX64rr32  : RREI<0xB930,
 919                         (outs), (ins GR64:$src1, GR32:$src2),
 920                         "cgfr\t$src1, $src2",
 921                         [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
 922                          (implicit PSW)]>;
 923 def UCMPZX64rr32 : RREI<0xB931,
 924                         (outs), (ins GR64:$src1, GR32:$src2),
 925                         "clgfr\t$src1, $src2",
 926                         [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
 927                          (implicit PSW)]>;
 928
 929 def CMPSX64rm32   : RXYI<0xE330,
 930                          (outs), (ins GR64:$src1, rriaddr:$src2),
 931                          "cgf\t$src1, $src2",
 932                          [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
 933                           (implicit PSW)]>;
 934 def UCMPZX64rm32  : RXYI<0xE331,
 935                          (outs), (ins GR64:$src1, rriaddr:$src2),
 936                          "clgf\t$src1, $src2",
 937                          [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
 938                           (implicit PSW)]>;
 939
 940 // FIXME: Add other crazy ucmp forms
 941
 942 } // Defs = [PSW]
 943
 944 //===----------------------------------------------------------------------===//
 945 // Non-Instruction Patterns.
 946 //===----------------------------------------------------------------------===//
 947
 948 // ConstPools, JumpTables
 949 def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
 950 def : Pat<(SystemZpcrelwrapper tconstpool:$src), (LA64rm tconstpool:$src)>;
 951
 952 // anyext
 953 def : Pat<(i64 (anyext GR32:$src)),
 954           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
 955
 956 // calls
 957 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
 958 def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
 959
 960 //===----------------------------------------------------------------------===//
 961 // Peepholes.
 962 //===----------------------------------------------------------------------===//
 963
 964 // FIXME: use add/sub tricks with 32678/-32768
 965
 966 // Arbitrary immediate support.
 967 def : Pat<(i32 imm:$src),
 968           (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;
 969
 970 // Implement in terms of LLIHF/OILF.
 971 def : Pat<(i64 imm:$imm),
 972           (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
 973
 974 // trunc patterns
 975 def : Pat<(i32 (trunc GR64:$src)),
 976           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
 977
 978 // sext_inreg patterns
 979 def : Pat<(sext_inreg GR64:$src, i32),
 980           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
 981
 982 // extload patterns
 983 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
 984 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
 985 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
 986 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
 987 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
 988
 989 // muls
 990 def : Pat<(mulhs GR32:$src1, GR32:$src2),
 991           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
 992                                                    GR32:$src1, subreg_odd32),
 993                                     GR32:$src2),
 994                           subreg_even32)>;
 995
 996 def : Pat<(mulhu GR32:$src1, GR32:$src2),
 997           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
 998                                                     GR32:$src1, subreg_odd32),
 999                                      GR32:$src2),
1000                           subreg_even32)>;
1001 def : Pat<(mulhu GR64:$src1, GR64:$src2),
1002           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1003                                                      GR64:$src1, subreg_odd),
1004                                       GR64:$src2),
1005                           subreg_even)>;