lib/Target/CellSPU/SPUISelDAGToDAG.cpp

   1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a pattern matching instruction selector for the Cell SPU,
  11 // converting from a legalized dag to a SPU-target dag.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "SPU.h"
  16 #include "SPUTargetMachine.h"
  17 #include "SPUISelLowering.h"
  18 #include "SPUHazardRecognizers.h"
  19 #include "SPUFrameInfo.h"
  20 #include "SPURegisterNames.h"
  21 #include "SPUTargetMachine.h"
  22 #include "llvm/CodeGen/MachineConstantPool.h"
  23 #include "llvm/CodeGen/MachineInstrBuilder.h"
  24 #include "llvm/CodeGen/MachineFunction.h"
  25 #include "llvm/CodeGen/SelectionDAG.h"
  26 #include "llvm/CodeGen/SelectionDAGISel.h"
  27 #include "llvm/CodeGen/PseudoSourceValue.h"
  28 #include "llvm/Target/TargetOptions.h"
  29 #include "llvm/ADT/Statistic.h"
  30 #include "llvm/Constants.h"
  31 #include "llvm/GlobalValue.h"
  32 #include "llvm/Intrinsics.h"
  33 #include "llvm/Support/Debug.h"
  34 #include "llvm/Support/ErrorHandling.h"
  35 #include "llvm/Support/MathExtras.h"
  36 #include "llvm/Support/Compiler.h"
  37 #include "llvm/Support/raw_ostream.h"
  38
  39 using namespace llvm;
  40
  41 namespace {
  42   //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
  43   bool
  44   isI64IntS10Immediate(ConstantSDNode *CN)
  45   {
  46     return isS10Constant(CN->getSExtValue());
  47   }
  48
  49   //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
  50   bool
  51   isI32IntS10Immediate(ConstantSDNode *CN)
  52   {
  53     return isS10Constant(CN->getSExtValue());
  54   }
  55
  56   //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
  57   bool
  58   isI32IntU10Immediate(ConstantSDNode *CN)
  59   {
  60     return isU10Constant(CN->getSExtValue());
  61   }
  62
  63   //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
  64   bool
  65   isI16IntS10Immediate(ConstantSDNode *CN)
  66   {
  67     return isS10Constant(CN->getSExtValue());
  68   }
  69
  70   //! SDNode predicate for i16 sign-extended, 10-bit immediate values
  71   bool
  72   isI16IntS10Immediate(SDNode *N)
  73   {
  74     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
  75     return (CN != 0 && isI16IntS10Immediate(CN));
  76   }
  77
  78   //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
  79   bool
  80   isI16IntU10Immediate(ConstantSDNode *CN)
  81   {
  82     return isU10Constant((short) CN->getZExtValue());
  83   }
  84
  85   //! SDNode predicate for i16 sign-extended, 10-bit immediate values
  86   bool
  87   isI16IntU10Immediate(SDNode *N)
  88   {
  89     return (N->getOpcode() == ISD::Constant
  90             && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
  91   }
  92
  93   //! ConstantSDNode predicate for signed 16-bit values
  94   /*!
  95     \arg CN The constant SelectionDAG node holding the value
  96     \arg Imm The returned 16-bit value, if returning true
  97
  98     This predicate tests the value in \a CN to see whether it can be
  99     represented as a 16-bit, sign-extended quantity. Returns true if
 100     this is the case.
 101    */
 102   bool
 103   isIntS16Immediate(ConstantSDNode *CN, short &Imm)
 104   {
 105     MVT vt = CN->getValueType(0);
 106     Imm = (short) CN->getZExtValue();
 107     if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
 108       return true;
 109     } else if (vt == MVT::i32) {
 110       int32_t i_val = (int32_t) CN->getZExtValue();
 111       short s_val = (short) i_val;
 112       return i_val == s_val;
 113     } else {
 114       int64_t i_val = (int64_t) CN->getZExtValue();
 115       short s_val = (short) i_val;
 116       return i_val == s_val;
 117     }
 118
 119     return false;
 120   }
 121
 122   //! SDNode predicate for signed 16-bit values.
 123   bool
 124   isIntS16Immediate(SDNode *N, short &Imm)
 125   {
 126     return (N->getOpcode() == ISD::Constant
 127             && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
 128   }
 129
 130   //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
 131   static bool
 132   isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
 133   {
 134     MVT vt = FPN->getValueType(0);
 135     if (vt == MVT::f32) {
 136       int val = FloatToBits(FPN->getValueAPF().convertToFloat());
 137       int sval = (int) ((val << 16) >> 16);
 138       Imm = (short) val;
 139       return val == sval;
 140     }
 141
 142     return false;
 143   }
 144
 145   bool
 146   isHighLow(const SDValue &Op)
 147   {
 148     return (Op.getOpcode() == SPUISD::IndirectAddr
 149             && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
 150                  && Op.getOperand(1).getOpcode() == SPUISD::Lo)
 151                 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
 152                     && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
 153   }
 154
 155   //===------------------------------------------------------------------===//
 156   //! MVT to "useful stuff" mapping structure:
 157
 158   struct valtype_map_s {
 159     MVT VT;
 160     unsigned ldresult_ins;      /// LDRESULT instruction (0 = undefined)
 161     bool ldresult_imm;          /// LDRESULT instruction requires immediate?
 162     unsigned lrinst;            /// LR instruction
 163   };
 164
 165   const valtype_map_s valtype_map[] = {
 166     { MVT::i8,    SPU::ORBIr8,  true,  SPU::LRr8 },
 167     { MVT::i16,   SPU::ORHIr16, true,  SPU::LRr16 },
 168     { MVT::i32,   SPU::ORIr32,  true,  SPU::LRr32 },
 169     { MVT::i64,   SPU::ORr64,   false, SPU::LRr64 },
 170     { MVT::f32,   SPU::ORf32,   false, SPU::LRf32 },
 171     { MVT::f64,   SPU::ORf64,   false, SPU::LRf64 },
 172     // vector types... (sigh!)
 173     { MVT::v16i8, 0,            false, SPU::LRv16i8 },
 174     { MVT::v8i16, 0,            false, SPU::LRv8i16 },
 175     { MVT::v4i32, 0,            false, SPU::LRv4i32 },
 176     { MVT::v2i64, 0,            false, SPU::LRv2i64 },
 177     { MVT::v4f32, 0,            false, SPU::LRv4f32 },
 178     { MVT::v2f64, 0,            false, SPU::LRv2f64 }
 179   };
 180
 181   const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
 182
 183   const valtype_map_s *getValueTypeMapEntry(MVT VT)
 184   {
 185     const valtype_map_s *retval = 0;
 186     for (size_t i = 0; i < n_valtype_map; ++i) {
 187       if (valtype_map[i].VT == VT) {
 188         retval = valtype_map + i;
 189         break;
 190       }
 191     }
 192
 193
 194 #ifndef NDEBUG
 195     if (retval == 0) {
 196       std::string msg;
 197       raw_string_ostream Msg(msg);
 198       Msg << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
 199            << VT.getMVTString();
 200       llvm_report_error(Msg.str());
 201     }
 202 #endif
 203
 204     return retval;
 205   }
 206
 207   //! Generate the carry-generate shuffle mask.
 208   SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
 209     SmallVector<SDValue, 16 > ShufBytes;
 210
 211     // Create the shuffle mask for "rotating" the borrow up one register slot
 212     // once the borrow is generated.
 213     ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
 214     ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
 215     ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
 216     ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
 217
 218     return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 219                        &ShufBytes[0], ShufBytes.size());
 220   }
 221
 222   //! Generate the borrow-generate shuffle mask
 223   SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
 224     SmallVector<SDValue, 16 > ShufBytes;
 225
 226     // Create the shuffle mask for "rotating" the borrow up one register slot
 227     // once the borrow is generated.
 228     ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
 229     ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
 230     ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
 231     ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
 232
 233     return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 234                        &ShufBytes[0], ShufBytes.size());
 235   }
 236
 237   //===------------------------------------------------------------------===//
 238   /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
 239   /// instructions for SelectionDAG operations.
 240   ///
 241   class SPUDAGToDAGISel :
 242     public SelectionDAGISel
 243   {
 244     SPUTargetMachine &TM;
 245     SPUTargetLowering &SPUtli;
 246     unsigned GlobalBaseReg;
 247
 248   public:
 249     explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
 250       SelectionDAGISel(tm),
 251       TM(tm),
 252       SPUtli(*tm.getTargetLowering())
 253     { }
 254
 255     virtual bool runOnFunction(Function &Fn) {
 256       // Make sure we re-emit a set of the global base reg if necessary
 257       GlobalBaseReg = 0;
 258       SelectionDAGISel::runOnFunction(Fn);
 259       return true;
 260     }
 261
 262     /// getI32Imm - Return a target constant with the specified value, of type
 263     /// i32.
 264     inline SDValue getI32Imm(uint32_t Imm) {
 265       return CurDAG->getTargetConstant(Imm, MVT::i32);
 266     }
 267
 268     /// getI64Imm - Return a target constant with the specified value, of type
 269     /// i64.
 270     inline SDValue getI64Imm(uint64_t Imm) {
 271       return CurDAG->getTargetConstant(Imm, MVT::i64);
 272     }
 273
 274     /// getSmallIPtrImm - Return a target constant of pointer type.
 275     inline SDValue getSmallIPtrImm(unsigned Imm) {
 276       return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
 277       }
 278
 279     SDNode *emitBuildVector(SDValue build_vec) {
 280       MVT vecVT = build_vec.getValueType();
 281       MVT eltVT = vecVT.getVectorElementType();
 282       SDNode *bvNode = build_vec.getNode();
 283       DebugLoc dl = bvNode->getDebugLoc();
 284
 285       // Check to see if this vector can be represented as a CellSPU immediate
 286       // constant by invoking all of the instruction selection predicates:
 287       if (((vecVT == MVT::v8i16) &&
 288            (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
 289           ((vecVT == MVT::v4i32) &&
 290            ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
 291             (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
 292             (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
 293             (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
 294           ((vecVT == MVT::v2i64) &&
 295            ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
 296             (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
 297             (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
 298         return Select(build_vec);
 299
 300       // No, need to emit a constant pool spill:
 301       std::vector<Constant*> CV;
 302
 303       for (size_t i = 0; i < build_vec.getNumOperands(); ++i) {
 304         ConstantSDNode *V = dyn_cast<ConstantSDNode > (build_vec.getOperand(i));
 305         CV.push_back(const_cast<ConstantInt *> (V->getConstantIntValue()));
 306       }
 307
 308       Constant *CP = ConstantVector::get(CV);
 309       SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
 310       unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
 311       SDValue CGPoolOffset =
 312               SPU::LowerConstantPool(CPIdx, *CurDAG,
 313                                      SPUtli.getSPUTargetMachine());
 314       return SelectCode(CurDAG->getLoad(build_vec.getValueType(), dl,
 315                                         CurDAG->getEntryNode(), CGPoolOffset,
 316                                         PseudoSourceValue::getConstantPool(), 0,
 317                                         false, Alignment));
 318     }
 319
 320     /// Select - Convert the specified operand from a target-independent to a
 321     /// target-specific node if it hasn't already been changed.
 322     SDNode *Select(SDValue Op);
 323
 324     //! Emit the instruction sequence for i64 shl
 325     SDNode *SelectSHLi64(SDValue &Op, MVT OpVT);
 326
 327     //! Emit the instruction sequence for i64 srl
 328     SDNode *SelectSRLi64(SDValue &Op, MVT OpVT);
 329
 330     //! Emit the instruction sequence for i64 sra
 331     SDNode *SelectSRAi64(SDValue &Op, MVT OpVT);
 332
 333     //! Emit the necessary sequence for loading i64 constants:
 334     SDNode *SelectI64Constant(SDValue &Op, MVT OpVT, DebugLoc dl);
 335
 336     //! Alternate instruction emit sequence for loading i64 constants
 337     SDNode *SelectI64Constant(uint64_t i64const, MVT OpVT, DebugLoc dl);
 338
 339     //! Returns true if the address N is an A-form (local store) address
 340     bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
 341                          SDValue &Index);
 342
 343     //! D-form address predicate
 344     bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
 345                          SDValue &Index);
 346
 347     /// Alternate D-form address using i7 offset predicate
 348     bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
 349                           SDValue &Base);
 350
 351     /// D-form address selection workhorse
 352     bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
 353                                SDValue &Base, int minOffset, int maxOffset);
 354
 355     //! Address predicate if N can be expressed as an indexed [r+r] operation.
 356     bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
 357                          SDValue &Index);
 358
 359     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
 360     /// inline asm expressions.
 361     virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
 362                                               char ConstraintCode,
 363                                               std::vector<SDValue> &OutOps) {
 364       SDValue Op0, Op1;
 365       switch (ConstraintCode) {
 366       default: return true;
 367       case 'm':   // memory
 368         if (!SelectDFormAddr(Op, Op, Op0, Op1)
 369             && !SelectAFormAddr(Op, Op, Op0, Op1))
 370           SelectXFormAddr(Op, Op, Op0, Op1);
 371         break;
 372       case 'o':   // offsetable
 373         if (!SelectDFormAddr(Op, Op, Op0, Op1)
 374             && !SelectAFormAddr(Op, Op, Op0, Op1)) {
 375           Op0 = Op;
 376           Op1 = getSmallIPtrImm(0);
 377         }
 378         break;
 379       case 'v':   // not offsetable
 380 #if 1
 381         llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
 382 #else
 383         SelectAddrIdxOnly(Op, Op, Op0, Op1);
 384 #endif
 385         break;
 386       }
 387
 388       OutOps.push_back(Op0);
 389       OutOps.push_back(Op1);
 390       return false;
 391     }
 392
 393     /// InstructionSelect - This callback is invoked by
 394     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
 395     virtual void InstructionSelect();
 396
 397     virtual const char *getPassName() const {
 398       return "Cell SPU DAG->DAG Pattern Instruction Selection";
 399     }
 400
 401     /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
 402     /// this target when scheduling the DAG.
 403     virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
 404       const TargetInstrInfo *II = TM.getInstrInfo();
 405       assert(II && "No InstrInfo?");
 406       return new SPUHazardRecognizer(*II);
 407     }
 408
 409     // Include the pieces autogenerated from the target description.
 410 #include "SPUGenDAGISel.inc"
 411   };
 412 }
 413
 414 /// InstructionSelect - This callback is invoked by
 415 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
 416 void
 417 SPUDAGToDAGISel::InstructionSelect()
 418 {
 419   DEBUG(BB->dump());
 420
 421   // Select target instructions for the DAG.
 422   SelectRoot(*CurDAG);
 423   CurDAG->RemoveDeadNodes();
 424 }
 425
 426 /*!
 427  \arg Op The ISD instruction operand
 428  \arg N The address to be tested
 429  \arg Base The base address
 430  \arg Index The base address index
 431  */
 432 bool
 433 SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
 434                     SDValue &Index) {
 435   // These match the addr256k operand type:
 436   MVT OffsVT = MVT::i16;
 437   SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
 438
 439   switch (N.getOpcode()) {
 440   case ISD::Constant:
 441   case ISD::ConstantPool:
 442   case ISD::GlobalAddress:
 443     llvm_report_error("SPU SelectAFormAddr: Constant/Pool/Global not lowered.");
 444     /*NOTREACHED*/
 445
 446   case ISD::TargetConstant:
 447   case ISD::TargetGlobalAddress:
 448   case ISD::TargetJumpTable:
 449     llvm_report_error("SPUSelectAFormAddr: Target Constant/Pool/Global "
 450                       "not wrapped as A-form address.");
 451     /*NOTREACHED*/
 452
 453   case SPUISD::AFormAddr:
 454     // Just load from memory if there's only a single use of the location,
 455     // otherwise, this will get handled below with D-form offset addresses
 456     if (N.hasOneUse()) {
 457       SDValue Op0 = N.getOperand(0);
 458       switch (Op0.getOpcode()) {
 459       case ISD::TargetConstantPool:
 460       case ISD::TargetJumpTable:
 461         Base = Op0;
 462         Index = Zero;
 463         return true;
 464
 465       case ISD::TargetGlobalAddress: {
 466         GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
 467         GlobalValue *GV = GSDN->getGlobal();
 468         if (GV->getAlignment() == 16) {
 469           Base = Op0;
 470           Index = Zero;
 471           return true;
 472         }
 473         break;
 474       }
 475       }
 476     }
 477     break;
 478   }
 479   return false;
 480 }
 481
 482 bool
 483 SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
 484                                   SDValue &Base) {
 485   const int minDForm2Offset = -(1 << 7);
 486   const int maxDForm2Offset = (1 << 7) - 1;
 487   return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
 488                                maxDForm2Offset);
 489 }
 490
 491 /*!
 492   \arg Op The ISD instruction (ignored)
 493   \arg N The address to be tested
 494   \arg Base Base address register/pointer
 495   \arg Index Base address index
 496
 497   Examine the input address by a base register plus a signed 10-bit
 498   displacement, [r+I10] (D-form address).
 499
 500   \return true if \a N is a D-form address with \a Base and \a Index set
 501   to non-empty SDValue instances.
 502 */
 503 bool
 504 SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
 505                                  SDValue &Index) {
 506   return DFormAddressPredicate(Op, N, Base, Index,
 507                                SPUFrameInfo::minFrameOffset(),
 508                                SPUFrameInfo::maxFrameOffset());
 509 }
 510
 511 bool
 512 SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
 513                                       SDValue &Index, int minOffset,
 514                                       int maxOffset) {
 515   unsigned Opc = N.getOpcode();
 516   MVT PtrTy = SPUtli.getPointerTy();
 517
 518   if (Opc == ISD::FrameIndex) {
 519     // Stack frame index must be less than 512 (divided by 16):
 520     FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
 521     int FI = int(FIN->getIndex());
 522     DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
 523                << FI << "\n");
 524     if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
 525       Base = CurDAG->getTargetConstant(0, PtrTy);
 526       Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
 527       return true;
 528     }
 529   } else if (Opc == ISD::ADD) {
 530     // Generated by getelementptr
 531     const SDValue Op0 = N.getOperand(0);
 532     const SDValue Op1 = N.getOperand(1);
 533
 534     if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
 535         || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
 536       Base = CurDAG->getTargetConstant(0, PtrTy);
 537       Index = N;
 538       return true;
 539     } else if (Op1.getOpcode() == ISD::Constant
 540                || Op1.getOpcode() == ISD::TargetConstant) {
 541       ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
 542       int32_t offset = int32_t(CN->getSExtValue());
 543
 544       if (Op0.getOpcode() == ISD::FrameIndex) {
 545         FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
 546         int FI = int(FIN->getIndex());
 547         DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
 548                    << " frame index = " << FI << "\n");
 549
 550         if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
 551           Base = CurDAG->getTargetConstant(offset, PtrTy);
 552           Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
 553           return true;
 554         }
 555       } else if (offset > minOffset && offset < maxOffset) {
 556         Base = CurDAG->getTargetConstant(offset, PtrTy);
 557         Index = Op0;
 558         return true;
 559       }
 560     } else if (Op0.getOpcode() == ISD::Constant
 561                || Op0.getOpcode() == ISD::TargetConstant) {
 562       ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
 563       int32_t offset = int32_t(CN->getSExtValue());
 564
 565       if (Op1.getOpcode() == ISD::FrameIndex) {
 566         FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
 567         int FI = int(FIN->getIndex());
 568         DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
 569                    << " frame index = " << FI << "\n");
 570
 571         if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
 572           Base = CurDAG->getTargetConstant(offset, PtrTy);
 573           Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
 574           return true;
 575         }
 576       } else if (offset > minOffset && offset < maxOffset) {
 577         Base = CurDAG->getTargetConstant(offset, PtrTy);
 578         Index = Op1;
 579         return true;
 580       }
 581     }
 582   } else if (Opc == SPUISD::IndirectAddr) {
 583     // Indirect with constant offset -> D-Form address
 584     const SDValue Op0 = N.getOperand(0);
 585     const SDValue Op1 = N.getOperand(1);
 586
 587     if (Op0.getOpcode() == SPUISD::Hi
 588         && Op1.getOpcode() == SPUISD::Lo) {
 589       // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
 590       Base = CurDAG->getTargetConstant(0, PtrTy);
 591       Index = N;
 592       return true;
 593     } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
 594       int32_t offset = 0;
 595       SDValue idxOp;
 596
 597       if (isa<ConstantSDNode>(Op1)) {
 598         ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
 599         offset = int32_t(CN->getSExtValue());
 600         idxOp = Op0;
 601       } else if (isa<ConstantSDNode>(Op0)) {
 602         ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
 603         offset = int32_t(CN->getSExtValue());
 604         idxOp = Op1;
 605       }
 606
 607       if (offset >= minOffset && offset <= maxOffset) {
 608         Base = CurDAG->getTargetConstant(offset, PtrTy);
 609         Index = idxOp;
 610         return true;
 611       }
 612     }
 613   } else if (Opc == SPUISD::AFormAddr) {
 614     Base = CurDAG->getTargetConstant(0, N.getValueType());
 615     Index = N;
 616     return true;
 617   } else if (Opc == SPUISD::LDRESULT) {
 618     Base = CurDAG->getTargetConstant(0, N.getValueType());
 619     Index = N;
 620     return true;
 621   } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
 622     unsigned OpOpc = Op.getOpcode();
 623
 624     if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
 625       // Direct load/store without getelementptr
 626       SDValue Addr, Offs;
 627
 628       // Get the register from CopyFromReg
 629       if (Opc == ISD::CopyFromReg)
 630         Addr = N.getOperand(1);
 631       else
 632         Addr = N;                       // Register
 633
 634       Offs = ((OpOpc == ISD::STORE) ? Op.getOperand(3) : Op.getOperand(2));
 635
 636       if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
 637         if (Offs.getOpcode() == ISD::UNDEF)
 638           Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
 639
 640         Base = Offs;
 641         Index = Addr;
 642         return true;
 643       }
 644     } else {
 645       /* If otherwise unadorned, default to D-form address with 0 offset: */
 646       if (Opc == ISD::CopyFromReg) {
 647         Index = N.getOperand(1);
 648       } else {
 649         Index = N;
 650       }
 651
 652       Base = CurDAG->getTargetConstant(0, Index.getValueType());
 653       return true;
 654     }
 655   }
 656
 657   return false;
 658 }
 659
 660 /*!
 661   \arg Op The ISD instruction operand
 662   \arg N The address operand
 663   \arg Base The base pointer operand
 664   \arg Index The offset/index operand
 665
 666   If the address \a N can be expressed as an A-form or D-form address, returns
 667   false.  Otherwise, creates two operands, Base and Index that will become the
 668   (r)(r) X-form address.
 669 */
 670 bool
 671 SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
 672                                  SDValue &Index) {
 673   if (!SelectAFormAddr(Op, N, Base, Index)
 674       && !SelectDFormAddr(Op, N, Base, Index)) {
 675     // If the address is neither A-form or D-form, punt and use an X-form
 676     // address:
 677     Base = N.getOperand(1);
 678     Index = N.getOperand(0);
 679     return true;
 680   }
 681
 682   return false;
 683 }
 684
 685 //! Convert the operand from a target-independent to a target-specific node
 686 /*!
 687  */
 688 SDNode *
 689 SPUDAGToDAGISel::Select(SDValue Op) {
 690   SDNode *N = Op.getNode();
 691   unsigned Opc = N->getOpcode();
 692   int n_ops = -1;
 693   unsigned NewOpc;
 694   MVT OpVT = Op.getValueType();
 695   SDValue Ops[8];
 696   DebugLoc dl = N->getDebugLoc();
 697
 698   if (N->isMachineOpcode()) {
 699     return NULL;   // Already selected.
 700   }
 701
 702   if (Opc == ISD::FrameIndex) {
 703     int FI = cast<FrameIndexSDNode>(N)->getIndex();
 704     SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
 705     SDValue Imm0 = CurDAG->getTargetConstant(0, Op.getValueType());
 706
 707     if (FI < 128) {
 708       NewOpc = SPU::AIr32;
 709       Ops[0] = TFI;
 710       Ops[1] = Imm0;
 711       n_ops = 2;
 712     } else {
 713       NewOpc = SPU::Ar32;
 714       Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType());
 715       Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, dl, Op.getValueType(),
 716                                              TFI, Imm0), 0);
 717       n_ops = 2;
 718     }
 719   } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
 720     // Catch the i64 constants that end up here. Note: The backend doesn't
 721     // attempt to legalize the constant (it's useless because DAGCombiner
 722     // will insert 64-bit constants and we can't stop it).
 723     return SelectI64Constant(Op, OpVT, Op.getDebugLoc());
 724   } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
 725              && OpVT == MVT::i64) {
 726     SDValue Op0 = Op.getOperand(0);
 727     MVT Op0VT = Op0.getValueType();
 728     MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
 729     MVT OpVecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
 730     SDValue shufMask;
 731
 732     switch (Op0VT.getSimpleVT()) {
 733     default:
 734       llvm_report_error("CellSPU Select: Unhandled zero/any extend MVT");
 735       /*NOTREACHED*/
 736     case MVT::i32:
 737       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 738                                  CurDAG->getConstant(0x80808080, MVT::i32),
 739                                  CurDAG->getConstant(0x00010203, MVT::i32),
 740                                  CurDAG->getConstant(0x80808080, MVT::i32),
 741                                  CurDAG->getConstant(0x08090a0b, MVT::i32));
 742       break;
 743
 744     case MVT::i16:
 745       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 746                                  CurDAG->getConstant(0x80808080, MVT::i32),
 747                                  CurDAG->getConstant(0x80800203, MVT::i32),
 748                                  CurDAG->getConstant(0x80808080, MVT::i32),
 749                                  CurDAG->getConstant(0x80800a0b, MVT::i32));
 750       break;
 751
 752     case MVT::i8:
 753       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 754                                  CurDAG->getConstant(0x80808080, MVT::i32),
 755                                  CurDAG->getConstant(0x80808003, MVT::i32),
 756                                  CurDAG->getConstant(0x80808080, MVT::i32),
 757                                  CurDAG->getConstant(0x8080800b, MVT::i32));
 758       break;
 759     }
 760
 761     SDNode *shufMaskLoad = emitBuildVector(shufMask);
 762     SDNode *PromoteScalar =
 763             SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl, Op0VecVT, Op0));
 764
 765     SDValue zextShuffle =
 766             CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
 767                             SDValue(PromoteScalar, 0),
 768                             SDValue(PromoteScalar, 0),
 769                             SDValue(shufMaskLoad, 0));
 770
 771     // N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
 772     // re-use it in the VEC2PREFSLOT selection without needing to explicitly
 773     // call SelectCode (it's already done for us.)
 774     SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle));
 775     return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
 776                                       zextShuffle));
 777   } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
 778     SDNode *CGLoad =
 779             emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
 780
 781     return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
 782                                       Op.getOperand(0), Op.getOperand(1),
 783                                       SDValue(CGLoad, 0)));
 784   } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
 785     SDNode *CGLoad =
 786             emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl));
 787
 788     return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
 789                                       Op.getOperand(0), Op.getOperand(1),
 790                                       SDValue(CGLoad, 0)));
 791   } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
 792     SDNode *CGLoad =
 793             emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
 794
 795     return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
 796                                       Op.getOperand(0), Op.getOperand(1),
 797                                       SDValue(CGLoad, 0)));
 798   } else if (Opc == ISD::TRUNCATE) {
 799     SDValue Op0 = Op.getOperand(0);
 800     if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
 801         && OpVT == MVT::i32
 802         && Op0.getValueType() == MVT::i64) {
 803       // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
 804       //
 805       // Take advantage of the fact that the upper 32 bits are in the
 806       // i32 preferred slot and avoid shuffle gymnastics:
 807       ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
 808       if (CN != 0) {
 809         unsigned shift_amt = unsigned(CN->getZExtValue());
 810
 811         if (shift_amt >= 32) {
 812           SDNode *hi32 =
 813                   CurDAG->getTargetNode(SPU::ORr32_r64, dl, OpVT,
 814                                         Op0.getOperand(0));
 815
 816           shift_amt -= 32;
 817           if (shift_amt > 0) {
 818             // Take care of the additional shift, if present:
 819             SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
 820             unsigned Opc = SPU::ROTMAIr32_i32;
 821
 822             if (Op0.getOpcode() == ISD::SRL)
 823               Opc = SPU::ROTMr32;
 824
 825             hi32 = CurDAG->getTargetNode(Opc, dl, OpVT, SDValue(hi32, 0),
 826                                          shift);
 827           }
 828
 829           return hi32;
 830         }
 831       }
 832     }
 833   } else if (Opc == ISD::SHL) {
 834     if (OpVT == MVT::i64) {
 835       return SelectSHLi64(Op, OpVT);
 836     }
 837   } else if (Opc == ISD::SRL) {
 838     if (OpVT == MVT::i64) {
 839       return SelectSRLi64(Op, OpVT);
 840     }
 841   } else if (Opc == ISD::SRA) {
 842     if (OpVT == MVT::i64) {
 843       return SelectSRAi64(Op, OpVT);
 844     }
 845   } else if (Opc == ISD::FNEG
 846              && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
 847     DebugLoc dl = Op.getDebugLoc();
 848     // Check if the pattern is a special form of DFNMS:
 849     // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
 850     SDValue Op0 = Op.getOperand(0);
 851     if (Op0.getOpcode() == ISD::FSUB) {
 852       SDValue Op00 = Op0.getOperand(0);
 853       if (Op00.getOpcode() == ISD::FMUL) {
 854         unsigned Opc = SPU::DFNMSf64;
 855         if (OpVT == MVT::v2f64)
 856           Opc = SPU::DFNMSv2f64;
 857
 858         return CurDAG->getTargetNode(Opc, dl, OpVT,
 859                                      Op00.getOperand(0),
 860                                      Op00.getOperand(1),
 861                                      Op0.getOperand(1));
 862       }
 863     }
 864
 865     SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
 866     SDNode *signMask = 0;
 867     unsigned Opc = SPU::XORfneg64;
 868
 869     if (OpVT == MVT::f64) {
 870       signMask = SelectI64Constant(negConst, MVT::i64, dl);
 871     } else if (OpVT == MVT::v2f64) {
 872       Opc = SPU::XORfnegvec;
 873       signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
 874                                                  MVT::v2i64,
 875                                                  negConst, negConst));
 876     }
 877
 878     return CurDAG->getTargetNode(Opc, dl, OpVT,
 879                                  Op.getOperand(0), SDValue(signMask, 0));
 880   } else if (Opc == ISD::FABS) {
 881     if (OpVT == MVT::f64) {
 882       SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
 883       return CurDAG->getTargetNode(SPU::ANDfabs64, dl, OpVT,
 884                                    Op.getOperand(0), SDValue(signMask, 0));
 885     } else if (OpVT == MVT::v2f64) {
 886       SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
 887       SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
 888                                        absConst, absConst);
 889       SDNode *signMask = emitBuildVector(absVec);
 890       return CurDAG->getTargetNode(SPU::ANDfabsvec, dl, OpVT,
 891                                    Op.getOperand(0), SDValue(signMask, 0));
 892     }
 893   } else if (Opc == SPUISD::LDRESULT) {
 894     // Custom select instructions for LDRESULT
 895     MVT VT = N->getValueType(0);
 896     SDValue Arg = N->getOperand(0);
 897     SDValue Chain = N->getOperand(1);
 898     SDNode *Result;
 899     const valtype_map_s *vtm = getValueTypeMapEntry(VT);
 900
 901     if (vtm->ldresult_ins == 0) {
 902       std::string msg;
 903       raw_string_ostream Msg(msg);
 904       Msg << "LDRESULT for unsupported type: "
 905            << VT.getMVTString();
 906       llvm_report_error(Msg.str());
 907     }
 908
 909     Opc = vtm->ldresult_ins;
 910     if (vtm->ldresult_imm) {
 911       SDValue Zero = CurDAG->getTargetConstant(0, VT);
 912
 913       Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
 914     } else {
 915       Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
 916     }
 917
 918     return Result;
 919   } else if (Opc == SPUISD::IndirectAddr) {
 920     // Look at the operands: SelectCode() will catch the cases that aren't
 921     // specifically handled here.
 922     //
 923     // SPUInstrInfo catches the following patterns:
 924     // (SPUindirect (SPUhi ...), (SPUlo ...))
 925     // (SPUindirect $sp, imm)
 926     MVT VT = Op.getValueType();
 927     SDValue Op0 = N->getOperand(0);
 928     SDValue Op1 = N->getOperand(1);
 929     RegisterSDNode *RN;
 930
 931     if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
 932         || (Op0.getOpcode() == ISD::Register
 933             && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
 934                 && RN->getReg() != SPU::R1))) {
 935       NewOpc = SPU::Ar32;
 936       if (Op1.getOpcode() == ISD::Constant) {
 937         ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
 938         Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
 939         NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
 940       }
 941       Ops[0] = Op0;
 942       Ops[1] = Op1;
 943       n_ops = 2;
 944     }
 945   }
 946
 947   if (n_ops > 0) {
 948     if (N->hasOneUse())
 949       return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
 950     else
 951       return CurDAG->getTargetNode(NewOpc, dl, OpVT, Ops, n_ops);
 952   } else
 953     return SelectCode(Op);
 954 }
 955
 956 /*!
 957  * Emit the instruction sequence for i64 left shifts. The basic algorithm
 958  * is to fill the bottom two word slots with zeros so that zeros are shifted
 959  * in as the entire quadword is shifted left.
 960  *
 961  * \note This code could also be used to implement v2i64 shl.
 962  *
 963  * @param Op The shl operand
 964  * @param OpVT Op's machine value value type (doesn't need to be passed, but
 965  * makes life easier.)
 966  * @return The SDNode with the entire instruction sequence
 967  */
 968 SDNode *
 969 SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) {
 970   SDValue Op0 = Op.getOperand(0);
 971   MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
 972   SDValue ShiftAmt = Op.getOperand(1);
 973   MVT ShiftAmtVT = ShiftAmt.getValueType();
 974   SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
 975   SDValue SelMaskVal;
 976   DebugLoc dl = Op.getDebugLoc();
 977
 978   VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
 979   SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
 980   SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
 981   ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT,
 982                                    CurDAG->getTargetConstant(0, OpVT));
 983   VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
 984                                  SDValue(ZeroFill, 0),
 985                                  SDValue(VecOp0, 0),
 986                                  SDValue(SelMask, 0));
 987
 988   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
 989     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
 990     unsigned bits = unsigned(CN->getZExtValue()) & 7;
 991
 992     if (bytes > 0) {
 993       Shift =
 994         CurDAG->getTargetNode(SPU::SHLQBYIv2i64, dl, VecVT,
 995                               SDValue(VecOp0, 0),
 996                               CurDAG->getTargetConstant(bytes, ShiftAmtVT));
 997     }
 998
 999     if (bits > 0) {
1000       Shift =
1001         CurDAG->getTargetNode(SPU::SHLQBIIv2i64, dl, VecVT,
1002                               SDValue((Shift != 0 ? Shift : VecOp0), 0),
1003                               CurDAG->getTargetConstant(bits, ShiftAmtVT));
1004     }
1005   } else {
1006     SDNode *Bytes =
1007       CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1008                             ShiftAmt,
1009                             CurDAG->getTargetConstant(3, ShiftAmtVT));
1010     SDNode *Bits =
1011       CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT,
1012                             ShiftAmt,
1013                             CurDAG->getTargetConstant(7, ShiftAmtVT));
1014     Shift =
1015       CurDAG->getTargetNode(SPU::SHLQBYv2i64, dl, VecVT,
1016                             SDValue(VecOp0, 0), SDValue(Bytes, 0));
1017     Shift =
1018       CurDAG->getTargetNode(SPU::SHLQBIv2i64, dl, VecVT,
1019                             SDValue(Shift, 0), SDValue(Bits, 0));
1020   }
1021
1022   return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1023 }
1024
1025 /*!
1026  * Emit the instruction sequence for i64 logical right shifts.
1027  *
1028  * @param Op The shl operand
1029  * @param OpVT Op's machine value value type (doesn't need to be passed, but
1030  * makes life easier.)
1031  * @return The SDNode with the entire instruction sequence
1032  */
1033 SDNode *
1034 SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) {
1035   SDValue Op0 = Op.getOperand(0);
1036   MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
1037   SDValue ShiftAmt = Op.getOperand(1);
1038   MVT ShiftAmtVT = ShiftAmt.getValueType();
1039   SDNode *VecOp0, *Shift = 0;
1040   DebugLoc dl = Op.getDebugLoc();
1041
1042   VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
1043
1044   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1045     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1046     unsigned bits = unsigned(CN->getZExtValue()) & 7;
1047
1048     if (bytes > 0) {
1049       Shift =
1050         CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, dl, VecVT,
1051                               SDValue(VecOp0, 0),
1052                               CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1053     }
1054
1055     if (bits > 0) {
1056       Shift =
1057         CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, dl, VecVT,
1058                               SDValue((Shift != 0 ? Shift : VecOp0), 0),
1059                               CurDAG->getTargetConstant(bits, ShiftAmtVT));
1060     }
1061   } else {
1062     SDNode *Bytes =
1063       CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1064                             ShiftAmt,
1065                             CurDAG->getTargetConstant(3, ShiftAmtVT));
1066     SDNode *Bits =
1067       CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT,
1068                             ShiftAmt,
1069                             CurDAG->getTargetConstant(7, ShiftAmtVT));
1070
1071     // Ensure that the shift amounts are negated!
1072     Bytes = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
1073                                   SDValue(Bytes, 0),
1074                                   CurDAG->getTargetConstant(0, ShiftAmtVT));
1075
1076     Bits = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
1077                                  SDValue(Bits, 0),
1078                                  CurDAG->getTargetConstant(0, ShiftAmtVT));
1079
1080     Shift =
1081       CurDAG->getTargetNode(SPU::ROTQMBYv2i64, dl, VecVT,
1082                             SDValue(VecOp0, 0), SDValue(Bytes, 0));
1083     Shift =
1084       CurDAG->getTargetNode(SPU::ROTQMBIv2i64, dl, VecVT,
1085                             SDValue(Shift, 0), SDValue(Bits, 0));
1086   }
1087
1088   return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1089 }
1090
1091 /*!
1092  * Emit the instruction sequence for i64 arithmetic right shifts.
1093  *
1094  * @param Op The shl operand
1095  * @param OpVT Op's machine value value type (doesn't need to be passed, but
1096  * makes life easier.)
1097  * @return The SDNode with the entire instruction sequence
1098  */
1099 SDNode *
1100 SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
1101   // Promote Op0 to vector
1102   MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
1103   SDValue ShiftAmt = Op.getOperand(1);
1104   MVT ShiftAmtVT = ShiftAmt.getValueType();
1105   DebugLoc dl = Op.getDebugLoc();
1106
1107   SDNode *VecOp0 =
1108     CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op.getOperand(0));
1109
1110   SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1111   SDNode *SignRot =
1112     CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1113                           SDValue(VecOp0, 0), SignRotAmt);
1114   SDNode *UpperHalfSign =
1115     CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
1116
1117   SDNode *UpperHalfSignMask =
1118     CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1119   SDNode *UpperLowerMask =
1120     CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT,
1121                           CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1122   SDNode *UpperLowerSelect =
1123     CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
1124                           SDValue(UpperHalfSignMask, 0),
1125                           SDValue(VecOp0, 0),
1126                           SDValue(UpperLowerMask, 0));
1127
1128   SDNode *Shift = 0;
1129
1130   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1131     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1132     unsigned bits = unsigned(CN->getZExtValue()) & 7;
1133
1134     if (bytes > 0) {
1135       bytes = 31 - bytes;
1136       Shift =
1137         CurDAG->getTargetNode(SPU::ROTQBYIv2i64, dl, VecVT,
1138                               SDValue(UpperLowerSelect, 0),
1139                               CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1140     }
1141
1142     if (bits > 0) {
1143       bits = 8 - bits;
1144       Shift =
1145         CurDAG->getTargetNode(SPU::ROTQBIIv2i64, dl, VecVT,
1146                               SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1147                               CurDAG->getTargetConstant(bits, ShiftAmtVT));
1148     }
1149   } else {
1150     SDNode *NegShift =
1151       CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
1152                             ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1153
1154     Shift =
1155       CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1156                             SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1157     Shift =
1158       CurDAG->getTargetNode(SPU::ROTQBIv2i64, dl, VecVT,
1159                             SDValue(Shift, 0), SDValue(NegShift, 0));
1160   }
1161
1162   return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1163 }
1164
1165 /*!
1166  Do the necessary magic necessary to load a i64 constant
1167  */
1168 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT,
1169                                            DebugLoc dl) {
1170   ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
1171   return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
1172 }
1173
1174 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, MVT OpVT,
1175                                            DebugLoc dl) {
1176   MVT OpVecVT = MVT::getVectorVT(OpVT, 2);
1177   SDValue i64vec =
1178           SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1179
1180   // Here's where it gets interesting, because we have to parse out the
1181   // subtree handed back in i64vec:
1182
1183   if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
1184     // The degenerate case where the upper and lower bits in the splat are
1185     // identical:
1186     SDValue Op0 = i64vec.getOperand(0);
1187
1188     ReplaceUses(i64vec, Op0);
1189     return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT,
1190                                  SDValue(emitBuildVector(Op0), 0));
1191   } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1192     SDValue lhs = i64vec.getOperand(0);
1193     SDValue rhs = i64vec.getOperand(1);
1194     SDValue shufmask = i64vec.getOperand(2);
1195
1196     if (lhs.getOpcode() == ISD::BIT_CONVERT) {
1197       ReplaceUses(lhs, lhs.getOperand(0));
1198       lhs = lhs.getOperand(0);
1199     }
1200
1201     SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1202                        ? lhs.getNode()
1203                        : emitBuildVector(lhs));
1204
1205     if (rhs.getOpcode() == ISD::BIT_CONVERT) {
1206       ReplaceUses(rhs, rhs.getOperand(0));
1207       rhs = rhs.getOperand(0);
1208     }
1209
1210     SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1211                        ? rhs.getNode()
1212                        : emitBuildVector(rhs));
1213
1214     if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
1215       ReplaceUses(shufmask, shufmask.getOperand(0));
1216       shufmask = shufmask.getOperand(0);
1217     }
1218
1219     SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1220                             ? shufmask.getNode()
1221                             : emitBuildVector(shufmask));
1222
1223     SDNode *shufNode =
1224             Select(CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1225                                    SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1226                                    SDValue(shufMaskNode, 0)));
1227
1228     return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT,
1229                                  SDValue(shufNode, 0));
1230   } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
1231     return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT,
1232                                  SDValue(emitBuildVector(i64vec), 0));
1233   } else {
1234     llvm_report_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
1235                       "condition");
1236   }
1237 }
1238
1239 /// createSPUISelDag - This pass converts a legalized DAG into a
1240 /// SPU-specific DAG, ready for instruction scheduling.
1241 ///
1242 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1243   return new SPUDAGToDAGISel(TM);
1244 }