lib/Target/PowerPC/PPCTargetMachine.cpp

   1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Top-level implementation for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "PPC.h"
  15 #include "PPCTargetAsmInfo.h"
  16 #include "PPCTargetMachine.h"
  17 #include "llvm/Module.h"
  18 #include "llvm/PassManager.h"
  19 #include "llvm/Target/TargetMachineRegistry.h"
  20 #include "llvm/Target/TargetOptions.h"
  21 #include "llvm/Support/FormattedStream.h"
  22 using namespace llvm;
  23
  24 /// PowerPCTargetMachineModule - Note that this is used on hosts that
  25 /// cannot link in a library unless there are references into the
  26 /// library.  In particular, it seems that it is not possible to get
  27 /// things to work on Win32 without this.  Though it is unused, do not
  28 /// remove it.
  29 extern "C" int PowerPCTargetMachineModule;
  30 int PowerPCTargetMachineModule = 0;
  31
  32 // Register the targets
  33 static RegisterTarget<PPC32TargetMachine>
  34 X("ppc32", "PowerPC 32");
  35 static RegisterTarget<PPC64TargetMachine>
  36 Y("ppc64", "PowerPC 64");
  37
  38 // Force static initialization.
  39 extern "C" void LLVMInitializePowerPCTarget() { }
  40
  41 // No assembler printer by default
  42 PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0;
  43
  44 const TargetAsmInfo *PPCTargetMachine::createTargetAsmInfo() const {
  45   if (Subtarget.isDarwin())
  46     return new PPCDarwinTargetAsmInfo(*this);
  47   else
  48     return new PPCLinuxTargetAsmInfo(*this);
  49 }
  50
  51 unsigned PPC32TargetMachine::getJITMatchQuality() {
  52 #if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) || defined(__PPC__)
  53   if (sizeof(void*) == 4)
  54     return 10;
  55 #endif
  56   return 0;
  57 }
  58 unsigned PPC64TargetMachine::getJITMatchQuality() {
  59 #if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) || defined(__PPC__)
  60   if (sizeof(void*) == 8)
  61     return 10;
  62 #endif
  63   return 0;
  64 }
  65
  66 unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
  67   // We strongly match "powerpc-*".
  68   std::string TT = M.getTargetTriple();
  69   if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
  70     return 20;
  71
  72   // If the target triple is something non-powerpc, we don't match.
  73   if (!TT.empty()) return 0;
  74
  75   if (M.getEndianness()  == Module::BigEndian &&
  76       M.getPointerSize() == Module::Pointer32)
  77     return 10;                                   // Weak match
  78   else if (M.getEndianness() != Module::AnyEndianness ||
  79            M.getPointerSize() != Module::AnyPointerSize)
  80     return 0;                                    // Match for some other target
  81
  82   return getJITMatchQuality()/2;
  83 }
  84
  85 unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
  86   // We strongly match "powerpc64-*".
  87   std::string TT = M.getTargetTriple();
  88   if (TT.size() >= 10 && std::string(TT.begin(), TT.begin()+10) == "powerpc64-")
  89     return 20;
  90
  91   if (M.getEndianness()  == Module::BigEndian &&
  92       M.getPointerSize() == Module::Pointer64)
  93     return 10;                                   // Weak match
  94   else if (M.getEndianness() != Module::AnyEndianness ||
  95            M.getPointerSize() != Module::AnyPointerSize)
  96     return 0;                                    // Match for some other target
  97
  98   return getJITMatchQuality()/2;
  99 }
 100
 101
 102 PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS,
 103                                    bool is64Bit)
 104   : Subtarget(*this, M, FS, is64Bit),
 105     DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
 106     FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
 107     InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
 108
 109   if (getRelocationModel() == Reloc::Default) {
 110     if (Subtarget.isDarwin())
 111       setRelocationModel(Reloc::DynamicNoPIC);
 112     else
 113       setRelocationModel(Reloc::Static);
 114   }
 115 }
 116
 117 /// Override this for PowerPC.  Tail merging happily breaks up instruction issue
 118 /// groups, which typically degrades performance.
 119 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
 120
 121 PPC32TargetMachine::PPC32TargetMachine(const Module &M, const std::string &FS)
 122   : PPCTargetMachine(M, FS, false) {
 123 }
 124
 125
 126 PPC64TargetMachine::PPC64TargetMachine(const Module &M, const std::string &FS)
 127   : PPCTargetMachine(M, FS, true) {
 128 }
 129
 130
 131 //===----------------------------------------------------------------------===//
 132 // Pass Pipeline Configuration
 133 //===----------------------------------------------------------------------===//
 134
 135 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
 136                                        CodeGenOpt::Level OptLevel) {
 137   // Install an instruction selector.
 138   PM.add(createPPCISelDag(*this));
 139   return false;
 140 }
 141
 142 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
 143                                       CodeGenOpt::Level OptLevel) {
 144   // Must run branch selection immediately preceding the asm printer.
 145   PM.add(createPPCBranchSelectionPass());
 146   return false;
 147 }
 148
 149 bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
 150                                           CodeGenOpt::Level OptLevel,
 151                                           bool Verbose,
 152                                           formatted_raw_ostream &Out) {
 153   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
 154   if (AsmPrinterCtor)
 155     PM.add(AsmPrinterCtor(Out, *this, Verbose));
 156
 157   return false;
 158 }
 159
 160 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
 161                                       CodeGenOpt::Level OptLevel,
 162                                       bool DumpAsm, MachineCodeEmitter &MCE) {
 163   // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
 164   // FIXME: This should be moved to TargetJITInfo!!
 165   if (Subtarget.isPPC64()) {
 166     // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
 167     // instructions to materialize arbitrary global variable + function +
 168     // constant pool addresses.
 169     setRelocationModel(Reloc::PIC_);
 170     // Temporary workaround for the inability of PPC64 JIT to handle jump
 171     // tables.
 172     DisableJumpTables = true;
 173   } else {
 174     setRelocationModel(Reloc::Static);
 175   }
 176
 177   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
 178   // writing?
 179   Subtarget.SetJITMode();
 180
 181   // Machine code emitter pass for PowerPC.
 182   PM.add(createPPCCodeEmitterPass(*this, MCE));
 183   if (DumpAsm)
 184     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 185
 186   return false;
 187 }
 188
 189 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
 190                                       CodeGenOpt::Level OptLevel,
 191                                       bool DumpAsm, JITCodeEmitter &JCE) {
 192   // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
 193   // FIXME: This should be moved to TargetJITInfo!!
 194   if (Subtarget.isPPC64()) {
 195     // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
 196     // instructions to materialize arbitrary global variable + function +
 197     // constant pool addresses.
 198     setRelocationModel(Reloc::PIC_);
 199     // Temporary workaround for the inability of PPC64 JIT to handle jump
 200     // tables.
 201     DisableJumpTables = true;
 202   } else {
 203     setRelocationModel(Reloc::Static);
 204   }
 205
 206   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
 207   // writing?
 208   Subtarget.SetJITMode();
 209
 210   // Machine code emitter pass for PowerPC.
 211   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
 212   if (DumpAsm)
 213     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 214
 215   return false;
 216 }
 217
 218 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
 219                                       CodeGenOpt::Level OptLevel,
 220                                       bool DumpAsm, ObjectCodeEmitter &OCE) {
 221   // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
 222   // FIXME: This should be moved to TargetJITInfo!!
 223   if (Subtarget.isPPC64()) {
 224     // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
 225     // instructions to materialize arbitrary global variable + function +
 226     // constant pool addresses.
 227     setRelocationModel(Reloc::PIC_);
 228     // Temporary workaround for the inability of PPC64 JIT to handle jump
 229     // tables.
 230     DisableJumpTables = true;
 231   } else {
 232     setRelocationModel(Reloc::Static);
 233   }
 234
 235   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
 236   // writing?
 237   Subtarget.SetJITMode();
 238
 239   // Machine code emitter pass for PowerPC.
 240   PM.add(createPPCObjectCodeEmitterPass(*this, OCE));
 241   if (DumpAsm)
 242     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 243
 244   return false;
 245 }
 246
 247 bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
 248                                             CodeGenOpt::Level OptLevel,
 249                                             bool DumpAsm,
 250                                             MachineCodeEmitter &MCE) {
 251   // Machine code emitter pass for PowerPC.
 252   PM.add(createPPCCodeEmitterPass(*this, MCE));
 253   if (DumpAsm)
 254     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 255
 256   return false;
 257 }
 258
 259 bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
 260                                             CodeGenOpt::Level OptLevel,
 261                                             bool DumpAsm,
 262                                             JITCodeEmitter &JCE) {
 263   // Machine code emitter pass for PowerPC.
 264   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
 265   if (DumpAsm)
 266     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 267
 268   return false;
 269 }
 270
 271 bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
 272                                             CodeGenOpt::Level OptLevel,
 273                                             bool DumpAsm,
 274                                             ObjectCodeEmitter &OCE) {
 275   // Machine code emitter pass for PowerPC.
 276   PM.add(createPPCObjectCodeEmitterPass(*this, OCE));
 277   if (DumpAsm)
 278     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 279
 280   return false;
 281 }
 282
 283