lib/Target/Alpha/AlphaISelDAGToDAG.cpp

   1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a pattern matching instruction selector for Alpha,
  11 // converting from a legalized dag to a Alpha dag.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "Alpha.h"
  16 #include "AlphaTargetMachine.h"
  17 #include "AlphaISelLowering.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineRegisterInfo.h"
  22 #include "llvm/CodeGen/SelectionDAG.h"
  23 #include "llvm/CodeGen/SelectionDAGISel.h"
  24 #include "llvm/Target/TargetOptions.h"
  25 #include "llvm/Constants.h"
  26 #include "llvm/DerivedTypes.h"
  27 #include "llvm/GlobalValue.h"
  28 #include "llvm/Intrinsics.h"
  29 #include "llvm/LLVMContext.h"
  30 #include "llvm/Support/Compiler.h"
  31 #include "llvm/Support/Debug.h"
  32 #include "llvm/Support/ErrorHandling.h"
  33 #include "llvm/Support/MathExtras.h"
  34 #include "llvm/Support/raw_ostream.h"
  35 #include <algorithm>
  36 using namespace llvm;
  37
  38 namespace {
  39
  40   //===--------------------------------------------------------------------===//
  41   /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
  42   /// instructions for SelectionDAG operations.
  43   class AlphaDAGToDAGISel : public SelectionDAGISel {
  44     static const int64_t IMM_LOW  = -32768;
  45     static const int64_t IMM_HIGH = 32767;
  46     static const int64_t IMM_MULT = 65536;
  47     static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
  48     static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW  * IMM_MULT;
  49
  50     static int64_t get_ldah16(int64_t x) {
  51       int64_t y = x / IMM_MULT;
  52       if (x % IMM_MULT > IMM_HIGH)
  53         ++y;
  54       return y;
  55     }
  56
  57     static int64_t get_lda16(int64_t x) {
  58       return x - get_ldah16(x) * IMM_MULT;
  59     }
  60
  61     /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
  62     /// instruction (if not, return 0).  Note that this code accepts partial
  63     /// zap masks.  For example (and LHS, 1) is a valid zap, as long we know
  64     /// that the bits 1-7 of LHS are already zero.  If LHS is non-null, we are
  65     /// in checking mode.  If LHS is null, we assume that the mask has already
  66     /// been validated before.
  67     uint64_t get_zapImm(SDValue LHS, uint64_t Constant) {
  68       uint64_t BitsToCheck = 0;
  69       unsigned Result = 0;
  70       for (unsigned i = 0; i != 8; ++i) {
  71         if (((Constant >> 8*i) & 0xFF) == 0) {
  72           // nothing to do.
  73         } else {
  74           Result |= 1 << i;
  75           if (((Constant >> 8*i) & 0xFF) == 0xFF) {
  76             // If the entire byte is set, zapnot the byte.
  77           } else if (LHS.getNode() == 0) {
  78             // Otherwise, if the mask was previously validated, we know its okay
  79             // to zapnot this entire byte even though all the bits aren't set.
  80           } else {
  81             // Otherwise we don't know that the it's okay to zapnot this entire
  82             // byte.  Only do this iff we can prove that the missing bits are
  83             // already null, so the bytezap doesn't need to really null them.
  84             BitsToCheck |= ~Constant & (0xFF << 8*i);
  85           }
  86         }
  87       }
  88
  89       // If there are missing bits in a byte (for example, X & 0xEF00), check to
  90       // see if the missing bits (0x1000) are already known zero if not, the zap
  91       // isn't okay to do, as it won't clear all the required bits.
  92       if (BitsToCheck &&
  93           !CurDAG->MaskedValueIsZero(LHS,
  94                                      APInt(LHS.getValueSizeInBits(),
  95                                            BitsToCheck)))
  96         return 0;
  97
  98       return Result;
  99     }
 100
 101     static uint64_t get_zapImm(uint64_t x) {
 102       unsigned build = 0;
 103       for(int i = 0; i != 8; ++i) {
 104         if ((x & 0x00FF) == 0x00FF)
 105           build |= 1 << i;
 106         else if ((x & 0x00FF) != 0)
 107           return 0;
 108         x >>= 8;
 109       }
 110       return build;
 111     }
 112
 113
 114     static uint64_t getNearPower2(uint64_t x) {
 115       if (!x) return 0;
 116       unsigned at = CountLeadingZeros_64(x);
 117       uint64_t complow = 1 << (63 - at);
 118       uint64_t comphigh = 1 << (64 - at);
 119       //cerr << x << ":" << complow << ":" << comphigh << "\n";
 120       if (abs(complow - x) <= abs(comphigh - x))
 121         return complow;
 122       else
 123         return comphigh;
 124     }
 125
 126     static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
 127       uint64_t y = getNearPower2(x);
 128       if (swap)
 129         return (y - x) == r;
 130       else
 131         return (x - y) == r;
 132     }
 133
 134     static bool isFPZ(SDValue N) {
 135       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
 136       return (CN && (CN->getValueAPF().isZero()));
 137     }
 138     static bool isFPZn(SDValue N) {
 139       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
 140       return (CN && CN->getValueAPF().isNegZero());
 141     }
 142     static bool isFPZp(SDValue N) {
 143       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
 144       return (CN && CN->getValueAPF().isPosZero());
 145     }
 146
 147   public:
 148     explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
 149       : SelectionDAGISel(TM)
 150     {}
 151
 152     /// getI64Imm - Return a target constant with the specified value, of type
 153     /// i64.
 154     inline SDValue getI64Imm(int64_t Imm) {
 155       return CurDAG->getTargetConstant(Imm, MVT::i64);
 156     }
 157
 158     // Select - Convert the specified operand from a target-independent to a
 159     // target-specific node if it hasn't already been changed.
 160     SDNode *Select(SDValue Op);
 161
 162     /// InstructionSelect - This callback is invoked by
 163     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
 164     virtual void InstructionSelect();
 165
 166     virtual const char *getPassName() const {
 167       return "Alpha DAG->DAG Pattern Instruction Selection";
 168     }
 169
 170     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
 171     /// inline asm expressions.
 172     virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
 173                                               char ConstraintCode,
 174                                               std::vector<SDValue> &OutOps) {
 175       SDValue Op0;
 176       switch (ConstraintCode) {
 177       default: return true;
 178       case 'm':   // memory
 179         Op0 = Op;
 180         break;
 181       }
 182
 183       OutOps.push_back(Op0);
 184       return false;
 185     }
 186
 187 // Include the pieces autogenerated from the target description.
 188 #include "AlphaGenDAGISel.inc"
 189
 190 private:
 191     /// getTargetMachine - Return a reference to the TargetMachine, casted
 192     /// to the target-specific type.
 193     const AlphaTargetMachine &getTargetMachine() {
 194       return static_cast<const AlphaTargetMachine &>(TM);
 195     }
 196
 197     /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
 198     /// to the target-specific type.
 199     const AlphaInstrInfo *getInstrInfo() {
 200       return getTargetMachine().getInstrInfo();
 201     }
 202
 203     SDNode *getGlobalBaseReg();
 204     SDNode *getGlobalRetAddr();
 205     void SelectCALL(SDValue Op);
 206
 207   };
 208 }
 209
 210 /// getGlobalBaseReg - Output the instructions required to put the
 211 /// GOT address into a register.
 212 ///
 213 SDNode *AlphaDAGToDAGISel::getGlobalBaseReg() {
 214   MachineFunction *MF = BB->getParent();
 215   unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
 216   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
 217 }
 218
 219 /// getGlobalRetAddr - Grab the return address.
 220 ///
 221 SDNode *AlphaDAGToDAGISel::getGlobalRetAddr() {
 222   MachineFunction *MF = BB->getParent();
 223   unsigned GlobalRetAddr = getInstrInfo()->getGlobalRetAddr(MF);
 224   return CurDAG->getRegister(GlobalRetAddr, TLI.getPointerTy()).getNode();
 225 }
 226
 227 /// InstructionSelect - This callback is invoked by
 228 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
 229 void AlphaDAGToDAGISel::InstructionSelect() {
 230   DEBUG(BB->dump());
 231
 232   // Select target instructions for the DAG.
 233   SelectRoot(*CurDAG);
 234   CurDAG->RemoveDeadNodes();
 235 }
 236
 237 // Select - Convert the specified operand from a target-independent to a
 238 // target-specific node if it hasn't already been changed.
 239 SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
 240   SDNode *N = Op.getNode();
 241   if (N->isMachineOpcode()) {
 242     return NULL;   // Already selected.
 243   }
 244   DebugLoc dl = N->getDebugLoc();
 245
 246   switch (N->getOpcode()) {
 247   default: break;
 248   case AlphaISD::CALL:
 249     SelectCALL(Op);
 250     return NULL;
 251
 252   case ISD::FrameIndex: {
 253     int FI = cast<FrameIndexSDNode>(N)->getIndex();
 254     return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
 255                                 CurDAG->getTargetFrameIndex(FI, MVT::i32),
 256                                 getI64Imm(0));
 257   }
 258   case ISD::GLOBAL_OFFSET_TABLE:
 259     return getGlobalBaseReg();
 260   case AlphaISD::GlobalRetAddr:
 261     return getGlobalRetAddr();
 262
 263   case AlphaISD::DivCall: {
 264     SDValue Chain = CurDAG->getEntryNode();
 265     SDValue N0 = Op.getOperand(0);
 266     SDValue N1 = Op.getOperand(1);
 267     SDValue N2 = Op.getOperand(2);
 268     Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1,
 269                                  SDValue(0,0));
 270     Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2,
 271                                  Chain.getValue(1));
 272     Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0,
 273                                  Chain.getValue(1));
 274     SDNode *CNode =
 275       CurDAG->getTargetNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag,
 276                             Chain, Chain.getValue(1));
 277     Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64,
 278                                    SDValue(CNode, 1));
 279     return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
 280   }
 281
 282   case ISD::READCYCLECOUNTER: {
 283     SDValue Chain = N->getOperand(0);
 284     return CurDAG->getTargetNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
 285                                  Chain);
 286   }
 287
 288   case ISD::Constant: {
 289     uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
 290
 291     if (uval == 0) {
 292       SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
 293                                                 Alpha::R31, MVT::i64);
 294       ReplaceUses(Op, Result);
 295       return NULL;
 296     }
 297
 298     int64_t val = (int64_t)uval;
 299     int32_t val32 = (int32_t)val;
 300     if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
 301         val >= IMM_LOW  + IMM_LOW  * IMM_MULT)
 302       break; //(LDAH (LDA))
 303     if ((uval >> 32) == 0 && //empty upper bits
 304         val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
 305       // val32 >= IMM_LOW  + IMM_LOW  * IMM_MULT) //always true
 306       break; //(zext (LDAH (LDA)))
 307     //Else use the constant pool
 308     ConstantInt *C = CurDAG->getContext()->getConstantInt(Type::Int64Ty, uval);
 309     SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
 310     SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI,
 311                                         SDValue(getGlobalBaseReg(), 0));
 312     return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
 313                                 CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
 314   }
 315   case ISD::TargetConstantFP:
 316   case ISD::ConstantFP: {
 317     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
 318     bool isDouble = N->getValueType(0) == MVT::f64;
 319     MVT T = isDouble ? MVT::f64 : MVT::f32;
 320     if (CN->getValueAPF().isPosZero()) {
 321       return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
 322                                   T, CurDAG->getRegister(Alpha::F31, T),
 323                                   CurDAG->getRegister(Alpha::F31, T));
 324     } else if (CN->getValueAPF().isNegZero()) {
 325       return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
 326                                   T, CurDAG->getRegister(Alpha::F31, T),
 327                                   CurDAG->getRegister(Alpha::F31, T));
 328     } else {
 329       llvm_report_error("Unhandled FP constant type");
 330     }
 331     break;
 332   }
 333
 334   case ISD::SETCC:
 335     if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
 336       ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
 337
 338       unsigned Opc = Alpha::WTF;
 339       bool rev = false;
 340       bool inv = false;
 341       switch(CC) {
 342       default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!");
 343       case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
 344         Opc = Alpha::CMPTEQ; break;
 345       case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
 346         Opc = Alpha::CMPTLT; break;
 347       case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
 348         Opc = Alpha::CMPTLE; break;
 349       case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
 350         Opc = Alpha::CMPTLT; rev = true; break;
 351       case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
 352         Opc = Alpha::CMPTLE; rev = true; break;
 353       case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
 354         Opc = Alpha::CMPTEQ; inv = true; break;
 355       case ISD::SETO:
 356         Opc = Alpha::CMPTUN; inv = true; break;
 357       case ISD::SETUO:
 358         Opc = Alpha::CMPTUN; break;
 359       };
 360       SDValue tmp1 = N->getOperand(rev?1:0);
 361       SDValue tmp2 = N->getOperand(rev?0:1);
 362       SDNode *cmp = CurDAG->getTargetNode(Opc, dl, MVT::f64, tmp1, tmp2);
 363       if (inv)
 364         cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, dl,
 365                                     MVT::f64, SDValue(cmp, 0),
 366                                     CurDAG->getRegister(Alpha::F31, MVT::f64));
 367       switch(CC) {
 368       case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
 369       case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
 370        {
 371          SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, MVT::f64,
 372                                               tmp1, tmp2);
 373          cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, MVT::f64,
 374                                      SDValue(cmp2, 0), SDValue(cmp, 0));
 375          break;
 376        }
 377       default: break;
 378       }
 379
 380       SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, dl,
 381                                          MVT::i64, SDValue(cmp, 0));
 382       return CurDAG->getTargetNode(Alpha::CMPULT, dl, MVT::i64,
 383                                    CurDAG->getRegister(Alpha::R31, MVT::i64),
 384                                    SDValue(LD,0));
 385     }
 386     break;
 387
 388   case ISD::SELECT:
 389     if (N->getValueType(0).isFloatingPoint() &&
 390         (N->getOperand(0).getOpcode() != ISD::SETCC ||
 391          !N->getOperand(0).getOperand(1).getValueType().isFloatingPoint())) {
 392       //This should be the condition not covered by the Patterns
 393       //FIXME: Don't have SelectCode die, but rather return something testable
 394       // so that things like this can be caught in fall though code
 395       //move int to fp
 396       bool isDouble = N->getValueType(0) == MVT::f64;
 397       SDValue cond = N->getOperand(0);
 398       SDValue TV = N->getOperand(1);
 399       SDValue FV = N->getOperand(2);
 400
 401       SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, dl, MVT::f64, cond);
 402       return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
 403                                    dl, MVT::f64, FV, TV, SDValue(LD,0));
 404     }
 405     break;
 406
 407   case ISD::AND: {
 408     ConstantSDNode* SC = NULL;
 409     ConstantSDNode* MC = NULL;
 410     if (N->getOperand(0).getOpcode() == ISD::SRL &&
 411         (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
 412         (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
 413       uint64_t sval = SC->getZExtValue();
 414       uint64_t mval = MC->getZExtValue();
 415       // If the result is a zap, let the autogened stuff handle it.
 416       if (get_zapImm(N->getOperand(0), mval))
 417         break;
 418       // given mask X, and shift S, we want to see if there is any zap in the
 419       // mask if we play around with the botton S bits
 420       uint64_t dontcare = (~0ULL) >> (64 - sval);
 421       uint64_t mask = mval << sval;
 422
 423       if (get_zapImm(mask | dontcare))
 424         mask = mask | dontcare;
 425
 426       if (get_zapImm(mask)) {
 427         SDValue Z =
 428           SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, MVT::i64,
 429                                           N->getOperand(0).getOperand(0),
 430                                           getI64Imm(get_zapImm(mask))), 0);
 431         return CurDAG->getTargetNode(Alpha::SRLr, dl, MVT::i64, Z,
 432                                      getI64Imm(sval));
 433       }
 434     }
 435     break;
 436   }
 437
 438   }
 439
 440   return SelectCode(Op);
 441 }
 442
 443 void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
 444   //TODO: add flag stuff to prevent nondeturministic breakage!
 445
 446   SDNode *N = Op.getNode();
 447   SDValue Chain = N->getOperand(0);
 448   SDValue Addr = N->getOperand(1);
 449   SDValue InFlag(0,0);  // Null incoming flag value.
 450   DebugLoc dl = N->getDebugLoc();
 451
 452    std::vector<SDValue> CallOperands;
 453    std::vector<MVT> TypeOperands;
 454
 455    //grab the arguments
 456    for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
 457      TypeOperands.push_back(N->getOperand(i).getValueType());
 458      CallOperands.push_back(N->getOperand(i));
 459    }
 460    int count = N->getNumOperands() - 2;
 461
 462    static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
 463                                        Alpha::R19, Alpha::R20, Alpha::R21};
 464    static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
 465                                          Alpha::F19, Alpha::F20, Alpha::F21};
 466
 467    for (int i = 6; i < count; ++i) {
 468      unsigned Opc = Alpha::WTF;
 469      if (TypeOperands[i].isInteger()) {
 470        Opc = Alpha::STQ;
 471      } else if (TypeOperands[i] == MVT::f32) {
 472        Opc = Alpha::STS;
 473      } else if (TypeOperands[i] == MVT::f64) {
 474        Opc = Alpha::STT;
 475      } else
 476        llvm_unreachable("Unknown operand");
 477
 478      SDValue Ops[] = { CallOperands[i],  getI64Imm((i - 6) * 8),
 479                        CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64),
 480                        Chain };
 481      Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 4), 0);
 482    }
 483    for (int i = 0; i < std::min(6, count); ++i) {
 484      if (TypeOperands[i].isInteger()) {
 485        Chain = CurDAG->getCopyToReg(Chain, dl, args_int[i],
 486                                     CallOperands[i], InFlag);
 487        InFlag = Chain.getValue(1);
 488      } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
 489        Chain = CurDAG->getCopyToReg(Chain, dl, args_float[i],
 490                                     CallOperands[i], InFlag);
 491        InFlag = Chain.getValue(1);
 492      } else
 493        llvm_unreachable("Unknown operand");
 494    }
 495
 496    // Finally, once everything is in registers to pass to the call, emit the
 497    // call itself.
 498    if (Addr.getOpcode() == AlphaISD::GPRelLo) {
 499      SDValue GOT = SDValue(getGlobalBaseReg(), 0);
 500      Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
 501      InFlag = Chain.getValue(1);
 502      Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other,
 503                                            MVT::Flag, Addr.getOperand(0),
 504                                            Chain, InFlag), 0);
 505    } else {
 506      Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
 507      InFlag = Chain.getValue(1);
 508      Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, MVT::Other,
 509                                              MVT::Flag, Chain, InFlag), 0);
 510    }
 511    InFlag = Chain.getValue(1);
 512
 513    std::vector<SDValue> CallResults;
 514
 515    switch (N->getValueType(0).getSimpleVT()) {
 516    default: llvm_unreachable("Unexpected ret value!");
 517      case MVT::Other: break;
 518    case MVT::i64:
 519      Chain = CurDAG->getCopyFromReg(Chain, dl,
 520                                     Alpha::R0, MVT::i64, InFlag).getValue(1);
 521      CallResults.push_back(Chain.getValue(0));
 522      break;
 523    case MVT::f32:
 524      Chain = CurDAG->getCopyFromReg(Chain, dl,
 525                                     Alpha::F0, MVT::f32, InFlag).getValue(1);
 526      CallResults.push_back(Chain.getValue(0));
 527      break;
 528    case MVT::f64:
 529      Chain = CurDAG->getCopyFromReg(Chain, dl,
 530                                     Alpha::F0, MVT::f64, InFlag).getValue(1);
 531      CallResults.push_back(Chain.getValue(0));
 532      break;
 533    }
 534
 535    CallResults.push_back(Chain);
 536    for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
 537      ReplaceUses(Op.getValue(i), CallResults[i]);
 538 }
 539
 540
 541 /// createAlphaISelDag - This pass converts a legalized DAG into a
 542 /// Alpha-specific DAG, ready for instruction scheduling.
 543 ///
 544 FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
 545   return new AlphaDAGToDAGISel(TM);
 546 }