lib/Target/Alpha/AlphaInstrInfo.cpp

   1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Alpha implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Alpha.h"
  15 #include "AlphaInstrInfo.h"
  16 #include "AlphaMachineFunctionInfo.h"
  17 #include "AlphaGenInstrInfo.inc"
  18 #include "llvm/CodeGen/MachineRegisterInfo.h"
  19 #include "llvm/ADT/STLExtras.h"
  20 #include "llvm/ADT/SmallVector.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/Support/ErrorHandling.h"
  23 using namespace llvm;
  24
  25 AlphaInstrInfo::AlphaInstrInfo()
  26   : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
  27     RI(*this) { }
  28
  29
  30 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
  31                                  unsigned& sourceReg, unsigned& destReg,
  32                                  unsigned& SrcSR, unsigned& DstSR) const {
  33   unsigned oc = MI.getOpcode();
  34   if (oc == Alpha::BISr   ||
  35       oc == Alpha::CPYSS  ||
  36       oc == Alpha::CPYST  ||
  37       oc == Alpha::CPYSSt ||
  38       oc == Alpha::CPYSTs) {
  39     // or r1, r2, r2
  40     // cpys(s|t) r1 r2 r2
  41     assert(MI.getNumOperands() >= 3 &&
  42            MI.getOperand(0).isReg() &&
  43            MI.getOperand(1).isReg() &&
  44            MI.getOperand(2).isReg() &&
  45            "invalid Alpha BIS instruction!");
  46     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
  47       sourceReg = MI.getOperand(1).getReg();
  48       destReg = MI.getOperand(0).getReg();
  49       SrcSR = DstSR = 0;
  50       return true;
  51     }
  52   }
  53   return false;
  54 }
  55
  56 unsigned
  57 AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
  58                                     int &FrameIndex) const {
  59   switch (MI->getOpcode()) {
  60   case Alpha::LDL:
  61   case Alpha::LDQ:
  62   case Alpha::LDBU:
  63   case Alpha::LDWU:
  64   case Alpha::LDS:
  65   case Alpha::LDT:
  66     if (MI->getOperand(1).isFI()) {
  67       FrameIndex = MI->getOperand(1).getIndex();
  68       return MI->getOperand(0).getReg();
  69     }
  70     break;
  71   }
  72   return 0;
  73 }
  74
  75 unsigned
  76 AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
  77                                    int &FrameIndex) const {
  78   switch (MI->getOpcode()) {
  79   case Alpha::STL:
  80   case Alpha::STQ:
  81   case Alpha::STB:
  82   case Alpha::STW:
  83   case Alpha::STS:
  84   case Alpha::STT:
  85     if (MI->getOperand(1).isFI()) {
  86       FrameIndex = MI->getOperand(1).getIndex();
  87       return MI->getOperand(0).getReg();
  88     }
  89     break;
  90   }
  91   return 0;
  92 }
  93
  94 static bool isAlphaIntCondCode(unsigned Opcode) {
  95   switch (Opcode) {
  96   case Alpha::BEQ:
  97   case Alpha::BNE:
  98   case Alpha::BGE:
  99   case Alpha::BGT:
 100   case Alpha::BLE:
 101   case Alpha::BLT:
 102   case Alpha::BLBC:
 103   case Alpha::BLBS:
 104     return true;
 105   default:
 106     return false;
 107   }
 108 }
 109
 110 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
 111                                       MachineBasicBlock *TBB,
 112                                       MachineBasicBlock *FBB,
 113                             const SmallVectorImpl<MachineOperand> &Cond) const {
 114   // FIXME this should probably have a DebugLoc argument
 115   DebugLoc dl = DebugLoc::getUnknownLoc();
 116   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 117   assert((Cond.size() == 2 || Cond.size() == 0) &&
 118          "Alpha branch conditions have two components!");
 119
 120   // One-way branch.
 121   if (FBB == 0) {
 122     if (Cond.empty())   // Unconditional branch
 123       BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB);
 124     else                // Conditional branch
 125       if (isAlphaIntCondCode(Cond[0].getImm()))
 126         BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
 127           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 128       else
 129         BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
 130           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 131     return 1;
 132   }
 133
 134   // Two-way Conditional Branch.
 135   if (isAlphaIntCondCode(Cond[0].getImm()))
 136     BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
 137       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 138   else
 139     BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
 140       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 141   BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB);
 142   return 2;
 143 }
 144
 145 bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
 146                                   MachineBasicBlock::iterator MI,
 147                                   unsigned DestReg, unsigned SrcReg,
 148                                   const TargetRegisterClass *DestRC,
 149                                   const TargetRegisterClass *SrcRC) const {
 150   //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
 151   if (DestRC != SrcRC) {
 152     // Not yet supported!
 153     return false;
 154   }
 155
 156   DebugLoc DL = DebugLoc::getUnknownLoc();
 157   if (MI != MBB.end()) DL = MI->getDebugLoc();
 158
 159   if (DestRC == Alpha::GPRCRegisterClass) {
 160     BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
 161       .addReg(SrcReg)
 162       .addReg(SrcReg);
 163   } else if (DestRC == Alpha::F4RCRegisterClass) {
 164     BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
 165       .addReg(SrcReg)
 166       .addReg(SrcReg);
 167   } else if (DestRC == Alpha::F8RCRegisterClass) {
 168     BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
 169       .addReg(SrcReg)
 170       .addReg(SrcReg);
 171   } else {
 172     // Attempt to copy register that is not GPR or FPR
 173     return false;
 174   }
 175
 176   return true;
 177 }
 178
 179 void
 180 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 181                                     MachineBasicBlock::iterator MI,
 182                                     unsigned SrcReg, bool isKill, int FrameIdx,
 183                                     const TargetRegisterClass *RC) const {
 184   //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
 185   //     << FrameIdx << "\n";
 186   //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
 187
 188   DebugLoc DL = DebugLoc::getUnknownLoc();
 189   if (MI != MBB.end()) DL = MI->getDebugLoc();
 190
 191   if (RC == Alpha::F4RCRegisterClass)
 192     BuildMI(MBB, MI, DL, get(Alpha::STS))
 193       .addReg(SrcReg, getKillRegState(isKill))
 194       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 195   else if (RC == Alpha::F8RCRegisterClass)
 196     BuildMI(MBB, MI, DL, get(Alpha::STT))
 197       .addReg(SrcReg, getKillRegState(isKill))
 198       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 199   else if (RC == Alpha::GPRCRegisterClass)
 200     BuildMI(MBB, MI, DL, get(Alpha::STQ))
 201       .addReg(SrcReg, getKillRegState(isKill))
 202       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 203   else
 204     llvm_unreachable("Unhandled register class");
 205 }
 206
 207 void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
 208                                        bool isKill,
 209                                        SmallVectorImpl<MachineOperand> &Addr,
 210                                        const TargetRegisterClass *RC,
 211                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
 212   unsigned Opc = 0;
 213   if (RC == Alpha::F4RCRegisterClass)
 214     Opc = Alpha::STS;
 215   else if (RC == Alpha::F8RCRegisterClass)
 216     Opc = Alpha::STT;
 217   else if (RC == Alpha::GPRCRegisterClass)
 218     Opc = Alpha::STQ;
 219   else
 220     llvm_unreachable("Unhandled register class");
 221   DebugLoc DL = DebugLoc::getUnknownLoc();
 222   MachineInstrBuilder MIB =
 223     BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
 224   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
 225     MIB.addOperand(Addr[i]);
 226   NewMIs.push_back(MIB);
 227 }
 228
 229 void
 230 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 231                                         MachineBasicBlock::iterator MI,
 232                                         unsigned DestReg, int FrameIdx,
 233                                         const TargetRegisterClass *RC) const {
 234   //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
 235   //     << FrameIdx << "\n";
 236   DebugLoc DL = DebugLoc::getUnknownLoc();
 237   if (MI != MBB.end()) DL = MI->getDebugLoc();
 238
 239   if (RC == Alpha::F4RCRegisterClass)
 240     BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg)
 241       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 242   else if (RC == Alpha::F8RCRegisterClass)
 243     BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg)
 244       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 245   else if (RC == Alpha::GPRCRegisterClass)
 246     BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
 247       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 248   else
 249     llvm_unreachable("Unhandled register class");
 250 }
 251
 252 void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 253                                         SmallVectorImpl<MachineOperand> &Addr,
 254                                         const TargetRegisterClass *RC,
 255                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
 256   unsigned Opc = 0;
 257   if (RC == Alpha::F4RCRegisterClass)
 258     Opc = Alpha::LDS;
 259   else if (RC == Alpha::F8RCRegisterClass)
 260     Opc = Alpha::LDT;
 261   else if (RC == Alpha::GPRCRegisterClass)
 262     Opc = Alpha::LDQ;
 263   else
 264     llvm_unreachable("Unhandled register class");
 265   DebugLoc DL = DebugLoc::getUnknownLoc();
 266   MachineInstrBuilder MIB =
 267     BuildMI(MF, DL, get(Opc), DestReg);
 268   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
 269     MIB.addOperand(Addr[i]);
 270   NewMIs.push_back(MIB);
 271 }
 272
 273 MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
 274                                                     MachineInstr *MI,
 275                                           const SmallVectorImpl<unsigned> &Ops,
 276                                                     int FrameIndex) const {
 277    if (Ops.size() != 1) return NULL;
 278
 279    // Make sure this is a reg-reg copy.
 280    unsigned Opc = MI->getOpcode();
 281
 282    MachineInstr *NewMI = NULL;
 283    switch(Opc) {
 284    default:
 285      break;
 286    case Alpha::BISr:
 287    case Alpha::CPYSS:
 288    case Alpha::CPYST:
 289      if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
 290        if (Ops[0] == 0) {  // move -> store
 291          unsigned InReg = MI->getOperand(1).getReg();
 292          bool isKill = MI->getOperand(1).isKill();
 293          bool isUndef = MI->getOperand(1).isUndef();
 294          Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
 295            ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
 296          NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
 297            .addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef))
 298            .addFrameIndex(FrameIndex)
 299            .addReg(Alpha::F31);
 300        } else {           // load -> move
 301          unsigned OutReg = MI->getOperand(0).getReg();
 302          bool isDead = MI->getOperand(0).isDead();
 303          bool isUndef = MI->getOperand(0).isUndef();
 304          Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
 305            ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
 306          NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
 307            .addReg(OutReg, RegState::Define | getDeadRegState(isDead) |
 308                    getUndefRegState(isUndef))
 309            .addFrameIndex(FrameIndex)
 310            .addReg(Alpha::F31);
 311        }
 312      }
 313      break;
 314    }
 315   return NewMI;
 316 }
 317
 318 static unsigned AlphaRevCondCode(unsigned Opcode) {
 319   switch (Opcode) {
 320   case Alpha::BEQ: return Alpha::BNE;
 321   case Alpha::BNE: return Alpha::BEQ;
 322   case Alpha::BGE: return Alpha::BLT;
 323   case Alpha::BGT: return Alpha::BLE;
 324   case Alpha::BLE: return Alpha::BGT;
 325   case Alpha::BLT: return Alpha::BGE;
 326   case Alpha::BLBC: return Alpha::BLBS;
 327   case Alpha::BLBS: return Alpha::BLBC;
 328   case Alpha::FBEQ: return Alpha::FBNE;
 329   case Alpha::FBNE: return Alpha::FBEQ;
 330   case Alpha::FBGE: return Alpha::FBLT;
 331   case Alpha::FBGT: return Alpha::FBLE;
 332   case Alpha::FBLE: return Alpha::FBGT;
 333   case Alpha::FBLT: return Alpha::FBGE;
 334   default:
 335     llvm_unreachable("Unknown opcode");
 336   }
 337   return 0; // Not reached
 338 }
 339
 340 // Branch analysis.
 341 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
 342                                    MachineBasicBlock *&FBB,
 343                                    SmallVectorImpl<MachineOperand> &Cond,
 344                                    bool AllowModify) const {
 345   // If the block has no terminators, it just falls into the block after it.
 346   MachineBasicBlock::iterator I = MBB.end();
 347   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
 348     return false;
 349
 350   // Get the last instruction in the block.
 351   MachineInstr *LastInst = I;
 352
 353   // If there is only one terminator instruction, process it.
 354   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 355     if (LastInst->getOpcode() == Alpha::BR) {
 356       TBB = LastInst->getOperand(0).getMBB();
 357       return false;
 358     } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
 359                LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
 360       // Block ends with fall-through condbranch.
 361       TBB = LastInst->getOperand(2).getMBB();
 362       Cond.push_back(LastInst->getOperand(0));
 363       Cond.push_back(LastInst->getOperand(1));
 364       return false;
 365     }
 366     // Otherwise, don't know what this is.
 367     return true;
 368   }
 369
 370   // Get the instruction before it if it's a terminator.
 371   MachineInstr *SecondLastInst = I;
 372
 373   // If there are three terminators, we don't know what sort of block this is.
 374   if (SecondLastInst && I != MBB.begin() &&
 375       isUnpredicatedTerminator(--I))
 376     return true;
 377
 378   // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
 379   if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
 380       SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
 381       LastInst->getOpcode() == Alpha::BR) {
 382     TBB =  SecondLastInst->getOperand(2).getMBB();
 383     Cond.push_back(SecondLastInst->getOperand(0));
 384     Cond.push_back(SecondLastInst->getOperand(1));
 385     FBB = LastInst->getOperand(0).getMBB();
 386     return false;
 387   }
 388
 389   // If the block ends with two Alpha::BRs, handle it.  The second one is not
 390   // executed, so remove it.
 391   if (SecondLastInst->getOpcode() == Alpha::BR &&
 392       LastInst->getOpcode() == Alpha::BR) {
 393     TBB = SecondLastInst->getOperand(0).getMBB();
 394     I = LastInst;
 395     if (AllowModify)
 396       I->eraseFromParent();
 397     return false;
 398   }
 399
 400   // Otherwise, can't handle this.
 401   return true;
 402 }
 403
 404 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 405   MachineBasicBlock::iterator I = MBB.end();
 406   if (I == MBB.begin()) return 0;
 407   --I;
 408   if (I->getOpcode() != Alpha::BR &&
 409       I->getOpcode() != Alpha::COND_BRANCH_I &&
 410       I->getOpcode() != Alpha::COND_BRANCH_F)
 411     return 0;
 412
 413   // Remove the branch.
 414   I->eraseFromParent();
 415
 416   I = MBB.end();
 417
 418   if (I == MBB.begin()) return 1;
 419   --I;
 420   if (I->getOpcode() != Alpha::COND_BRANCH_I &&
 421       I->getOpcode() != Alpha::COND_BRANCH_F)
 422     return 1;
 423
 424   // Remove the branch.
 425   I->eraseFromParent();
 426   return 2;
 427 }
 428
 429 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
 430                                 MachineBasicBlock::iterator MI) const {
 431   DebugLoc DL = DebugLoc::getUnknownLoc();
 432   if (MI != MBB.end()) DL = MI->getDebugLoc();
 433   BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
 434     .addReg(Alpha::R31)
 435     .addReg(Alpha::R31);
 436 }
 437
 438 bool AlphaInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
 439   if (MBB.empty()) return false;
 440
 441   switch (MBB.back().getOpcode()) {
 442   case Alpha::RETDAG: // Return.
 443   case Alpha::RETDAGp:
 444   case Alpha::BR:     // Uncond branch.
 445   case Alpha::JMP:  // Indirect branch.
 446     return true;
 447   default: return false;
 448   }
 449 }
 450 bool AlphaInstrInfo::
 451 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
 452   assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
 453   Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));
 454   return false;
 455 }
 456
 457 /// getGlobalBaseReg - Return a virtual register initialized with the
 458 /// the global base register value. Output instructions required to
 459 /// initialize the register in the function entry block, if necessary.
 460 ///
 461 unsigned AlphaInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
 462   AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
 463   unsigned GlobalBaseReg = AlphaFI->getGlobalBaseReg();
 464   if (GlobalBaseReg != 0)
 465     return GlobalBaseReg;
 466
 467   // Insert the set of GlobalBaseReg into the first MBB of the function
 468   MachineBasicBlock &FirstMBB = MF->front();
 469   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
 470   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 471   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 472
 473   GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
 474   bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Alpha::R29,
 475                               &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
 476   assert(Ok && "Couldn't assign to global base register!");
 477   Ok = Ok; // Silence warning when assertions are turned off.
 478   RegInfo.addLiveIn(Alpha::R29);
 479
 480   AlphaFI->setGlobalBaseReg(GlobalBaseReg);
 481   return GlobalBaseReg;
 482 }
 483
 484 /// getGlobalRetAddr - Return a virtual register initialized with the
 485 /// the global base register value. Output instructions required to
 486 /// initialize the register in the function entry block, if necessary.
 487 ///
 488 unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const {
 489   AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
 490   unsigned GlobalRetAddr = AlphaFI->getGlobalRetAddr();
 491   if (GlobalRetAddr != 0)
 492     return GlobalRetAddr;
 493
 494   // Insert the set of GlobalRetAddr into the first MBB of the function
 495   MachineBasicBlock &FirstMBB = MF->front();
 496   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
 497   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 498   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 499
 500   GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
 501   bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalRetAddr, Alpha::R26,
 502                               &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
 503   assert(Ok && "Couldn't assign to global return address register!");
 504   Ok = Ok; // Silence warning when assertions are turned off.
 505   RegInfo.addLiveIn(Alpha::R26);
 506
 507   AlphaFI->setGlobalRetAddr(GlobalRetAddr);
 508   return GlobalRetAddr;
 509 }