Merge branch 'master' into systemz
[llvm/systemz.git] / lib / Target / Alpha / AlphaTargetMachine.cpp
blobc57d06f93c4bc6a3418fc765db5c3104a38dffcc
1 //===-- AlphaTargetMachine.cpp - Define TargetMachine for Alpha -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
11 //===----------------------------------------------------------------------===//
13 #include "Alpha.h"
14 #include "AlphaJITInfo.h"
15 #include "AlphaTargetAsmInfo.h"
16 #include "AlphaTargetMachine.h"
17 #include "llvm/Module.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Target/TargetMachineRegistry.h"
20 #include "llvm/Support/FormattedStream.h"
22 using namespace llvm;
24 // Register the targets
25 extern Target TheAlphaTarget;
26 static RegisterTarget<AlphaTargetMachine> X(TheAlphaTarget, "alpha",
27 "Alpha [experimental]");
29 // Force static initialization.
30 extern "C" void LLVMInitializeAlphaTarget() { }
32 const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
33 return new AlphaTargetAsmInfo(*this);
36 AlphaTargetMachine::AlphaTargetMachine(const Target &T, const Module &M,
37 const std::string &FS)
38 : LLVMTargetMachine(T),
39 DataLayout("e-f128:128:128"),
40 FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
41 JITInfo(*this),
42 Subtarget(M, FS),
43 TLInfo(*this) {
44 setRelocationModel(Reloc::PIC_);
48 //===----------------------------------------------------------------------===//
49 // Pass Pipeline Configuration
50 //===----------------------------------------------------------------------===//
52 bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
53 CodeGenOpt::Level OptLevel) {
54 PM.add(createAlphaISelDag(*this));
55 return false;
57 bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
58 CodeGenOpt::Level OptLevel) {
59 // Must run branch selection immediately preceding the asm printer
60 PM.add(createAlphaBranchSelectionPass());
61 PM.add(createAlphaLLRPPass(*this));
62 return false;
64 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
65 CodeGenOpt::Level OptLevel,
66 MachineCodeEmitter &MCE) {
67 PM.add(createAlphaCodeEmitterPass(*this, MCE));
68 return false;
70 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
71 CodeGenOpt::Level OptLevel,
72 JITCodeEmitter &JCE) {
73 PM.add(createAlphaJITCodeEmitterPass(*this, JCE));
74 return false;
76 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
77 CodeGenOpt::Level OptLevel,
78 ObjectCodeEmitter &OCE) {
79 PM.add(createAlphaObjectCodeEmitterPass(*this, OCE));
80 return false;
82 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
83 CodeGenOpt::Level OptLevel,
84 MachineCodeEmitter &MCE) {
85 return addCodeEmitter(PM, OptLevel, MCE);
87 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
88 CodeGenOpt::Level OptLevel,
89 JITCodeEmitter &JCE) {
90 return addCodeEmitter(PM, OptLevel, JCE);
92 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
93 CodeGenOpt::Level OptLevel,
94 ObjectCodeEmitter &OCE) {
95 return addCodeEmitter(PM, OptLevel, OCE);