lib/Target/PowerPC/PPCHazardRecognizers.cpp

   1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements hazard recognizers for scheduling on PowerPC processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "pre-RA-sched"
  15 #include "PPCHazardRecognizers.h"
  16 #include "PPC.h"
  17 #include "PPCInstrInfo.h"
  18 #include "llvm/CodeGen/ScheduleDAG.h"
  19 #include "llvm/Support/Debug.h"
  20 #include "llvm/Support/ErrorHandling.h"
  21 using namespace llvm;
  22
  23 //===----------------------------------------------------------------------===//
  24 // PowerPC 970 Hazard Recognizer
  25 //
  26 // This models the dispatch group formation of the PPC970 processor.  Dispatch
  27 // groups are bundles of up to five instructions that can contain various mixes
  28 // of instructions.  The PPC970 can dispatch a peak of 4 non-branch and one
  29 // branch instruction per-cycle.
  30 //
  31 // There are a number of restrictions to dispatch group formation: some
  32 // instructions can only be issued in the first slot of a dispatch group, & some
  33 // instructions fill an entire dispatch group.  Additionally, only branches can
  34 // issue in the 5th (last) slot.
  35 //
  36 // Finally, there are a number of "structural" hazards on the PPC970.  These
  37 // conditions cause large performance penalties due to misprediction, recovery,
  38 // and replay logic that has to happen.  These cases include setting a CTR and
  39 // branching through it in the same dispatch group, and storing to an address,
  40 // then loading from the same address within a dispatch group.  To avoid these
  41 // conditions, we insert no-op instructions when appropriate.
  42 //
  43 // FIXME: This is missing some significant cases:
  44 //   1. Modeling of microcoded instructions.
  45 //   2. Handling of serialized operations.
  46 //   3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
  47 //
  48
  49 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
  50   : TII(tii) {
  51   EndDispatchGroup();
  52 }
  53
  54 void PPCHazardRecognizer970::EndDispatchGroup() {
  55   DOUT << "=== Start of dispatch group\n";
  56   NumIssued = 0;
  57
  58   // Structural hazard info.
  59   HasCTRSet = false;
  60   NumStores = 0;
  61 }
  62
  63
  64 PPCII::PPC970_Unit
  65 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
  66                                      bool &isFirst, bool &isSingle,
  67                                      bool &isCracked,
  68                                      bool &isLoad, bool &isStore) {
  69   if ((int)Opcode >= 0) {
  70     isFirst = isSingle = isCracked = isLoad = isStore = false;
  71     return PPCII::PPC970_Pseudo;
  72   }
  73   Opcode = ~Opcode;
  74
  75   const TargetInstrDesc &TID = TII.get(Opcode);
  76
  77   isLoad  = TID.mayLoad();
  78   isStore = TID.mayStore();
  79
  80   unsigned TSFlags = TID.TSFlags;
  81
  82   isFirst   = TSFlags & PPCII::PPC970_First;
  83   isSingle  = TSFlags & PPCII::PPC970_Single;
  84   isCracked = TSFlags & PPCII::PPC970_Cracked;
  85   return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
  86 }
  87
  88 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer
  89 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
  90 bool PPCHazardRecognizer970::
  91 isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const {
  92   for (unsigned i = 0, e = NumStores; i != e; ++i) {
  93     // Handle exact and commuted addresses.
  94     if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i])
  95       return true;
  96     if (Ptr2 == StorePtr1[i] && Ptr1 == StorePtr2[i])
  97       return true;
  98
  99     // Okay, we don't have an exact match, if this is an indexed offset, see if
 100     // we have overlap (which happens during fp->int conversion for example).
 101     if (StorePtr2[i] == Ptr2) {
 102       if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1[i]))
 103         if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
 104           // Okay the base pointers match, so we have [c1+r] vs [c2+r].  Check
 105           // to see if the load and store actually overlap.
 106           int StoreOffs = StoreOffset->getZExtValue();
 107           int LoadOffs  = LoadOffset->getZExtValue();
 108           if (StoreOffs < LoadOffs) {
 109             if (int(StoreOffs+StoreSize[i]) > LoadOffs) return true;
 110           } else {
 111             if (int(LoadOffs+LoadSize) > StoreOffs) return true;
 112           }
 113         }
 114     }
 115   }
 116   return false;
 117 }
 118
 119 /// getHazardType - We return hazard for any non-branch instruction that would
 120 /// terminate terminate the dispatch group.  We turn NoopHazard for any
 121 /// instructions that wouldn't terminate the dispatch group that would cause a
 122 /// pipeline flush.
 123 ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::
 124 getHazardType(SUnit *SU) {
 125   const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
 126   bool isFirst, isSingle, isCracked, isLoad, isStore;
 127   PPCII::PPC970_Unit InstrType =
 128     GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
 129                  isLoad, isStore);
 130   if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
 131   unsigned Opcode = Node->getMachineOpcode();
 132
 133   // We can only issue a PPC970_First/PPC970_Single instruction (such as
 134   // crand/mtspr/etc) if this is the first cycle of the dispatch group.
 135   if (NumIssued != 0 && (isFirst || isSingle))
 136     return Hazard;
 137
 138   // If this instruction is cracked into two ops by the decoder, we know that
 139   // it is not a branch and that it cannot issue if 3 other instructions are
 140   // already in the dispatch group.
 141   if (isCracked && NumIssued > 2)
 142     return Hazard;
 143
 144   switch (InstrType) {
 145   default: llvm_unreachable("Unknown instruction type!");
 146   case PPCII::PPC970_FXU:
 147   case PPCII::PPC970_LSU:
 148   case PPCII::PPC970_FPU:
 149   case PPCII::PPC970_VALU:
 150   case PPCII::PPC970_VPERM:
 151     // We can only issue a branch as the last instruction in a group.
 152     if (NumIssued == 4) return Hazard;
 153     break;
 154   case PPCII::PPC970_CRU:
 155     // We can only issue a CR instruction in the first two slots.
 156     if (NumIssued >= 2) return Hazard;
 157     break;
 158   case PPCII::PPC970_BRU:
 159     break;
 160   }
 161
 162   // Do not allow MTCTR and BCTRL to be in the same dispatch group.
 163   if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
 164     return NoopHazard;
 165
 166   // If this is a load following a store, make sure it's not to the same or
 167   // overlapping address.
 168   if (isLoad && NumStores) {
 169     unsigned LoadSize;
 170     switch (Opcode) {
 171     default: llvm_unreachable("Unknown load!");
 172     case PPC::LBZ:   case PPC::LBZU:
 173     case PPC::LBZX:
 174     case PPC::LBZ8:  case PPC::LBZU8:
 175     case PPC::LBZX8:
 176     case PPC::LVEBX:
 177       LoadSize = 1;
 178       break;
 179     case PPC::LHA:   case PPC::LHAU:
 180     case PPC::LHAX:
 181     case PPC::LHZ:   case PPC::LHZU:
 182     case PPC::LHZX:
 183     case PPC::LVEHX:
 184     case PPC::LHBRX:
 185     case PPC::LHA8:   case PPC::LHAU8:
 186     case PPC::LHAX8:
 187     case PPC::LHZ8:   case PPC::LHZU8:
 188     case PPC::LHZX8:
 189       LoadSize = 2;
 190       break;
 191     case PPC::LFS:    case PPC::LFSU:
 192     case PPC::LFSX:
 193     case PPC::LWZ:    case PPC::LWZU:
 194     case PPC::LWZX:
 195     case PPC::LWA:
 196     case PPC::LWAX:
 197     case PPC::LVEWX:
 198     case PPC::LWBRX:
 199     case PPC::LWZ8:
 200     case PPC::LWZX8:
 201       LoadSize = 4;
 202       break;
 203     case PPC::LFD:    case PPC::LFDU:
 204     case PPC::LFDX:
 205     case PPC::LD:     case PPC::LDU:
 206     case PPC::LDX:
 207       LoadSize = 8;
 208       break;
 209     case PPC::LVX:
 210     case PPC::LVXL:
 211       LoadSize = 16;
 212       break;
 213     }
 214
 215     if (isLoadOfStoredAddress(LoadSize,
 216                               Node->getOperand(0), Node->getOperand(1)))
 217       return NoopHazard;
 218   }
 219
 220   return NoHazard;
 221 }
 222
 223 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
 224   const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
 225   bool isFirst, isSingle, isCracked, isLoad, isStore;
 226   PPCII::PPC970_Unit InstrType =
 227     GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
 228                  isLoad, isStore);
 229   if (InstrType == PPCII::PPC970_Pseudo) return;
 230   unsigned Opcode = Node->getMachineOpcode();
 231
 232   // Update structural hazard information.
 233   if (Opcode == PPC::MTCTR) HasCTRSet = true;
 234
 235   // Track the address stored to.
 236   if (isStore) {
 237     unsigned ThisStoreSize;
 238     switch (Opcode) {
 239     default: llvm_unreachable("Unknown store instruction!");
 240     case PPC::STB:    case PPC::STB8:
 241     case PPC::STBU:   case PPC::STBU8:
 242     case PPC::STBX:   case PPC::STBX8:
 243     case PPC::STVEBX:
 244       ThisStoreSize = 1;
 245       break;
 246     case PPC::STH:    case PPC::STH8:
 247     case PPC::STHU:   case PPC::STHU8:
 248     case PPC::STHX:   case PPC::STHX8:
 249     case PPC::STVEHX:
 250     case PPC::STHBRX:
 251       ThisStoreSize = 2;
 252       break;
 253     case PPC::STFS:
 254     case PPC::STFSU:
 255     case PPC::STFSX:
 256     case PPC::STWX:   case PPC::STWX8:
 257     case PPC::STWUX:
 258     case PPC::STW:    case PPC::STW8:
 259     case PPC::STWU:   case PPC::STWU8:
 260     case PPC::STVEWX:
 261     case PPC::STFIWX:
 262     case PPC::STWBRX:
 263       ThisStoreSize = 4;
 264       break;
 265     case PPC::STD_32:
 266     case PPC::STDX_32:
 267     case PPC::STD:
 268     case PPC::STDU:
 269     case PPC::STFD:
 270     case PPC::STFDX:
 271     case PPC::STDX:
 272     case PPC::STDUX:
 273       ThisStoreSize = 8;
 274       break;
 275     case PPC::STVX:
 276     case PPC::STVXL:
 277       ThisStoreSize = 16;
 278       break;
 279     }
 280
 281     StoreSize[NumStores] = ThisStoreSize;
 282     StorePtr1[NumStores] = Node->getOperand(1);
 283     StorePtr2[NumStores] = Node->getOperand(2);
 284     ++NumStores;
 285   }
 286
 287   if (InstrType == PPCII::PPC970_BRU || isSingle)
 288     NumIssued = 4;  // Terminate a d-group.
 289   ++NumIssued;
 290
 291   // If this instruction is cracked into two ops by the decoder, remember that
 292   // we issued two pieces.
 293   if (isCracked)
 294     ++NumIssued;
 295
 296   if (NumIssued == 5)
 297     EndDispatchGroup();
 298 }
 299
 300 void PPCHazardRecognizer970::AdvanceCycle() {
 301   assert(NumIssued < 5 && "Illegal dispatch group!");
 302   ++NumIssued;
 303   if (NumIssued == 5)
 304     EndDispatchGroup();
 305 }