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Merge branch 'master' into systemz
[llvm/systemz.git] / lib / Target / X86 / X86InstrInfo.cpp
blob6f5e717384fea6bdad537944bbbbafa012669c42
1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Target/TargetAsmInfo.h"
35 using namespace llvm;
36
37 namespace {
38 cl::opt<bool>
39 NoFusing("disable-spill-fusing",
40 cl::desc("Disable fusing of spill code into instructions"));
41 cl::opt<bool>
42 PrintFailedFusing("print-failed-fuse-candidates",
43 cl::desc("Print instructions that the allocator wants to"
44 " fuse, but the X86 backend currently can't"),
45 cl::Hidden);
46 cl::opt<bool>
47 ReMatPICStubLoad("remat-pic-stub-load",
48 cl::desc("Re-materialize load from stub in PIC mode"),
49 cl::init(false), cl::Hidden);
50 }
51
52 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
53 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
54 TM(tm), RI(tm, *this) {
55 SmallVector<unsigned,16> AmbEntries;
56 static const unsigned OpTbl2Addr[][2] = {
57 { X86::ADC32ri, X86::ADC32mi },
58 { X86::ADC32ri8, X86::ADC32mi8 },
59 { X86::ADC32rr, X86::ADC32mr },
60 { X86::ADC64ri32, X86::ADC64mi32 },
61 { X86::ADC64ri8, X86::ADC64mi8 },
62 { X86::ADC64rr, X86::ADC64mr },
63 { X86::ADD16ri, X86::ADD16mi },
64 { X86::ADD16ri8, X86::ADD16mi8 },
65 { X86::ADD16rr, X86::ADD16mr },
66 { X86::ADD32ri, X86::ADD32mi },
67 { X86::ADD32ri8, X86::ADD32mi8 },
68 { X86::ADD32rr, X86::ADD32mr },
69 { X86::ADD64ri32, X86::ADD64mi32 },
70 { X86::ADD64ri8, X86::ADD64mi8 },
71 { X86::ADD64rr, X86::ADD64mr },
72 { X86::ADD8ri, X86::ADD8mi },
73 { X86::ADD8rr, X86::ADD8mr },
74 { X86::AND16ri, X86::AND16mi },
75 { X86::AND16ri8, X86::AND16mi8 },
76 { X86::AND16rr, X86::AND16mr },
77 { X86::AND32ri, X86::AND32mi },
78 { X86::AND32ri8, X86::AND32mi8 },
79 { X86::AND32rr, X86::AND32mr },
80 { X86::AND64ri32, X86::AND64mi32 },
81 { X86::AND64ri8, X86::AND64mi8 },
82 { X86::AND64rr, X86::AND64mr },
83 { X86::AND8ri, X86::AND8mi },
84 { X86::AND8rr, X86::AND8mr },
85 { X86::DEC16r, X86::DEC16m },
86 { X86::DEC32r, X86::DEC32m },
87 { X86::DEC64_16r, X86::DEC64_16m },
88 { X86::DEC64_32r, X86::DEC64_32m },
89 { X86::DEC64r, X86::DEC64m },
90 { X86::DEC8r, X86::DEC8m },
91 { X86::INC16r, X86::INC16m },
92 { X86::INC32r, X86::INC32m },
93 { X86::INC64_16r, X86::INC64_16m },
94 { X86::INC64_32r, X86::INC64_32m },
95 { X86::INC64r, X86::INC64m },
96 { X86::INC8r, X86::INC8m },
97 { X86::NEG16r, X86::NEG16m },
98 { X86::NEG32r, X86::NEG32m },
99 { X86::NEG64r, X86::NEG64m },
100 { X86::NEG8r, X86::NEG8m },
101 { X86::NOT16r, X86::NOT16m },
102 { X86::NOT32r, X86::NOT32m },
103 { X86::NOT64r, X86::NOT64m },
104 { X86::NOT8r, X86::NOT8m },
105 { X86::OR16ri, X86::OR16mi },
106 { X86::OR16ri8, X86::OR16mi8 },
107 { X86::OR16rr, X86::OR16mr },
108 { X86::OR32ri, X86::OR32mi },
109 { X86::OR32ri8, X86::OR32mi8 },
110 { X86::OR32rr, X86::OR32mr },
111 { X86::OR64ri32, X86::OR64mi32 },
112 { X86::OR64ri8, X86::OR64mi8 },
113 { X86::OR64rr, X86::OR64mr },
114 { X86::OR8ri, X86::OR8mi },
115 { X86::OR8rr, X86::OR8mr },
116 { X86::ROL16r1, X86::ROL16m1 },
117 { X86::ROL16rCL, X86::ROL16mCL },
118 { X86::ROL16ri, X86::ROL16mi },
119 { X86::ROL32r1, X86::ROL32m1 },
120 { X86::ROL32rCL, X86::ROL32mCL },
121 { X86::ROL32ri, X86::ROL32mi },
122 { X86::ROL64r1, X86::ROL64m1 },
123 { X86::ROL64rCL, X86::ROL64mCL },
124 { X86::ROL64ri, X86::ROL64mi },
125 { X86::ROL8r1, X86::ROL8m1 },
126 { X86::ROL8rCL, X86::ROL8mCL },
127 { X86::ROL8ri, X86::ROL8mi },
128 { X86::ROR16r1, X86::ROR16m1 },
129 { X86::ROR16rCL, X86::ROR16mCL },
130 { X86::ROR16ri, X86::ROR16mi },
131 { X86::ROR32r1, X86::ROR32m1 },
132 { X86::ROR32rCL, X86::ROR32mCL },
133 { X86::ROR32ri, X86::ROR32mi },
134 { X86::ROR64r1, X86::ROR64m1 },
135 { X86::ROR64rCL, X86::ROR64mCL },
136 { X86::ROR64ri, X86::ROR64mi },
137 { X86::ROR8r1, X86::ROR8m1 },
138 { X86::ROR8rCL, X86::ROR8mCL },
139 { X86::ROR8ri, X86::ROR8mi },
140 { X86::SAR16r1, X86::SAR16m1 },
141 { X86::SAR16rCL, X86::SAR16mCL },
142 { X86::SAR16ri, X86::SAR16mi },
143 { X86::SAR32r1, X86::SAR32m1 },
144 { X86::SAR32rCL, X86::SAR32mCL },
145 { X86::SAR32ri, X86::SAR32mi },
146 { X86::SAR64r1, X86::SAR64m1 },
147 { X86::SAR64rCL, X86::SAR64mCL },
148 { X86::SAR64ri, X86::SAR64mi },
149 { X86::SAR8r1, X86::SAR8m1 },
150 { X86::SAR8rCL, X86::SAR8mCL },
151 { X86::SAR8ri, X86::SAR8mi },
152 { X86::SBB32ri, X86::SBB32mi },
153 { X86::SBB32ri8, X86::SBB32mi8 },
154 { X86::SBB32rr, X86::SBB32mr },
155 { X86::SBB64ri32, X86::SBB64mi32 },
156 { X86::SBB64ri8, X86::SBB64mi8 },
157 { X86::SBB64rr, X86::SBB64mr },
158 { X86::SHL16rCL, X86::SHL16mCL },
159 { X86::SHL16ri, X86::SHL16mi },
160 { X86::SHL32rCL, X86::SHL32mCL },
161 { X86::SHL32ri, X86::SHL32mi },
162 { X86::SHL64rCL, X86::SHL64mCL },
163 { X86::SHL64ri, X86::SHL64mi },
164 { X86::SHL8rCL, X86::SHL8mCL },
165 { X86::SHL8ri, X86::SHL8mi },
166 { X86::SHLD16rrCL, X86::SHLD16mrCL },
167 { X86::SHLD16rri8, X86::SHLD16mri8 },
168 { X86::SHLD32rrCL, X86::SHLD32mrCL },
169 { X86::SHLD32rri8, X86::SHLD32mri8 },
170 { X86::SHLD64rrCL, X86::SHLD64mrCL },
171 { X86::SHLD64rri8, X86::SHLD64mri8 },
172 { X86::SHR16r1, X86::SHR16m1 },
173 { X86::SHR16rCL, X86::SHR16mCL },
174 { X86::SHR16ri, X86::SHR16mi },
175 { X86::SHR32r1, X86::SHR32m1 },
176 { X86::SHR32rCL, X86::SHR32mCL },
177 { X86::SHR32ri, X86::SHR32mi },
178 { X86::SHR64r1, X86::SHR64m1 },
179 { X86::SHR64rCL, X86::SHR64mCL },
180 { X86::SHR64ri, X86::SHR64mi },
181 { X86::SHR8r1, X86::SHR8m1 },
182 { X86::SHR8rCL, X86::SHR8mCL },
183 { X86::SHR8ri, X86::SHR8mi },
184 { X86::SHRD16rrCL, X86::SHRD16mrCL },
185 { X86::SHRD16rri8, X86::SHRD16mri8 },
186 { X86::SHRD32rrCL, X86::SHRD32mrCL },
187 { X86::SHRD32rri8, X86::SHRD32mri8 },
188 { X86::SHRD64rrCL, X86::SHRD64mrCL },
189 { X86::SHRD64rri8, X86::SHRD64mri8 },
190 { X86::SUB16ri, X86::SUB16mi },
191 { X86::SUB16ri8, X86::SUB16mi8 },
192 { X86::SUB16rr, X86::SUB16mr },
193 { X86::SUB32ri, X86::SUB32mi },
194 { X86::SUB32ri8, X86::SUB32mi8 },
195 { X86::SUB32rr, X86::SUB32mr },
196 { X86::SUB64ri32, X86::SUB64mi32 },
197 { X86::SUB64ri8, X86::SUB64mi8 },
198 { X86::SUB64rr, X86::SUB64mr },
199 { X86::SUB8ri, X86::SUB8mi },
200 { X86::SUB8rr, X86::SUB8mr },
201 { X86::XOR16ri, X86::XOR16mi },
202 { X86::XOR16ri8, X86::XOR16mi8 },
203 { X86::XOR16rr, X86::XOR16mr },
204 { X86::XOR32ri, X86::XOR32mi },
205 { X86::XOR32ri8, X86::XOR32mi8 },
206 { X86::XOR32rr, X86::XOR32mr },
207 { X86::XOR64ri32, X86::XOR64mi32 },
208 { X86::XOR64ri8, X86::XOR64mi8 },
209 { X86::XOR64rr, X86::XOR64mr },
210 { X86::XOR8ri, X86::XOR8mi },
211 { X86::XOR8rr, X86::XOR8mr }
212 };
213
214 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
215 unsigned RegOp = OpTbl2Addr[i][0];
216 unsigned MemOp = OpTbl2Addr[i][1];
217 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
218 std::make_pair(MemOp,0))).second)
219 assert(false && "Duplicated entries?");
220 // Index 0, folded load and store, no alignment requirement.
221 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
222 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
223 std::make_pair(RegOp,
224 AuxInfo))).second)
225 AmbEntries.push_back(MemOp);
226 }
227
228 // If the third value is 1, then it's folding either a load or a store.
229 static const unsigned OpTbl0[][4] = {
230 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
231 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
232 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
233 { X86::CALL32r, X86::CALL32m, 1, 0 },
234 { X86::CALL64r, X86::CALL64m, 1, 0 },
235 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
236 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
237 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
238 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
239 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
240 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
241 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
242 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
243 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
244 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
245 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
246 { X86::DIV16r, X86::DIV16m, 1, 0 },
247 { X86::DIV32r, X86::DIV32m, 1, 0 },
248 { X86::DIV64r, X86::DIV64m, 1, 0 },
249 { X86::DIV8r, X86::DIV8m, 1, 0 },
250 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
251 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
252 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
253 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
254 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
255 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
256 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
257 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
258 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
259 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
260 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
261 { X86::JMP32r, X86::JMP32m, 1, 0 },
262 { X86::JMP64r, X86::JMP64m, 1, 0 },
263 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
264 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
265 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
266 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
267 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
268 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
269 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
270 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
271 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
272 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
273 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
274 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
275 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
276 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
277 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0, 0 },
278 { X86::MOVSDrr, X86::MOVSDmr, 0, 0 },
279 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
280 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
281 { X86::MOVSSrr, X86::MOVSSmr, 0, 0 },
282 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
283 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
284 { X86::MUL16r, X86::MUL16m, 1, 0 },
285 { X86::MUL32r, X86::MUL32m, 1, 0 },
286 { X86::MUL64r, X86::MUL64m, 1, 0 },
287 { X86::MUL8r, X86::MUL8m, 1, 0 },
288 { X86::SETAEr, X86::SETAEm, 0, 0 },
289 { X86::SETAr, X86::SETAm, 0, 0 },
290 { X86::SETBEr, X86::SETBEm, 0, 0 },
291 { X86::SETBr, X86::SETBm, 0, 0 },
292 { X86::SETEr, X86::SETEm, 0, 0 },
293 { X86::SETGEr, X86::SETGEm, 0, 0 },
294 { X86::SETGr, X86::SETGm, 0, 0 },
295 { X86::SETLEr, X86::SETLEm, 0, 0 },
296 { X86::SETLr, X86::SETLm, 0, 0 },
297 { X86::SETNEr, X86::SETNEm, 0, 0 },
298 { X86::SETNOr, X86::SETNOm, 0, 0 },
299 { X86::SETNPr, X86::SETNPm, 0, 0 },
300 { X86::SETNSr, X86::SETNSm, 0, 0 },
301 { X86::SETOr, X86::SETOm, 0, 0 },
302 { X86::SETPr, X86::SETPm, 0, 0 },
303 { X86::SETSr, X86::SETSm, 0, 0 },
304 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
305 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
306 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
307 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
308 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
309 };
310
311 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
312 unsigned RegOp = OpTbl0[i][0];
313 unsigned MemOp = OpTbl0[i][1];
314 unsigned Align = OpTbl0[i][3];
315 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
316 std::make_pair(MemOp,Align))).second)
317 assert(false && "Duplicated entries?");
318 unsigned FoldedLoad = OpTbl0[i][2];
319 // Index 0, folded load or store.
320 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
321 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
322 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
323 std::make_pair(RegOp, AuxInfo))).second)
324 AmbEntries.push_back(MemOp);
325 }
326
327 static const unsigned OpTbl1[][3] = {
328 { X86::CMP16rr, X86::CMP16rm, 0 },
329 { X86::CMP32rr, X86::CMP32rm, 0 },
330 { X86::CMP64rr, X86::CMP64rm, 0 },
331 { X86::CMP8rr, X86::CMP8rm, 0 },
332 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
333 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
334 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
335 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
336 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
337 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
338 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
339 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
340 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
341 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
342 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
343 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
344 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
345 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
346 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
347 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
348 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
349 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
350 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
351 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
352 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
353 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
354 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
355 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
356 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
357 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
358 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
359 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
360 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
361 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
362 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
363 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
364 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
365 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
366 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
367 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
368 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
369 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
370 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
371 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
372 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
373 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
374 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
375 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
376 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
377 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
378 { X86::MOV16rr, X86::MOV16rm, 0 },
379 { X86::MOV32rr, X86::MOV32rm, 0 },
380 { X86::MOV64rr, X86::MOV64rm, 0 },
381 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
382 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
383 { X86::MOV8rr, X86::MOV8rm, 0 },
384 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
385 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
386 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
387 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
388 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
389 { X86::MOVDQArr, X86::MOVDQArm, 16 },
390 { X86::MOVSD2PDrr, X86::MOVSD2PDrm, 0 },
391 { X86::MOVSDrr, X86::MOVSDrm, 0 },
392 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
393 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
394 { X86::MOVSS2PSrr, X86::MOVSS2PSrm, 0 },
395 { X86::MOVSSrr, X86::MOVSSrm, 0 },
396 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
397 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
398 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
399 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
400 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
401 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
402 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
403 { X86::MOVUPSrr, X86::MOVUPSrm, 16 },
404 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
405 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
406 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
407 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
408 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
409 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
410 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
411 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
412 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
413 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
414 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
415 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
416 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
417 { X86::RCPPSr, X86::RCPPSm, 16 },
418 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
419 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
420 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
421 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
422 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
423 { X86::SQRTPDr, X86::SQRTPDm, 16 },
424 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
425 { X86::SQRTPSr, X86::SQRTPSm, 16 },
426 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
427 { X86::SQRTSDr, X86::SQRTSDm, 0 },
428 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
429 { X86::SQRTSSr, X86::SQRTSSm, 0 },
430 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
431 { X86::TEST16rr, X86::TEST16rm, 0 },
432 { X86::TEST32rr, X86::TEST32rm, 0 },
433 { X86::TEST64rr, X86::TEST64rm, 0 },
434 { X86::TEST8rr, X86::TEST8rm, 0 },
435 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
436 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
437 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
438 };
439
440 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
441 unsigned RegOp = OpTbl1[i][0];
442 unsigned MemOp = OpTbl1[i][1];
443 unsigned Align = OpTbl1[i][2];
444 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
445 std::make_pair(MemOp,Align))).second)
446 assert(false && "Duplicated entries?");
447 // Index 1, folded load
448 unsigned AuxInfo = 1 | (1 << 4);
449 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
450 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
451 std::make_pair(RegOp, AuxInfo))).second)
452 AmbEntries.push_back(MemOp);
453 }
454
455 static const unsigned OpTbl2[][3] = {
456 { X86::ADC32rr, X86::ADC32rm, 0 },
457 { X86::ADC64rr, X86::ADC64rm, 0 },
458 { X86::ADD16rr, X86::ADD16rm, 0 },
459 { X86::ADD32rr, X86::ADD32rm, 0 },
460 { X86::ADD64rr, X86::ADD64rm, 0 },
461 { X86::ADD8rr, X86::ADD8rm, 0 },
462 { X86::ADDPDrr, X86::ADDPDrm, 16 },
463 { X86::ADDPSrr, X86::ADDPSrm, 16 },
464 { X86::ADDSDrr, X86::ADDSDrm, 0 },
465 { X86::ADDSSrr, X86::ADDSSrm, 0 },
466 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
467 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
468 { X86::AND16rr, X86::AND16rm, 0 },
469 { X86::AND32rr, X86::AND32rm, 0 },
470 { X86::AND64rr, X86::AND64rm, 0 },
471 { X86::AND8rr, X86::AND8rm, 0 },
472 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
473 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
474 { X86::ANDPDrr, X86::ANDPDrm, 16 },
475 { X86::ANDPSrr, X86::ANDPSrm, 16 },
476 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
477 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
478 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
479 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
480 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
481 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
482 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
483 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
484 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
485 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
486 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
487 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
488 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
489 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
490 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
491 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
492 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
493 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
494 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
495 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
496 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
497 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
498 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
499 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
500 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
501 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
502 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
503 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
504 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
505 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
506 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
507 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
508 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
509 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
510 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
511 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
512 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
513 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
514 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
515 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
516 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
517 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
518 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
519 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
520 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
521 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
522 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
523 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
524 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
525 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
526 { X86::CMPSDrr, X86::CMPSDrm, 0 },
527 { X86::CMPSSrr, X86::CMPSSrm, 0 },
528 { X86::DIVPDrr, X86::DIVPDrm, 16 },
529 { X86::DIVPSrr, X86::DIVPSrm, 16 },
530 { X86::DIVSDrr, X86::DIVSDrm, 0 },
531 { X86::DIVSSrr, X86::DIVSSrm, 0 },
532 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
533 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
534 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
535 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
536 { X86::FsORPDrr, X86::FsORPDrm, 16 },
537 { X86::FsORPSrr, X86::FsORPSrm, 16 },
538 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
539 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
540 { X86::HADDPDrr, X86::HADDPDrm, 16 },
541 { X86::HADDPSrr, X86::HADDPSrm, 16 },
542 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
543 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
544 { X86::IMUL16rr, X86::IMUL16rm, 0 },
545 { X86::IMUL32rr, X86::IMUL32rm, 0 },
546 { X86::IMUL64rr, X86::IMUL64rm, 0 },
547 { X86::MAXPDrr, X86::MAXPDrm, 16 },
548 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
549 { X86::MAXPSrr, X86::MAXPSrm, 16 },
550 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
551 { X86::MAXSDrr, X86::MAXSDrm, 0 },
552 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
553 { X86::MAXSSrr, X86::MAXSSrm, 0 },
554 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
555 { X86::MINPDrr, X86::MINPDrm, 16 },
556 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
557 { X86::MINPSrr, X86::MINPSrm, 16 },
558 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
559 { X86::MINSDrr, X86::MINSDrm, 0 },
560 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
561 { X86::MINSSrr, X86::MINSSrm, 0 },
562 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
563 { X86::MULPDrr, X86::MULPDrm, 16 },
564 { X86::MULPSrr, X86::MULPSrm, 16 },
565 { X86::MULSDrr, X86::MULSDrm, 0 },
566 { X86::MULSSrr, X86::MULSSrm, 0 },
567 { X86::OR16rr, X86::OR16rm, 0 },
568 { X86::OR32rr, X86::OR32rm, 0 },
569 { X86::OR64rr, X86::OR64rm, 0 },
570 { X86::OR8rr, X86::OR8rm, 0 },
571 { X86::ORPDrr, X86::ORPDrm, 16 },
572 { X86::ORPSrr, X86::ORPSrm, 16 },
573 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
574 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
575 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
576 { X86::PADDBrr, X86::PADDBrm, 16 },
577 { X86::PADDDrr, X86::PADDDrm, 16 },
578 { X86::PADDQrr, X86::PADDQrm, 16 },
579 { X86::PADDSBrr, X86::PADDSBrm, 16 },
580 { X86::PADDSWrr, X86::PADDSWrm, 16 },
581 { X86::PADDWrr, X86::PADDWrm, 16 },
582 { X86::PANDNrr, X86::PANDNrm, 16 },
583 { X86::PANDrr, X86::PANDrm, 16 },
584 { X86::PAVGBrr, X86::PAVGBrm, 16 },
585 { X86::PAVGWrr, X86::PAVGWrm, 16 },
586 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
587 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
588 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
589 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
590 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
591 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
592 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
593 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
594 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
595 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
596 { X86::PMINSWrr, X86::PMINSWrm, 16 },
597 { X86::PMINUBrr, X86::PMINUBrm, 16 },
598 { X86::PMULDQrr, X86::PMULDQrm, 16 },
599 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
600 { X86::PMULHWrr, X86::PMULHWrm, 16 },
601 { X86::PMULLDrr, X86::PMULLDrm, 16 },
602 { X86::PMULLDrr_int, X86::PMULLDrm_int, 16 },
603 { X86::PMULLWrr, X86::PMULLWrm, 16 },
604 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
605 { X86::PORrr, X86::PORrm, 16 },
606 { X86::PSADBWrr, X86::PSADBWrm, 16 },
607 { X86::PSLLDrr, X86::PSLLDrm, 16 },
608 { X86::PSLLQrr, X86::PSLLQrm, 16 },
609 { X86::PSLLWrr, X86::PSLLWrm, 16 },
610 { X86::PSRADrr, X86::PSRADrm, 16 },
611 { X86::PSRAWrr, X86::PSRAWrm, 16 },
612 { X86::PSRLDrr, X86::PSRLDrm, 16 },
613 { X86::PSRLQrr, X86::PSRLQrm, 16 },
614 { X86::PSRLWrr, X86::PSRLWrm, 16 },
615 { X86::PSUBBrr, X86::PSUBBrm, 16 },
616 { X86::PSUBDrr, X86::PSUBDrm, 16 },
617 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
618 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
619 { X86::PSUBWrr, X86::PSUBWrm, 16 },
620 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
621 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
622 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
623 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
624 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
625 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
626 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
627 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
628 { X86::PXORrr, X86::PXORrm, 16 },
629 { X86::SBB32rr, X86::SBB32rm, 0 },
630 { X86::SBB64rr, X86::SBB64rm, 0 },
631 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
632 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
633 { X86::SUB16rr, X86::SUB16rm, 0 },
634 { X86::SUB32rr, X86::SUB32rm, 0 },
635 { X86::SUB64rr, X86::SUB64rm, 0 },
636 { X86::SUB8rr, X86::SUB8rm, 0 },
637 { X86::SUBPDrr, X86::SUBPDrm, 16 },
638 { X86::SUBPSrr, X86::SUBPSrm, 16 },
639 { X86::SUBSDrr, X86::SUBSDrm, 0 },
640 { X86::SUBSSrr, X86::SUBSSrm, 0 },
641 // FIXME: TEST*rr -> swapped operand of TEST*mr.
642 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
643 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
644 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
645 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
646 { X86::XOR16rr, X86::XOR16rm, 0 },
647 { X86::XOR32rr, X86::XOR32rm, 0 },
648 { X86::XOR64rr, X86::XOR64rm, 0 },
649 { X86::XOR8rr, X86::XOR8rm, 0 },
650 { X86::XORPDrr, X86::XORPDrm, 16 },
651 { X86::XORPSrr, X86::XORPSrm, 16 }
652 };
653
654 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
655 unsigned RegOp = OpTbl2[i][0];
656 unsigned MemOp = OpTbl2[i][1];
657 unsigned Align = OpTbl2[i][2];
658 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
659 std::make_pair(MemOp,Align))).second)
660 assert(false && "Duplicated entries?");
661 // Index 2, folded load
662 unsigned AuxInfo = 2 | (1 << 4);
663 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
664 std::make_pair(RegOp, AuxInfo))).second)
665 AmbEntries.push_back(MemOp);
666 }
667
668 // Remove ambiguous entries.
669 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
670 }
671
672 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
673 unsigned &SrcReg, unsigned &DstReg,
674 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
675 switch (MI.getOpcode()) {
676 default:
677 return false;
678 case X86::MOV8rr:
679 case X86::MOV8rr_NOREX:
680 case X86::MOV16rr:
681 case X86::MOV32rr:
682 case X86::MOV64rr:
683 case X86::MOVSSrr:
684 case X86::MOVSDrr:
685
686 // FP Stack register class copies
687 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
688 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
689 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
690
691 case X86::FsMOVAPSrr:
692 case X86::FsMOVAPDrr:
693 case X86::MOVAPSrr:
694 case X86::MOVAPDrr:
695 case X86::MOVDQArr:
696 case X86::MOVSS2PSrr:
697 case X86::MOVSD2PDrr:
698 case X86::MOVPS2SSrr:
699 case X86::MOVPD2SDrr:
700 case X86::MMX_MOVQ64rr:
701 assert(MI.getNumOperands() >= 2 &&
702 MI.getOperand(0).isReg() &&
703 MI.getOperand(1).isReg() &&
704 "invalid register-register move instruction");
705 SrcReg = MI.getOperand(1).getReg();
706 DstReg = MI.getOperand(0).getReg();
707 SrcSubIdx = MI.getOperand(1).getSubReg();
708 DstSubIdx = MI.getOperand(0).getSubReg();
709 return true;
710 }
711 }
712
713 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
714 int &FrameIndex) const {
715 switch (MI->getOpcode()) {
716 default: break;
717 case X86::MOV8rm:
718 case X86::MOV16rm:
719 case X86::MOV32rm:
720 case X86::MOV64rm:
721 case X86::LD_Fp64m:
722 case X86::MOVSSrm:
723 case X86::MOVSDrm:
724 case X86::MOVAPSrm:
725 case X86::MOVAPDrm:
726 case X86::MOVDQArm:
727 case X86::MMX_MOVD64rm:
728 case X86::MMX_MOVQ64rm:
729 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
730 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
731 MI->getOperand(2).getImm() == 1 &&
732 MI->getOperand(3).getReg() == 0 &&
733 MI->getOperand(4).getImm() == 0) {
734 FrameIndex = MI->getOperand(1).getIndex();
735 return MI->getOperand(0).getReg();
736 }
737 break;
738 }
739 return 0;
740 }
741
742 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
743 int &FrameIndex) const {
744 switch (MI->getOpcode()) {
745 default: break;
746 case X86::MOV8mr:
747 case X86::MOV16mr:
748 case X86::MOV32mr:
749 case X86::MOV64mr:
750 case X86::ST_FpP64m:
751 case X86::MOVSSmr:
752 case X86::MOVSDmr:
753 case X86::MOVAPSmr:
754 case X86::MOVAPDmr:
755 case X86::MOVDQAmr:
756 case X86::MMX_MOVD64mr:
757 case X86::MMX_MOVQ64mr:
758 case X86::MMX_MOVNTQmr:
759 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
760 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
761 MI->getOperand(1).getImm() == 1 &&
762 MI->getOperand(2).getReg() == 0 &&
763 MI->getOperand(3).getImm() == 0) {
764 FrameIndex = MI->getOperand(0).getIndex();
765 return MI->getOperand(X86AddrNumOperands).getReg();
766 }
767 break;
768 }
769 return 0;
770 }
771
772 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
773 /// X86::MOVPC32r.
774 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
775 bool isPICBase = false;
776 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
777 E = MRI.def_end(); I != E; ++I) {
778 MachineInstr *DefMI = I.getOperand().getParent();
779 if (DefMI->getOpcode() != X86::MOVPC32r)
780 return false;
781 assert(!isPICBase && "More than one PIC base?");
782 isPICBase = true;
783 }
784 return isPICBase;
785 }
786
787 /// CanRematLoadWithDispOperand - Return true if a load with the specified
788 /// operand is a candidate for remat: for this to be true we need to know that
789 /// the load will always return the same value, even if moved.
790 static bool CanRematLoadWithDispOperand(const MachineOperand &MO,
791 X86TargetMachine &TM) {
792 // Loads from constant pool entries can be remat'd.
793 if (MO.isCPI()) return true;
794
795 // We can remat globals in some cases.
796 if (MO.isGlobal()) {
797 // If this is a load of a stub, not of the global, we can remat it. This
798 // access will always return the address of the global.
799 if (isGlobalStubReference(MO.getTargetFlags()))
800 return true;
801
802 // If the global itself is constant, we can remat the load.
803 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(MO.getGlobal()))
804 if (GV->isConstant())
805 return true;
806 }
807 return false;
808 }
809
810 bool
811 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
812 switch (MI->getOpcode()) {
813 default: break;
814 case X86::MOV8rm:
815 case X86::MOV16rm:
816 case X86::MOV32rm:
817 case X86::MOV64rm:
818 case X86::LD_Fp64m:
819 case X86::MOVSSrm:
820 case X86::MOVSDrm:
821 case X86::MOVAPSrm:
822 case X86::MOVAPDrm:
823 case X86::MOVDQArm:
824 case X86::MMX_MOVD64rm:
825 case X86::MMX_MOVQ64rm: {
826 // Loads from constant pools are trivially rematerializable.
827 if (MI->getOperand(1).isReg() &&
828 MI->getOperand(2).isImm() &&
829 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
830 CanRematLoadWithDispOperand(MI->getOperand(4), TM)) {
831 unsigned BaseReg = MI->getOperand(1).getReg();
832 if (BaseReg == 0 || BaseReg == X86::RIP)
833 return true;
834 // Allow re-materialization of PIC load.
835 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
836 return false;
837 const MachineFunction &MF = *MI->getParent()->getParent();
838 const MachineRegisterInfo &MRI = MF.getRegInfo();
839 bool isPICBase = false;
840 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
841 E = MRI.def_end(); I != E; ++I) {
842 MachineInstr *DefMI = I.getOperand().getParent();
843 if (DefMI->getOpcode() != X86::MOVPC32r)
844 return false;
845 assert(!isPICBase && "More than one PIC base?");
846 isPICBase = true;
847 }
848 return isPICBase;
849 }
850 return false;
851 }
852
853 case X86::LEA32r:
854 case X86::LEA64r: {
855 if (MI->getOperand(2).isImm() &&
856 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
857 !MI->getOperand(4).isReg()) {
858 // lea fi#, lea GV, etc. are all rematerializable.
859 if (!MI->getOperand(1).isReg())
860 return true;
861 unsigned BaseReg = MI->getOperand(1).getReg();
862 if (BaseReg == 0)
863 return true;
864 // Allow re-materialization of lea PICBase + x.
865 const MachineFunction &MF = *MI->getParent()->getParent();
866 const MachineRegisterInfo &MRI = MF.getRegInfo();
867 return regIsPICBase(BaseReg, MRI);
868 }
869 return false;
870 }
871 }
872
873 // All other instructions marked M_REMATERIALIZABLE are always trivially
874 // rematerializable.
875 return true;
876 }
877
878 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
879 /// would clobber the EFLAGS condition register. Note the result may be
880 /// conservative. If it cannot definitely determine the safety after visiting
881 /// two instructions it assumes it's not safe.
882 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
883 MachineBasicBlock::iterator I) {
884 // It's always safe to clobber EFLAGS at the end of a block.
885 if (I == MBB.end())
886 return true;
887
888 // For compile time consideration, if we are not able to determine the
889 // safety after visiting 2 instructions, we will assume it's not safe.
890 for (unsigned i = 0; i < 2; ++i) {
891 bool SeenDef = false;
892 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
893 MachineOperand &MO = I->getOperand(j);
894 if (!MO.isReg())
895 continue;
896 if (MO.getReg() == X86::EFLAGS) {
897 if (MO.isUse())
898 return false;
899 SeenDef = true;
900 }
901 }
902
903 if (SeenDef)
904 // This instruction defines EFLAGS, no need to look any further.
905 return true;
906 ++I;
907
908 // If we make it to the end of the block, it's safe to clobber EFLAGS.
909 if (I == MBB.end())
910 return true;
911 }
912
913 // Conservative answer.
914 return false;
915 }
916
917 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
918 MachineBasicBlock::iterator I,
919 unsigned DestReg,
920 const MachineInstr *Orig) const {
921 DebugLoc DL = DebugLoc::getUnknownLoc();
922 if (I != MBB.end()) DL = I->getDebugLoc();
923
924 unsigned SubIdx = Orig->getOperand(0).isReg()
925 ? Orig->getOperand(0).getSubReg() : 0;
926 bool ChangeSubIdx = SubIdx != 0;
927 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
928 DestReg = RI.getSubReg(DestReg, SubIdx);
929 SubIdx = 0;
930 }
931
932 // MOV32r0 etc. are implemented with xor which clobbers condition code.
933 // Re-materialize them as movri instructions to avoid side effects.
934 bool Emitted = false;
935 switch (Orig->getOpcode()) {
936 default: break;
937 case X86::MOV8r0:
938 case X86::MOV16r0:
939 case X86::MOV32r0: {
940 if (!isSafeToClobberEFLAGS(MBB, I)) {
941 unsigned Opc = 0;
942 switch (Orig->getOpcode()) {
943 default: break;
944 case X86::MOV8r0: Opc = X86::MOV8ri; break;
945 case X86::MOV16r0: Opc = X86::MOV16ri; break;
946 case X86::MOV32r0: Opc = X86::MOV32ri; break;
947 }
948 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
949 Emitted = true;
950 }
951 break;
952 }
953 }
954
955 if (!Emitted) {
956 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
957 MI->getOperand(0).setReg(DestReg);
958 MBB.insert(I, MI);
959 }
960
961 if (ChangeSubIdx) {
962 MachineInstr *NewMI = prior(I);
963 NewMI->getOperand(0).setSubReg(SubIdx);
964 }
965 }
966
967 /// isInvariantLoad - Return true if the specified instruction (which is marked
968 /// mayLoad) is loading from a location whose value is invariant across the
969 /// function. For example, loading a value from the constant pool or from
970 /// from the argument area of a function if it does not change. This should
971 /// only return true of *all* loads the instruction does are invariant (if it
972 /// does multiple loads).
973 bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const {
974 // This code cares about loads from three cases: constant pool entries,
975 // invariant argument slots, and global stubs. In order to handle these cases
976 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
977 // operand and base our analysis on it. This is safe because the address of
978 // none of these three cases is ever used as anything other than a load base
979 // and X86 doesn't have any instructions that load from multiple places.
980
981 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
982 const MachineOperand &MO = MI->getOperand(i);
983 // Loads from constant pools are trivially invariant.
984 if (MO.isCPI())
985 return true;
986
987 if (MO.isGlobal())
988 return isGlobalStubReference(MO.getTargetFlags());
989
990 // If this is a load from an invariant stack slot, the load is a constant.
991 if (MO.isFI()) {
992 const MachineFrameInfo &MFI =
993 *MI->getParent()->getParent()->getFrameInfo();
994 int Idx = MO.getIndex();
995 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
996 }
997 }
998
999 // All other instances of these instructions are presumed to have other
1000 // issues.
1001 return false;
1002 }
1003
1004 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1005 /// is not marked dead.
1006 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1007 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1008 MachineOperand &MO = MI->getOperand(i);
1009 if (MO.isReg() && MO.isDef() &&
1010 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1011 return true;
1012 }
1013 }
1014 return false;
1015 }
1016
1017 /// convertToThreeAddress - This method must be implemented by targets that
1018 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1019 /// may be able to convert a two-address instruction into a true
1020 /// three-address instruction on demand. This allows the X86 target (for
1021 /// example) to convert ADD and SHL instructions into LEA instructions if they
1022 /// would require register copies due to two-addressness.
1023 ///
1024 /// This method returns a null pointer if the transformation cannot be
1025 /// performed, otherwise it returns the new instruction.
1026 ///
1027 MachineInstr *
1028 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1029 MachineBasicBlock::iterator &MBBI,
1030 LiveVariables *LV) const {
1031 MachineInstr *MI = MBBI;
1032 MachineFunction &MF = *MI->getParent()->getParent();
1033 // All instructions input are two-addr instructions. Get the known operands.
1034 unsigned Dest = MI->getOperand(0).getReg();
1035 unsigned Src = MI->getOperand(1).getReg();
1036 bool isDead = MI->getOperand(0).isDead();
1037 bool isKill = MI->getOperand(1).isKill();
1038
1039 MachineInstr *NewMI = NULL;
1040 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1041 // we have better subtarget support, enable the 16-bit LEA generation here.
1042 bool DisableLEA16 = true;
1043
1044 unsigned MIOpc = MI->getOpcode();
1045 switch (MIOpc) {
1046 case X86::SHUFPSrri: {
1047 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1048 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1049
1050 unsigned B = MI->getOperand(1).getReg();
1051 unsigned C = MI->getOperand(2).getReg();
1052 if (B != C) return 0;
1053 unsigned A = MI->getOperand(0).getReg();
1054 unsigned M = MI->getOperand(3).getImm();
1055 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1056 .addReg(A, RegState::Define | getDeadRegState(isDead))
1057 .addReg(B, getKillRegState(isKill)).addImm(M);
1058 break;
1059 }
1060 case X86::SHL64ri: {
1061 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1062 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1063 // the flags produced by a shift yet, so this is safe.
1064 unsigned ShAmt = MI->getOperand(2).getImm();
1065 if (ShAmt == 0 || ShAmt >= 4) return 0;
1066
1067 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1068 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1069 .addReg(0).addImm(1 << ShAmt)
1070 .addReg(Src, getKillRegState(isKill))
1071 .addImm(0);
1072 break;
1073 }
1074 case X86::SHL32ri: {
1075 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1076 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1077 // the flags produced by a shift yet, so this is safe.
1078 unsigned ShAmt = MI->getOperand(2).getImm();
1079 if (ShAmt == 0 || ShAmt >= 4) return 0;
1080
1081 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1082 X86::LEA64_32r : X86::LEA32r;
1083 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1084 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1085 .addReg(0).addImm(1 << ShAmt)
1086 .addReg(Src, getKillRegState(isKill)).addImm(0);
1087 break;
1088 }
1089 case X86::SHL16ri: {
1090 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1091 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1092 // the flags produced by a shift yet, so this is safe.
1093 unsigned ShAmt = MI->getOperand(2).getImm();
1094 if (ShAmt == 0 || ShAmt >= 4) return 0;
1095
1096 if (DisableLEA16) {
1097 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1098 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1099 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1100 ? X86::LEA64_32r : X86::LEA32r;
1101 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1102 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1103
1104 // Build and insert into an implicit UNDEF value. This is OK because
1105 // well be shifting and then extracting the lower 16-bits.
1106 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1107 MachineInstr *InsMI =
1108 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1109 .addReg(leaInReg)
1110 .addReg(Src, getKillRegState(isKill))
1111 .addImm(X86::SUBREG_16BIT);
1112
1113 NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1114 .addReg(0).addImm(1 << ShAmt)
1115 .addReg(leaInReg, RegState::Kill)
1116 .addImm(0);
1117
1118 MachineInstr *ExtMI =
1119 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1120 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1121 .addReg(leaOutReg, RegState::Kill)
1122 .addImm(X86::SUBREG_16BIT);
1123
1124 if (LV) {
1125 // Update live variables
1126 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1127 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1128 if (isKill)
1129 LV->replaceKillInstruction(Src, MI, InsMI);
1130 if (isDead)
1131 LV->replaceKillInstruction(Dest, MI, ExtMI);
1132 }
1133 return ExtMI;
1134 } else {
1135 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1136 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1137 .addReg(0).addImm(1 << ShAmt)
1138 .addReg(Src, getKillRegState(isKill))
1139 .addImm(0);
1140 }
1141 break;
1142 }
1143 default: {
1144 // The following opcodes also sets the condition code register(s). Only
1145 // convert them to equivalent lea if the condition code register def's
1146 // are dead!
1147 if (hasLiveCondCodeDef(MI))
1148 return 0;
1149
1150 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1151 switch (MIOpc) {
1152 default: return 0;
1153 case X86::INC64r:
1154 case X86::INC32r:
1155 case X86::INC64_32r: {
1156 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1157 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1158 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1159 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1160 .addReg(Dest, RegState::Define |
1161 getDeadRegState(isDead)),
1162 Src, isKill, 1);
1163 break;
1164 }
1165 case X86::INC16r:
1166 case X86::INC64_16r:
1167 if (DisableLEA16) return 0;
1168 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1169 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1170 .addReg(Dest, RegState::Define |
1171 getDeadRegState(isDead)),
1172 Src, isKill, 1);
1173 break;
1174 case X86::DEC64r:
1175 case X86::DEC32r:
1176 case X86::DEC64_32r: {
1177 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1178 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1179 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1180 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1181 .addReg(Dest, RegState::Define |
1182 getDeadRegState(isDead)),
1183 Src, isKill, -1);
1184 break;
1185 }
1186 case X86::DEC16r:
1187 case X86::DEC64_16r:
1188 if (DisableLEA16) return 0;
1189 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1190 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1191 .addReg(Dest, RegState::Define |
1192 getDeadRegState(isDead)),
1193 Src, isKill, -1);
1194 break;
1195 case X86::ADD64rr:
1196 case X86::ADD32rr: {
1197 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1198 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1199 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1200 unsigned Src2 = MI->getOperand(2).getReg();
1201 bool isKill2 = MI->getOperand(2).isKill();
1202 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1203 .addReg(Dest, RegState::Define |
1204 getDeadRegState(isDead)),
1205 Src, isKill, Src2, isKill2);
1206 if (LV && isKill2)
1207 LV->replaceKillInstruction(Src2, MI, NewMI);
1208 break;
1209 }
1210 case X86::ADD16rr: {
1211 if (DisableLEA16) return 0;
1212 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1213 unsigned Src2 = MI->getOperand(2).getReg();
1214 bool isKill2 = MI->getOperand(2).isKill();
1215 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1216 .addReg(Dest, RegState::Define |
1217 getDeadRegState(isDead)),
1218 Src, isKill, Src2, isKill2);
1219 if (LV && isKill2)
1220 LV->replaceKillInstruction(Src2, MI, NewMI);
1221 break;
1222 }
1223 case X86::ADD64ri32:
1224 case X86::ADD64ri8:
1225 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1226 if (MI->getOperand(2).isImm())
1227 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1228 .addReg(Dest, RegState::Define |
1229 getDeadRegState(isDead)),
1230 Src, isKill, MI->getOperand(2).getImm());
1231 break;
1232 case X86::ADD32ri:
1233 case X86::ADD32ri8:
1234 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1235 if (MI->getOperand(2).isImm()) {
1236 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1237 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1238 .addReg(Dest, RegState::Define |
1239 getDeadRegState(isDead)),
1240 Src, isKill, MI->getOperand(2).getImm());
1241 }
1242 break;
1243 case X86::ADD16ri:
1244 case X86::ADD16ri8:
1245 if (DisableLEA16) return 0;
1246 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1247 if (MI->getOperand(2).isImm())
1248 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1249 .addReg(Dest, RegState::Define |
1250 getDeadRegState(isDead)),
1251 Src, isKill, MI->getOperand(2).getImm());
1252 break;
1253 case X86::SHL16ri:
1254 if (DisableLEA16) return 0;
1255 case X86::SHL32ri:
1256 case X86::SHL64ri: {
1257 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1258 "Unknown shl instruction!");
1259 unsigned ShAmt = MI->getOperand(2).getImm();
1260 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1261 X86AddressMode AM;
1262 AM.Scale = 1 << ShAmt;
1263 AM.IndexReg = Src;
1264 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1265 : (MIOpc == X86::SHL32ri
1266 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1267 NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1268 .addReg(Dest, RegState::Define |
1269 getDeadRegState(isDead)), AM);
1270 if (isKill)
1271 NewMI->getOperand(3).setIsKill(true);
1272 }
1273 break;
1274 }
1275 }
1276 }
1277 }
1278
1279 if (!NewMI) return 0;
1280
1281 if (LV) { // Update live variables
1282 if (isKill)
1283 LV->replaceKillInstruction(Src, MI, NewMI);
1284 if (isDead)
1285 LV->replaceKillInstruction(Dest, MI, NewMI);
1286 }
1287
1288 MFI->insert(MBBI, NewMI); // Insert the new inst
1289 return NewMI;
1290 }
1291
1292 /// commuteInstruction - We have a few instructions that must be hacked on to
1293 /// commute them.
1294 ///
1295 MachineInstr *
1296 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1297 switch (MI->getOpcode()) {
1298 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1299 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1300 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1301 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1302 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1303 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1304 unsigned Opc;
1305 unsigned Size;
1306 switch (MI->getOpcode()) {
1307 default: llvm_unreachable("Unreachable!");
1308 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1309 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1310 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1311 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1312 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1313 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1314 }
1315 unsigned Amt = MI->getOperand(3).getImm();
1316 if (NewMI) {
1317 MachineFunction &MF = *MI->getParent()->getParent();
1318 MI = MF.CloneMachineInstr(MI);
1319 NewMI = false;
1320 }
1321 MI->setDesc(get(Opc));
1322 MI->getOperand(3).setImm(Size-Amt);
1323 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1324 }
1325 case X86::CMOVB16rr:
1326 case X86::CMOVB32rr:
1327 case X86::CMOVB64rr:
1328 case X86::CMOVAE16rr:
1329 case X86::CMOVAE32rr:
1330 case X86::CMOVAE64rr:
1331 case X86::CMOVE16rr:
1332 case X86::CMOVE32rr:
1333 case X86::CMOVE64rr:
1334 case X86::CMOVNE16rr:
1335 case X86::CMOVNE32rr:
1336 case X86::CMOVNE64rr:
1337 case X86::CMOVBE16rr:
1338 case X86::CMOVBE32rr:
1339 case X86::CMOVBE64rr:
1340 case X86::CMOVA16rr:
1341 case X86::CMOVA32rr:
1342 case X86::CMOVA64rr:
1343 case X86::CMOVL16rr:
1344 case X86::CMOVL32rr:
1345 case X86::CMOVL64rr:
1346 case X86::CMOVGE16rr:
1347 case X86::CMOVGE32rr:
1348 case X86::CMOVGE64rr:
1349 case X86::CMOVLE16rr:
1350 case X86::CMOVLE32rr:
1351 case X86::CMOVLE64rr:
1352 case X86::CMOVG16rr:
1353 case X86::CMOVG32rr:
1354 case X86::CMOVG64rr:
1355 case X86::CMOVS16rr:
1356 case X86::CMOVS32rr:
1357 case X86::CMOVS64rr:
1358 case X86::CMOVNS16rr:
1359 case X86::CMOVNS32rr:
1360 case X86::CMOVNS64rr:
1361 case X86::CMOVP16rr:
1362 case X86::CMOVP32rr:
1363 case X86::CMOVP64rr:
1364 case X86::CMOVNP16rr:
1365 case X86::CMOVNP32rr:
1366 case X86::CMOVNP64rr:
1367 case X86::CMOVO16rr:
1368 case X86::CMOVO32rr:
1369 case X86::CMOVO64rr:
1370 case X86::CMOVNO16rr:
1371 case X86::CMOVNO32rr:
1372 case X86::CMOVNO64rr: {
1373 unsigned Opc = 0;
1374 switch (MI->getOpcode()) {
1375 default: break;
1376 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1377 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1378 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1379 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1380 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1381 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1382 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1383 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1384 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1385 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1386 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1387 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1388 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1389 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1390 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1391 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1392 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1393 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1394 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1395 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1396 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1397 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1398 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1399 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1400 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1401 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1402 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1403 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1404 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1405 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1406 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1407 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1408 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1409 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1410 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1411 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1412 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1413 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1414 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1415 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1416 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1417 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1418 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1419 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1420 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1421 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1422 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1423 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1424 }
1425 if (NewMI) {
1426 MachineFunction &MF = *MI->getParent()->getParent();
1427 MI = MF.CloneMachineInstr(MI);
1428 NewMI = false;
1429 }
1430 MI->setDesc(get(Opc));
1431 // Fallthrough intended.
1432 }
1433 default:
1434 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1435 }
1436 }
1437
1438 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1439 switch (BrOpc) {
1440 default: return X86::COND_INVALID;
1441 case X86::JE: return X86::COND_E;
1442 case X86::JNE: return X86::COND_NE;
1443 case X86::JL: return X86::COND_L;
1444 case X86::JLE: return X86::COND_LE;
1445 case X86::JG: return X86::COND_G;
1446 case X86::JGE: return X86::COND_GE;
1447 case X86::JB: return X86::COND_B;
1448 case X86::JBE: return X86::COND_BE;
1449 case X86::JA: return X86::COND_A;
1450 case X86::JAE: return X86::COND_AE;
1451 case X86::JS: return X86::COND_S;
1452 case X86::JNS: return X86::COND_NS;
1453 case X86::JP: return X86::COND_P;
1454 case X86::JNP: return X86::COND_NP;
1455 case X86::JO: return X86::COND_O;
1456 case X86::JNO: return X86::COND_NO;
1457 }
1458 }
1459
1460 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1461 switch (CC) {
1462 default: llvm_unreachable("Illegal condition code!");
1463 case X86::COND_E: return X86::JE;
1464 case X86::COND_NE: return X86::JNE;
1465 case X86::COND_L: return X86::JL;
1466 case X86::COND_LE: return X86::JLE;
1467 case X86::COND_G: return X86::JG;
1468 case X86::COND_GE: return X86::JGE;
1469 case X86::COND_B: return X86::JB;
1470 case X86::COND_BE: return X86::JBE;
1471 case X86::COND_A: return X86::JA;
1472 case X86::COND_AE: return X86::JAE;
1473 case X86::COND_S: return X86::JS;
1474 case X86::COND_NS: return X86::JNS;
1475 case X86::COND_P: return X86::JP;
1476 case X86::COND_NP: return X86::JNP;
1477 case X86::COND_O: return X86::JO;
1478 case X86::COND_NO: return X86::JNO;
1479 }
1480 }
1481
1482 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1483 /// e.g. turning COND_E to COND_NE.
1484 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1485 switch (CC) {
1486 default: llvm_unreachable("Illegal condition code!");
1487 case X86::COND_E: return X86::COND_NE;
1488 case X86::COND_NE: return X86::COND_E;
1489 case X86::COND_L: return X86::COND_GE;
1490 case X86::COND_LE: return X86::COND_G;
1491 case X86::COND_G: return X86::COND_LE;
1492 case X86::COND_GE: return X86::COND_L;
1493 case X86::COND_B: return X86::COND_AE;
1494 case X86::COND_BE: return X86::COND_A;
1495 case X86::COND_A: return X86::COND_BE;
1496 case X86::COND_AE: return X86::COND_B;
1497 case X86::COND_S: return X86::COND_NS;
1498 case X86::COND_NS: return X86::COND_S;
1499 case X86::COND_P: return X86::COND_NP;
1500 case X86::COND_NP: return X86::COND_P;
1501 case X86::COND_O: return X86::COND_NO;
1502 case X86::COND_NO: return X86::COND_O;
1503 }
1504 }
1505
1506 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1507 const TargetInstrDesc &TID = MI->getDesc();
1508 if (!TID.isTerminator()) return false;
1509
1510 // Conditional branch is a special case.
1511 if (TID.isBranch() && !TID.isBarrier())
1512 return true;
1513 if (!TID.isPredicable())
1514 return true;
1515 return !isPredicated(MI);
1516 }
1517
1518 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1519 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1520 const X86InstrInfo &TII) {
1521 if (MI->getOpcode() == X86::FP_REG_KILL)
1522 return false;
1523 return TII.isUnpredicatedTerminator(MI);
1524 }
1525
1526 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1527 MachineBasicBlock *&TBB,
1528 MachineBasicBlock *&FBB,
1529 SmallVectorImpl<MachineOperand> &Cond,
1530 bool AllowModify) const {
1531 // Start from the bottom of the block and work up, examining the
1532 // terminator instructions.
1533 MachineBasicBlock::iterator I = MBB.end();
1534 while (I != MBB.begin()) {
1535 --I;
1536 // Working from the bottom, when we see a non-terminator
1537 // instruction, we're done.
1538 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1539 break;
1540 // A terminator that isn't a branch can't easily be handled
1541 // by this analysis.
1542 if (!I->getDesc().isBranch())
1543 return true;
1544 // Handle unconditional branches.
1545 if (I->getOpcode() == X86::JMP) {
1546 if (!AllowModify) {
1547 TBB = I->getOperand(0).getMBB();
1548 continue;
1549 }
1550
1551 // If the block has any instructions after a JMP, delete them.
1552 while (next(I) != MBB.end())
1553 next(I)->eraseFromParent();
1554 Cond.clear();
1555 FBB = 0;
1556 // Delete the JMP if it's equivalent to a fall-through.
1557 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1558 TBB = 0;
1559 I->eraseFromParent();
1560 I = MBB.end();
1561 continue;
1562 }
1563 // TBB is used to indicate the unconditinal destination.
1564 TBB = I->getOperand(0).getMBB();
1565 continue;
1566 }
1567 // Handle conditional branches.
1568 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1569 if (BranchCode == X86::COND_INVALID)
1570 return true; // Can't handle indirect branch.
1571 // Working from the bottom, handle the first conditional branch.
1572 if (Cond.empty()) {
1573 FBB = TBB;
1574 TBB = I->getOperand(0).getMBB();
1575 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1576 continue;
1577 }
1578 // Handle subsequent conditional branches. Only handle the case
1579 // where all conditional branches branch to the same destination
1580 // and their condition opcodes fit one of the special
1581 // multi-branch idioms.
1582 assert(Cond.size() == 1);
1583 assert(TBB);
1584 // Only handle the case where all conditional branches branch to
1585 // the same destination.
1586 if (TBB != I->getOperand(0).getMBB())
1587 return true;
1588 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1589 // If the conditions are the same, we can leave them alone.
1590 if (OldBranchCode == BranchCode)
1591 continue;
1592 // If they differ, see if they fit one of the known patterns.
1593 // Theoretically we could handle more patterns here, but
1594 // we shouldn't expect to see them if instruction selection
1595 // has done a reasonable job.
1596 if ((OldBranchCode == X86::COND_NP &&
1597 BranchCode == X86::COND_E) ||
1598 (OldBranchCode == X86::COND_E &&
1599 BranchCode == X86::COND_NP))
1600 BranchCode = X86::COND_NP_OR_E;
1601 else if ((OldBranchCode == X86::COND_P &&
1602 BranchCode == X86::COND_NE) ||
1603 (OldBranchCode == X86::COND_NE &&
1604 BranchCode == X86::COND_P))
1605 BranchCode = X86::COND_NE_OR_P;
1606 else
1607 return true;
1608 // Update the MachineOperand.
1609 Cond[0].setImm(BranchCode);
1610 }
1611
1612 return false;
1613 }
1614
1615 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1616 MachineBasicBlock::iterator I = MBB.end();
1617 unsigned Count = 0;
1618
1619 while (I != MBB.begin()) {
1620 --I;
1621 if (I->getOpcode() != X86::JMP &&
1622 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1623 break;
1624 // Remove the branch.
1625 I->eraseFromParent();
1626 I = MBB.end();
1627 ++Count;
1628 }
1629
1630 return Count;
1631 }
1632
1633 unsigned
1634 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1635 MachineBasicBlock *FBB,
1636 const SmallVectorImpl<MachineOperand> &Cond) const {
1637 // FIXME this should probably have a DebugLoc operand
1638 DebugLoc dl = DebugLoc::getUnknownLoc();
1639 // Shouldn't be a fall through.
1640 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1641 assert((Cond.size() == 1 || Cond.size() == 0) &&
1642 "X86 branch conditions have one component!");
1643
1644 if (Cond.empty()) {
1645 // Unconditional branch?
1646 assert(!FBB && "Unconditional branch with multiple successors!");
1647 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1648 return 1;
1649 }
1650
1651 // Conditional branch.
1652 unsigned Count = 0;
1653 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1654 switch (CC) {
1655 case X86::COND_NP_OR_E:
1656 // Synthesize NP_OR_E with two branches.
1657 BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1658 ++Count;
1659 BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1660 ++Count;
1661 break;
1662 case X86::COND_NE_OR_P:
1663 // Synthesize NE_OR_P with two branches.
1664 BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1665 ++Count;
1666 BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1667 ++Count;
1668 break;
1669 default: {
1670 unsigned Opc = GetCondBranchFromCond(CC);
1671 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1672 ++Count;
1673 }
1674 }
1675 if (FBB) {
1676 // Two-way Conditional branch. Insert the second branch.
1677 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1678 ++Count;
1679 }
1680 return Count;
1681 }
1682
1683 /// isHReg - Test if the given register is a physical h register.
1684 static bool isHReg(unsigned Reg) {
1685 return X86::GR8_ABCD_HRegClass.contains(Reg);
1686 }
1687
1688 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1689 MachineBasicBlock::iterator MI,
1690 unsigned DestReg, unsigned SrcReg,
1691 const TargetRegisterClass *DestRC,
1692 const TargetRegisterClass *SrcRC) const {
1693 DebugLoc DL = DebugLoc::getUnknownLoc();
1694 if (MI != MBB.end()) DL = MI->getDebugLoc();
1695
1696 // Determine if DstRC and SrcRC have a common superclass in common.
1697 const TargetRegisterClass *CommonRC = DestRC;
1698 if (DestRC == SrcRC)
1699 /* Source and destination have the same register class. */;
1700 else if (CommonRC->hasSuperClass(SrcRC))
1701 CommonRC = SrcRC;
1702 else if (!DestRC->hasSubClass(SrcRC))
1703 CommonRC = 0;
1704
1705 if (CommonRC) {
1706 unsigned Opc;
1707 if (CommonRC == &X86::GR64RegClass) {
1708 Opc = X86::MOV64rr;
1709 } else if (CommonRC == &X86::GR32RegClass) {
1710 Opc = X86::MOV32rr;
1711 } else if (CommonRC == &X86::GR16RegClass) {
1712 Opc = X86::MOV16rr;
1713 } else if (CommonRC == &X86::GR8RegClass) {
1714 // Copying to or from a physical H register on x86-64 requires a NOREX
1715 // move. Otherwise use a normal move.
1716 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1717 TM.getSubtarget<X86Subtarget>().is64Bit())
1718 Opc = X86::MOV8rr_NOREX;
1719 else
1720 Opc = X86::MOV8rr;
1721 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1722 Opc = X86::MOV64rr;
1723 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1724 Opc = X86::MOV32rr;
1725 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1726 Opc = X86::MOV16rr;
1727 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1728 Opc = X86::MOV8rr;
1729 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1730 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1731 Opc = X86::MOV8rr_NOREX;
1732 else
1733 Opc = X86::MOV8rr;
1734 } else if (CommonRC == &X86::GR64_NOREXRegClass) {
1735 Opc = X86::MOV64rr;
1736 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1737 Opc = X86::MOV32rr;
1738 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1739 Opc = X86::MOV16rr;
1740 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1741 Opc = X86::MOV8rr;
1742 } else if (CommonRC == &X86::RFP32RegClass) {
1743 Opc = X86::MOV_Fp3232;
1744 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1745 Opc = X86::MOV_Fp6464;
1746 } else if (CommonRC == &X86::RFP80RegClass) {
1747 Opc = X86::MOV_Fp8080;
1748 } else if (CommonRC == &X86::FR32RegClass) {
1749 Opc = X86::FsMOVAPSrr;
1750 } else if (CommonRC == &X86::FR64RegClass) {
1751 Opc = X86::FsMOVAPDrr;
1752 } else if (CommonRC == &X86::VR128RegClass) {
1753 Opc = X86::MOVAPSrr;
1754 } else if (CommonRC == &X86::VR64RegClass) {
1755 Opc = X86::MMX_MOVQ64rr;
1756 } else {
1757 return false;
1758 }
1759 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1760 return true;
1761 }
1762
1763 // Moving EFLAGS to / from another register requires a push and a pop.
1764 if (SrcRC == &X86::CCRRegClass) {
1765 if (SrcReg != X86::EFLAGS)
1766 return false;
1767 if (DestRC == &X86::GR64RegClass) {
1768 BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1769 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1770 return true;
1771 } else if (DestRC == &X86::GR32RegClass) {
1772 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1773 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1774 return true;
1775 }
1776 } else if (DestRC == &X86::CCRRegClass) {
1777 if (DestReg != X86::EFLAGS)
1778 return false;
1779 if (SrcRC == &X86::GR64RegClass) {
1780 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1781 BuildMI(MBB, MI, DL, get(X86::POPFQ));
1782 return true;
1783 } else if (SrcRC == &X86::GR32RegClass) {
1784 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1785 BuildMI(MBB, MI, DL, get(X86::POPFD));
1786 return true;
1787 }
1788 }
1789
1790 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1791 if (SrcRC == &X86::RSTRegClass) {
1792 // Copying from ST(0)/ST(1).
1793 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1794 // Can only copy from ST(0)/ST(1) right now
1795 return false;
1796 bool isST0 = SrcReg == X86::ST0;
1797 unsigned Opc;
1798 if (DestRC == &X86::RFP32RegClass)
1799 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1800 else if (DestRC == &X86::RFP64RegClass)
1801 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1802 else {
1803 if (DestRC != &X86::RFP80RegClass)
1804 return false;
1805 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1806 }
1807 BuildMI(MBB, MI, DL, get(Opc), DestReg);
1808 return true;
1809 }
1810
1811 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1812 if (DestRC == &X86::RSTRegClass) {
1813 // Copying to ST(0) / ST(1).
1814 if (DestReg != X86::ST0 && DestReg != X86::ST1)
1815 // Can only copy to TOS right now
1816 return false;
1817 bool isST0 = DestReg == X86::ST0;
1818 unsigned Opc;
1819 if (SrcRC == &X86::RFP32RegClass)
1820 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1821 else if (SrcRC == &X86::RFP64RegClass)
1822 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1823 else {
1824 if (SrcRC != &X86::RFP80RegClass)
1825 return false;
1826 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1827 }
1828 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1829 return true;
1830 }
1831
1832 // Not yet supported!
1833 return false;
1834 }
1835
1836 static unsigned getStoreRegOpcode(unsigned SrcReg,
1837 const TargetRegisterClass *RC,
1838 bool isStackAligned,
1839 TargetMachine &TM) {
1840 unsigned Opc = 0;
1841 if (RC == &X86::GR64RegClass) {
1842 Opc = X86::MOV64mr;
1843 } else if (RC == &X86::GR32RegClass) {
1844 Opc = X86::MOV32mr;
1845 } else if (RC == &X86::GR16RegClass) {
1846 Opc = X86::MOV16mr;
1847 } else if (RC == &X86::GR8RegClass) {
1848 // Copying to or from a physical H register on x86-64 requires a NOREX
1849 // move. Otherwise use a normal move.
1850 if (isHReg(SrcReg) &&
1851 TM.getSubtarget<X86Subtarget>().is64Bit())
1852 Opc = X86::MOV8mr_NOREX;
1853 else
1854 Opc = X86::MOV8mr;
1855 } else if (RC == &X86::GR64_ABCDRegClass) {
1856 Opc = X86::MOV64mr;
1857 } else if (RC == &X86::GR32_ABCDRegClass) {
1858 Opc = X86::MOV32mr;
1859 } else if (RC == &X86::GR16_ABCDRegClass) {
1860 Opc = X86::MOV16mr;
1861 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1862 Opc = X86::MOV8mr;
1863 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1864 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1865 Opc = X86::MOV8mr_NOREX;
1866 else
1867 Opc = X86::MOV8mr;
1868 } else if (RC == &X86::GR64_NOREXRegClass) {
1869 Opc = X86::MOV64mr;
1870 } else if (RC == &X86::GR32_NOREXRegClass) {
1871 Opc = X86::MOV32mr;
1872 } else if (RC == &X86::GR16_NOREXRegClass) {
1873 Opc = X86::MOV16mr;
1874 } else if (RC == &X86::GR8_NOREXRegClass) {
1875 Opc = X86::MOV8mr;
1876 } else if (RC == &X86::RFP80RegClass) {
1877 Opc = X86::ST_FpP80m; // pops
1878 } else if (RC == &X86::RFP64RegClass) {
1879 Opc = X86::ST_Fp64m;
1880 } else if (RC == &X86::RFP32RegClass) {
1881 Opc = X86::ST_Fp32m;
1882 } else if (RC == &X86::FR32RegClass) {
1883 Opc = X86::MOVSSmr;
1884 } else if (RC == &X86::FR64RegClass) {
1885 Opc = X86::MOVSDmr;
1886 } else if (RC == &X86::VR128RegClass) {
1887 // If stack is realigned we can use aligned stores.
1888 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1889 } else if (RC == &X86::VR64RegClass) {
1890 Opc = X86::MMX_MOVQ64mr;
1891 } else {
1892 llvm_unreachable("Unknown regclass");
1893 }
1894
1895 return Opc;
1896 }
1897
1898 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1899 MachineBasicBlock::iterator MI,
1900 unsigned SrcReg, bool isKill, int FrameIdx,
1901 const TargetRegisterClass *RC) const {
1902 const MachineFunction &MF = *MBB.getParent();
1903 bool isAligned = (RI.getStackAlignment() >= 16) ||
1904 RI.needsStackRealignment(MF);
1905 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1906 DebugLoc DL = DebugLoc::getUnknownLoc();
1907 if (MI != MBB.end()) DL = MI->getDebugLoc();
1908 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1909 .addReg(SrcReg, getKillRegState(isKill));
1910 }
1911
1912 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1913 bool isKill,
1914 SmallVectorImpl<MachineOperand> &Addr,
1915 const TargetRegisterClass *RC,
1916 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1917 bool isAligned = (RI.getStackAlignment() >= 16) ||
1918 RI.needsStackRealignment(MF);
1919 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1920 DebugLoc DL = DebugLoc::getUnknownLoc();
1921 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1922 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1923 MIB.addOperand(Addr[i]);
1924 MIB.addReg(SrcReg, getKillRegState(isKill));
1925 NewMIs.push_back(MIB);
1926 }
1927
1928 static unsigned getLoadRegOpcode(unsigned DestReg,
1929 const TargetRegisterClass *RC,
1930 bool isStackAligned,
1931 const TargetMachine &TM) {
1932 unsigned Opc = 0;
1933 if (RC == &X86::GR64RegClass) {
1934 Opc = X86::MOV64rm;
1935 } else if (RC == &X86::GR32RegClass) {
1936 Opc = X86::MOV32rm;
1937 } else if (RC == &X86::GR16RegClass) {
1938 Opc = X86::MOV16rm;
1939 } else if (RC == &X86::GR8RegClass) {
1940 // Copying to or from a physical H register on x86-64 requires a NOREX
1941 // move. Otherwise use a normal move.
1942 if (isHReg(DestReg) &&
1943 TM.getSubtarget<X86Subtarget>().is64Bit())
1944 Opc = X86::MOV8rm_NOREX;
1945 else
1946 Opc = X86::MOV8rm;
1947 } else if (RC == &X86::GR64_ABCDRegClass) {
1948 Opc = X86::MOV64rm;
1949 } else if (RC == &X86::GR32_ABCDRegClass) {
1950 Opc = X86::MOV32rm;
1951 } else if (RC == &X86::GR16_ABCDRegClass) {
1952 Opc = X86::MOV16rm;
1953 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1954 Opc = X86::MOV8rm;
1955 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1956 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1957 Opc = X86::MOV8rm_NOREX;
1958 else
1959 Opc = X86::MOV8rm;
1960 } else if (RC == &X86::GR64_NOREXRegClass) {
1961 Opc = X86::MOV64rm;
1962 } else if (RC == &X86::GR32_NOREXRegClass) {
1963 Opc = X86::MOV32rm;
1964 } else if (RC == &X86::GR16_NOREXRegClass) {
1965 Opc = X86::MOV16rm;
1966 } else if (RC == &X86::GR8_NOREXRegClass) {
1967 Opc = X86::MOV8rm;
1968 } else if (RC == &X86::RFP80RegClass) {
1969 Opc = X86::LD_Fp80m;
1970 } else if (RC == &X86::RFP64RegClass) {
1971 Opc = X86::LD_Fp64m;
1972 } else if (RC == &X86::RFP32RegClass) {
1973 Opc = X86::LD_Fp32m;
1974 } else if (RC == &X86::FR32RegClass) {
1975 Opc = X86::MOVSSrm;
1976 } else if (RC == &X86::FR64RegClass) {
1977 Opc = X86::MOVSDrm;
1978 } else if (RC == &X86::VR128RegClass) {
1979 // If stack is realigned we can use aligned loads.
1980 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1981 } else if (RC == &X86::VR64RegClass) {
1982 Opc = X86::MMX_MOVQ64rm;
1983 } else {
1984 llvm_unreachable("Unknown regclass");
1985 }
1986
1987 return Opc;
1988 }
1989
1990 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1991 MachineBasicBlock::iterator MI,
1992 unsigned DestReg, int FrameIdx,
1993 const TargetRegisterClass *RC) const{
1994 const MachineFunction &MF = *MBB.getParent();
1995 bool isAligned = (RI.getStackAlignment() >= 16) ||
1996 RI.needsStackRealignment(MF);
1997 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
1998 DebugLoc DL = DebugLoc::getUnknownLoc();
1999 if (MI != MBB.end()) DL = MI->getDebugLoc();
2000 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2001 }
2002
2003 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2004 SmallVectorImpl<MachineOperand> &Addr,
2005 const TargetRegisterClass *RC,
2006 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2007 bool isAligned = (RI.getStackAlignment() >= 16) ||
2008 RI.needsStackRealignment(MF);
2009 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2010 DebugLoc DL = DebugLoc::getUnknownLoc();
2011 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2012 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2013 MIB.addOperand(Addr[i]);
2014 NewMIs.push_back(MIB);
2015 }
2016
2017 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2018 MachineBasicBlock::iterator MI,
2019 const std::vector<CalleeSavedInfo> &CSI) const {
2020 if (CSI.empty())
2021 return false;
2022
2023 DebugLoc DL = DebugLoc::getUnknownLoc();
2024 if (MI != MBB.end()) DL = MI->getDebugLoc();
2025
2026 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2027 unsigned SlotSize = is64Bit ? 8 : 4;
2028
2029 MachineFunction &MF = *MBB.getParent();
2030 unsigned FPReg = RI.getFrameRegister(MF);
2031 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2032 unsigned CalleeFrameSize = 0;
2033
2034 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2035 for (unsigned i = CSI.size(); i != 0; --i) {
2036 unsigned Reg = CSI[i-1].getReg();
2037 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2038 // Add the callee-saved register as live-in. It's killed at the spill.
2039 MBB.addLiveIn(Reg);
2040 if (Reg == FPReg)
2041 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2042 continue;
2043 if (RegClass != &X86::VR128RegClass) {
2044 CalleeFrameSize += SlotSize;
2045 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2046 } else {
2047 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2048 }
2049 }
2050
2051 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2052 return true;
2053 }
2054
2055 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2056 MachineBasicBlock::iterator MI,
2057 const std::vector<CalleeSavedInfo> &CSI) const {
2058 if (CSI.empty())
2059 return false;
2060
2061 DebugLoc DL = DebugLoc::getUnknownLoc();
2062 if (MI != MBB.end()) DL = MI->getDebugLoc();
2063
2064 MachineFunction &MF = *MBB.getParent();
2065 unsigned FPReg = RI.getFrameRegister(MF);
2066 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2067 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2068 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2069 unsigned Reg = CSI[i].getReg();
2070 if (Reg == FPReg)
2071 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2072 continue;
2073 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2074 if (RegClass != &X86::VR128RegClass) {
2075 BuildMI(MBB, MI, DL, get(Opc), Reg);
2076 } else {
2077 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2078 }
2079 }
2080 return true;
2081 }
2082
2083 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2084 const SmallVectorImpl<MachineOperand> &MOs,
2085 MachineInstr *MI,
2086 const TargetInstrInfo &TII) {
2087 // Create the base instruction with the memory operand as the first part.
2088 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2089 MI->getDebugLoc(), true);
2090 MachineInstrBuilder MIB(NewMI);
2091 unsigned NumAddrOps = MOs.size();
2092 for (unsigned i = 0; i != NumAddrOps; ++i)
2093 MIB.addOperand(MOs[i]);
2094 if (NumAddrOps < 4) // FrameIndex only
2095 addOffset(MIB, 0);
2096
2097 // Loop over the rest of the ri operands, converting them over.
2098 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2099 for (unsigned i = 0; i != NumOps; ++i) {
2100 MachineOperand &MO = MI->getOperand(i+2);
2101 MIB.addOperand(MO);
2102 }
2103 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2104 MachineOperand &MO = MI->getOperand(i);
2105 MIB.addOperand(MO);
2106 }
2107 return MIB;
2108 }
2109
2110 static MachineInstr *FuseInst(MachineFunction &MF,
2111 unsigned Opcode, unsigned OpNo,
2112 const SmallVectorImpl<MachineOperand> &MOs,
2113 MachineInstr *MI, const TargetInstrInfo &TII) {
2114 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2115 MI->getDebugLoc(), true);
2116 MachineInstrBuilder MIB(NewMI);
2117
2118 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2119 MachineOperand &MO = MI->getOperand(i);
2120 if (i == OpNo) {
2121 assert(MO.isReg() && "Expected to fold into reg operand!");
2122 unsigned NumAddrOps = MOs.size();
2123 for (unsigned i = 0; i != NumAddrOps; ++i)
2124 MIB.addOperand(MOs[i]);
2125 if (NumAddrOps < 4) // FrameIndex only
2126 addOffset(MIB, 0);
2127 } else {
2128 MIB.addOperand(MO);
2129 }
2130 }
2131 return MIB;
2132 }
2133
2134 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2135 const SmallVectorImpl<MachineOperand> &MOs,
2136 MachineInstr *MI) {
2137 MachineFunction &MF = *MI->getParent()->getParent();
2138 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2139
2140 unsigned NumAddrOps = MOs.size();
2141 for (unsigned i = 0; i != NumAddrOps; ++i)
2142 MIB.addOperand(MOs[i]);
2143 if (NumAddrOps < 4) // FrameIndex only
2144 addOffset(MIB, 0);
2145 return MIB.addImm(0);
2146 }
2147
2148 MachineInstr*
2149 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2150 MachineInstr *MI, unsigned i,
2151 const SmallVectorImpl<MachineOperand> &MOs,
2152 unsigned Align) const {
2153 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2154 bool isTwoAddrFold = false;
2155 unsigned NumOps = MI->getDesc().getNumOperands();
2156 bool isTwoAddr = NumOps > 1 &&
2157 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2158
2159 MachineInstr *NewMI = NULL;
2160 // Folding a memory location into the two-address part of a two-address
2161 // instruction is different than folding it other places. It requires
2162 // replacing the *two* registers with the memory location.
2163 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2164 MI->getOperand(0).isReg() &&
2165 MI->getOperand(1).isReg() &&
2166 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2167 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2168 isTwoAddrFold = true;
2169 } else if (i == 0) { // If operand 0
2170 if (MI->getOpcode() == X86::MOV16r0)
2171 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2172 else if (MI->getOpcode() == X86::MOV32r0)
2173 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2174 else if (MI->getOpcode() == X86::MOV8r0)
2175 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2176 if (NewMI)
2177 return NewMI;
2178
2179 OpcodeTablePtr = &RegOp2MemOpTable0;
2180 } else if (i == 1) {
2181 OpcodeTablePtr = &RegOp2MemOpTable1;
2182 } else if (i == 2) {
2183 OpcodeTablePtr = &RegOp2MemOpTable2;
2184 }
2185
2186 // If table selected...
2187 if (OpcodeTablePtr) {
2188 // Find the Opcode to fuse
2189 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2190 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2191 if (I != OpcodeTablePtr->end()) {
2192 unsigned MinAlign = I->second.second;
2193 if (Align < MinAlign)
2194 return NULL;
2195 if (isTwoAddrFold)
2196 NewMI = FuseTwoAddrInst(MF, I->second.first, MOs, MI, *this);
2197 else
2198 NewMI = FuseInst(MF, I->second.first, i, MOs, MI, *this);
2199 return NewMI;
2200 }
2201 }
2202
2203 // No fusion
2204 if (PrintFailedFusing)
2205 cerr << "We failed to fuse operand " << i << " in " << *MI;
2206 return NULL;
2207 }
2208
2209
2210 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2211 MachineInstr *MI,
2212 const SmallVectorImpl<unsigned> &Ops,
2213 int FrameIndex) const {
2214 // Check switch flag
2215 if (NoFusing) return NULL;
2216
2217 const MachineFrameInfo *MFI = MF.getFrameInfo();
2218 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2219 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2220 unsigned NewOpc = 0;
2221 switch (MI->getOpcode()) {
2222 default: return NULL;
2223 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2224 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2225 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2226 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2227 }
2228 // Change to CMPXXri r, 0 first.
2229 MI->setDesc(get(NewOpc));
2230 MI->getOperand(1).ChangeToImmediate(0);
2231 } else if (Ops.size() != 1)
2232 return NULL;
2233
2234 SmallVector<MachineOperand,4> MOs;
2235 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2236 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Alignment);
2237 }
2238
2239 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2240 MachineInstr *MI,
2241 const SmallVectorImpl<unsigned> &Ops,
2242 MachineInstr *LoadMI) const {
2243 // Check switch flag
2244 if (NoFusing) return NULL;
2245
2246 // Determine the alignment of the load.
2247 unsigned Alignment = 0;
2248 if (LoadMI->hasOneMemOperand())
2249 Alignment = LoadMI->memoperands_begin()->getAlignment();
2250 else if (LoadMI->getOpcode() == X86::V_SET0 ||
2251 LoadMI->getOpcode() == X86::V_SETALLONES)
2252 Alignment = 16;
2253 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2254 unsigned NewOpc = 0;
2255 switch (MI->getOpcode()) {
2256 default: return NULL;
2257 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2258 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2259 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2260 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2261 }
2262 // Change to CMPXXri r, 0 first.
2263 MI->setDesc(get(NewOpc));
2264 MI->getOperand(1).ChangeToImmediate(0);
2265 } else if (Ops.size() != 1)
2266 return NULL;
2267
2268 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2269 if (LoadMI->getOpcode() == X86::V_SET0 ||
2270 LoadMI->getOpcode() == X86::V_SETALLONES) {
2271 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2272 // Create a constant-pool entry and operands to load from it.
2273
2274 // x86-32 PIC requires a PIC base register for constant pools.
2275 unsigned PICBase = 0;
2276 if (TM.getRelocationModel() == Reloc::PIC_ &&
2277 !TM.getSubtarget<X86Subtarget>().is64Bit())
2278 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2279 // This doesn't work for several reasons.
2280 // 1. GlobalBaseReg may have been spilled.
2281 // 2. It may not be live at MI.
2282 return false;
2283
2284 // Create a v4i32 constant-pool entry.
2285 MachineConstantPool &MCP = *MF.getConstantPool();
2286 const VectorType *Ty = VectorType::get(Type::Int32Ty, 4);
2287 Constant *C = LoadMI->getOpcode() == X86::V_SET0 ?
2288 MF.getFunction()->getContext()->getNullValue(Ty) :
2289 MF.getFunction()->getContext()->getAllOnesValue(Ty);
2290 unsigned CPI = MCP.getConstantPoolIndex(C, 16);
2291
2292 // Create operands to load from the constant pool entry.
2293 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2294 MOs.push_back(MachineOperand::CreateImm(1));
2295 MOs.push_back(MachineOperand::CreateReg(0, false));
2296 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2297 MOs.push_back(MachineOperand::CreateReg(0, false));
2298 } else {
2299 // Folding a normal load. Just copy the load's address operands.
2300 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2301 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2302 MOs.push_back(LoadMI->getOperand(i));
2303 }
2304 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Alignment);
2305 }
2306
2307
2308 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2309 const SmallVectorImpl<unsigned> &Ops) const {
2310 // Check switch flag
2311 if (NoFusing) return 0;
2312
2313 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2314 switch (MI->getOpcode()) {
2315 default: return false;
2316 case X86::TEST8rr:
2317 case X86::TEST16rr:
2318 case X86::TEST32rr:
2319 case X86::TEST64rr:
2320 return true;
2321 }
2322 }
2323
2324 if (Ops.size() != 1)
2325 return false;
2326
2327 unsigned OpNum = Ops[0];
2328 unsigned Opc = MI->getOpcode();
2329 unsigned NumOps = MI->getDesc().getNumOperands();
2330 bool isTwoAddr = NumOps > 1 &&
2331 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2332
2333 // Folding a memory location into the two-address part of a two-address
2334 // instruction is different than folding it other places. It requires
2335 // replacing the *two* registers with the memory location.
2336 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2337 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2338 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2339 } else if (OpNum == 0) { // If operand 0
2340 switch (Opc) {
2341 case X86::MOV8r0:
2342 case X86::MOV16r0:
2343 case X86::MOV32r0:
2344 return true;
2345 default: break;
2346 }
2347 OpcodeTablePtr = &RegOp2MemOpTable0;
2348 } else if (OpNum == 1) {
2349 OpcodeTablePtr = &RegOp2MemOpTable1;
2350 } else if (OpNum == 2) {
2351 OpcodeTablePtr = &RegOp2MemOpTable2;
2352 }
2353
2354 if (OpcodeTablePtr) {
2355 // Find the Opcode to fuse
2356 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2357 OpcodeTablePtr->find((unsigned*)Opc);
2358 if (I != OpcodeTablePtr->end())
2359 return true;
2360 }
2361 return false;
2362 }
2363
2364 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2365 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2366 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2367 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2368 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2369 if (I == MemOp2RegOpTable.end())
2370 return false;
2371 DebugLoc dl = MI->getDebugLoc();
2372 unsigned Opc = I->second.first;
2373 unsigned Index = I->second.second & 0xf;
2374 bool FoldedLoad = I->second.second & (1 << 4);
2375 bool FoldedStore = I->second.second & (1 << 5);
2376 if (UnfoldLoad && !FoldedLoad)
2377 return false;
2378 UnfoldLoad &= FoldedLoad;
2379 if (UnfoldStore && !FoldedStore)
2380 return false;
2381 UnfoldStore &= FoldedStore;
2382
2383 const TargetInstrDesc &TID = get(Opc);
2384 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2385 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2386 ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2387 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2388 SmallVector<MachineOperand,2> BeforeOps;
2389 SmallVector<MachineOperand,2> AfterOps;
2390 SmallVector<MachineOperand,4> ImpOps;
2391 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2392 MachineOperand &Op = MI->getOperand(i);
2393 if (i >= Index && i < Index + X86AddrNumOperands)
2394 AddrOps.push_back(Op);
2395 else if (Op.isReg() && Op.isImplicit())
2396 ImpOps.push_back(Op);
2397 else if (i < Index)
2398 BeforeOps.push_back(Op);
2399 else if (i > Index)
2400 AfterOps.push_back(Op);
2401 }
2402
2403 // Emit the load instruction.
2404 if (UnfoldLoad) {
2405 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2406 if (UnfoldStore) {
2407 // Address operands cannot be marked isKill.
2408 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2409 MachineOperand &MO = NewMIs[0]->getOperand(i);
2410 if (MO.isReg())
2411 MO.setIsKill(false);
2412 }
2413 }
2414 }
2415
2416 // Emit the data processing instruction.
2417 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2418 MachineInstrBuilder MIB(DataMI);
2419
2420 if (FoldedStore)
2421 MIB.addReg(Reg, RegState::Define);
2422 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2423 MIB.addOperand(BeforeOps[i]);
2424 if (FoldedLoad)
2425 MIB.addReg(Reg);
2426 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2427 MIB.addOperand(AfterOps[i]);
2428 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2429 MachineOperand &MO = ImpOps[i];
2430 MIB.addReg(MO.getReg(),
2431 getDefRegState(MO.isDef()) |
2432 RegState::Implicit |
2433 getKillRegState(MO.isKill()) |
2434 getDeadRegState(MO.isDead()) |
2435 getUndefRegState(MO.isUndef()));
2436 }
2437 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2438 unsigned NewOpc = 0;
2439 switch (DataMI->getOpcode()) {
2440 default: break;
2441 case X86::CMP64ri32:
2442 case X86::CMP32ri:
2443 case X86::CMP16ri:
2444 case X86::CMP8ri: {
2445 MachineOperand &MO0 = DataMI->getOperand(0);
2446 MachineOperand &MO1 = DataMI->getOperand(1);
2447 if (MO1.getImm() == 0) {
2448 switch (DataMI->getOpcode()) {
2449 default: break;
2450 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2451 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2452 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2453 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2454 }
2455 DataMI->setDesc(get(NewOpc));
2456 MO1.ChangeToRegister(MO0.getReg(), false);
2457 }
2458 }
2459 }
2460 NewMIs.push_back(DataMI);
2461
2462 // Emit the store instruction.
2463 if (UnfoldStore) {
2464 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2465 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
2466 ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2467 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2468 }
2469
2470 return true;
2471 }
2472
2473 bool
2474 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2475 SmallVectorImpl<SDNode*> &NewNodes) const {
2476 if (!N->isMachineOpcode())
2477 return false;
2478
2479 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2480 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2481 if (I == MemOp2RegOpTable.end())
2482 return false;
2483 unsigned Opc = I->second.first;
2484 unsigned Index = I->second.second & 0xf;
2485 bool FoldedLoad = I->second.second & (1 << 4);
2486 bool FoldedStore = I->second.second & (1 << 5);
2487 const TargetInstrDesc &TID = get(Opc);
2488 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2489 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2490 ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2491 unsigned NumDefs = TID.NumDefs;
2492 std::vector<SDValue> AddrOps;
2493 std::vector<SDValue> BeforeOps;
2494 std::vector<SDValue> AfterOps;
2495 DebugLoc dl = N->getDebugLoc();
2496 unsigned NumOps = N->getNumOperands();
2497 for (unsigned i = 0; i != NumOps-1; ++i) {
2498 SDValue Op = N->getOperand(i);
2499 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2500 AddrOps.push_back(Op);
2501 else if (i < Index-NumDefs)
2502 BeforeOps.push_back(Op);
2503 else if (i > Index-NumDefs)
2504 AfterOps.push_back(Op);
2505 }
2506 SDValue Chain = N->getOperand(NumOps-1);
2507 AddrOps.push_back(Chain);
2508
2509 // Emit the load instruction.
2510 SDNode *Load = 0;
2511 const MachineFunction &MF = DAG.getMachineFunction();
2512 if (FoldedLoad) {
2513 MVT VT = *RC->vt_begin();
2514 bool isAligned = (RI.getStackAlignment() >= 16) ||
2515 RI.needsStackRealignment(MF);
2516 Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2517 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2518 NewNodes.push_back(Load);
2519 }
2520
2521 // Emit the data processing instruction.
2522 std::vector<MVT> VTs;
2523 const TargetRegisterClass *DstRC = 0;
2524 if (TID.getNumDefs() > 0) {
2525 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2526 DstRC = DstTOI.isLookupPtrRegClass()
2527 ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2528 VTs.push_back(*DstRC->vt_begin());
2529 }
2530 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2531 MVT VT = N->getValueType(i);
2532 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2533 VTs.push_back(VT);
2534 }
2535 if (Load)
2536 BeforeOps.push_back(SDValue(Load, 0));
2537 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2538 SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0],
2539 BeforeOps.size());
2540 NewNodes.push_back(NewNode);
2541
2542 // Emit the store instruction.
2543 if (FoldedStore) {
2544 AddrOps.pop_back();
2545 AddrOps.push_back(SDValue(NewNode, 0));
2546 AddrOps.push_back(Chain);
2547 bool isAligned = (RI.getStackAlignment() >= 16) ||
2548 RI.needsStackRealignment(MF);
2549 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
2550 isAligned, TM),
2551 dl, MVT::Other,
2552 &AddrOps[0], AddrOps.size());
2553 NewNodes.push_back(Store);
2554 }
2555
2556 return true;
2557 }
2558
2559 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2560 bool UnfoldLoad, bool UnfoldStore) const {
2561 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2562 MemOp2RegOpTable.find((unsigned*)Opc);
2563 if (I == MemOp2RegOpTable.end())
2564 return 0;
2565 bool FoldedLoad = I->second.second & (1 << 4);
2566 bool FoldedStore = I->second.second & (1 << 5);
2567 if (UnfoldLoad && !FoldedLoad)
2568 return 0;
2569 if (UnfoldStore && !FoldedStore)
2570 return 0;
2571 return I->second.first;
2572 }
2573
2574 bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2575 if (MBB.empty()) return false;
2576
2577 switch (MBB.back().getOpcode()) {
2578 case X86::TCRETURNri:
2579 case X86::TCRETURNdi:
2580 case X86::RET: // Return.
2581 case X86::RETI:
2582 case X86::TAILJMPd:
2583 case X86::TAILJMPr:
2584 case X86::TAILJMPm:
2585 case X86::JMP: // Uncond branch.
2586 case X86::JMP32r: // Indirect branch.
2587 case X86::JMP64r: // Indirect branch (64-bit).
2588 case X86::JMP32m: // Indirect branch through mem.
2589 case X86::JMP64m: // Indirect branch through mem (64-bit).
2590 return true;
2591 default: return false;
2592 }
2593 }
2594
2595 bool X86InstrInfo::
2596 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2597 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2598 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2599 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2600 return true;
2601 Cond[0].setImm(GetOppositeBranchCondition(CC));
2602 return false;
2603 }
2604
2605 bool X86InstrInfo::
2606 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2607 // FIXME: Return false for x87 stack register classes for now. We can't
2608 // allow any loads of these registers before FpGet_ST0_80.
2609 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2610 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2611 }
2612
2613 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2614 switch (Desc->TSFlags & X86II::ImmMask) {
2615 case X86II::Imm8: return 1;
2616 case X86II::Imm16: return 2;
2617 case X86II::Imm32: return 4;
2618 case X86II::Imm64: return 8;
2619 default: llvm_unreachable("Immediate size not set!");
2620 return 0;
2621 }
2622 }
2623
2624 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2625 /// e.g. r8, xmm8, etc.
2626 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2627 if (!MO.isReg()) return false;
2628 switch (MO.getReg()) {
2629 default: break;
2630 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2631 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2632 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2633 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2634 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2635 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2636 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2637 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2638 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2639 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2640 return true;
2641 }
2642 return false;
2643 }
2644
2645
2646 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2647 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2648 /// size, and 3) use of X86-64 extended registers.
2649 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2650 unsigned REX = 0;
2651 const TargetInstrDesc &Desc = MI.getDesc();
2652
2653 // Pseudo instructions do not need REX prefix byte.
2654 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2655 return 0;
2656 if (Desc.TSFlags & X86II::REX_W)
2657 REX |= 1 << 3;
2658
2659 unsigned NumOps = Desc.getNumOperands();
2660 if (NumOps) {
2661 bool isTwoAddr = NumOps > 1 &&
2662 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2663
2664 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2665 unsigned i = isTwoAddr ? 1 : 0;
2666 for (unsigned e = NumOps; i != e; ++i) {
2667 const MachineOperand& MO = MI.getOperand(i);
2668 if (MO.isReg()) {
2669 unsigned Reg = MO.getReg();
2670 if (isX86_64NonExtLowByteReg(Reg))
2671 REX |= 0x40;
2672 }
2673 }
2674
2675 switch (Desc.TSFlags & X86II::FormMask) {
2676 case X86II::MRMInitReg:
2677 if (isX86_64ExtendedReg(MI.getOperand(0)))
2678 REX |= (1 << 0) | (1 << 2);
2679 break;
2680 case X86II::MRMSrcReg: {
2681 if (isX86_64ExtendedReg(MI.getOperand(0)))
2682 REX |= 1 << 2;
2683 i = isTwoAddr ? 2 : 1;
2684 for (unsigned e = NumOps; i != e; ++i) {
2685 const MachineOperand& MO = MI.getOperand(i);
2686 if (isX86_64ExtendedReg(MO))
2687 REX |= 1 << 0;
2688 }
2689 break;
2690 }
2691 case X86II::MRMSrcMem: {
2692 if (isX86_64ExtendedReg(MI.getOperand(0)))
2693 REX |= 1 << 2;
2694 unsigned Bit = 0;
2695 i = isTwoAddr ? 2 : 1;
2696 for (; i != NumOps; ++i) {
2697 const MachineOperand& MO = MI.getOperand(i);
2698 if (MO.isReg()) {
2699 if (isX86_64ExtendedReg(MO))
2700 REX |= 1 << Bit;
2701 Bit++;
2702 }
2703 }
2704 break;
2705 }
2706 case X86II::MRM0m: case X86II::MRM1m:
2707 case X86II::MRM2m: case X86II::MRM3m:
2708 case X86II::MRM4m: case X86II::MRM5m:
2709 case X86II::MRM6m: case X86II::MRM7m:
2710 case X86II::MRMDestMem: {
2711 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2712 i = isTwoAddr ? 1 : 0;
2713 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2714 REX |= 1 << 2;
2715 unsigned Bit = 0;
2716 for (; i != e; ++i) {
2717 const MachineOperand& MO = MI.getOperand(i);
2718 if (MO.isReg()) {
2719 if (isX86_64ExtendedReg(MO))
2720 REX |= 1 << Bit;
2721 Bit++;
2722 }
2723 }
2724 break;
2725 }
2726 default: {
2727 if (isX86_64ExtendedReg(MI.getOperand(0)))
2728 REX |= 1 << 0;
2729 i = isTwoAddr ? 2 : 1;
2730 for (unsigned e = NumOps; i != e; ++i) {
2731 const MachineOperand& MO = MI.getOperand(i);
2732 if (isX86_64ExtendedReg(MO))
2733 REX |= 1 << 2;
2734 }
2735 break;
2736 }
2737 }
2738 }
2739 return REX;
2740 }
2741
2742 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2743 /// relative block address instruction
2744 ///
2745 static unsigned sizePCRelativeBlockAddress() {
2746 return 4;
2747 }
2748
2749 /// sizeGlobalAddress - Give the size of the emission of this global address
2750 ///
2751 static unsigned sizeGlobalAddress(bool dword) {
2752 return dword ? 8 : 4;
2753 }
2754
2755 /// sizeConstPoolAddress - Give the size of the emission of this constant
2756 /// pool address
2757 ///
2758 static unsigned sizeConstPoolAddress(bool dword) {
2759 return dword ? 8 : 4;
2760 }
2761
2762 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2763 /// symbol
2764 ///
2765 static unsigned sizeExternalSymbolAddress(bool dword) {
2766 return dword ? 8 : 4;
2767 }
2768
2769 /// sizeJumpTableAddress - Give the size of the emission of this jump
2770 /// table address
2771 ///
2772 static unsigned sizeJumpTableAddress(bool dword) {
2773 return dword ? 8 : 4;
2774 }
2775
2776 static unsigned sizeConstant(unsigned Size) {
2777 return Size;
2778 }
2779
2780 static unsigned sizeRegModRMByte(){
2781 return 1;
2782 }
2783
2784 static unsigned sizeSIBByte(){
2785 return 1;
2786 }
2787
2788 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2789 unsigned FinalSize = 0;
2790 // If this is a simple integer displacement that doesn't require a relocation.
2791 if (!RelocOp) {
2792 FinalSize += sizeConstant(4);
2793 return FinalSize;
2794 }
2795
2796 // Otherwise, this is something that requires a relocation.
2797 if (RelocOp->isGlobal()) {
2798 FinalSize += sizeGlobalAddress(false);
2799 } else if (RelocOp->isCPI()) {
2800 FinalSize += sizeConstPoolAddress(false);
2801 } else if (RelocOp->isJTI()) {
2802 FinalSize += sizeJumpTableAddress(false);
2803 } else {
2804 llvm_unreachable("Unknown value to relocate!");
2805 }
2806 return FinalSize;
2807 }
2808
2809 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2810 bool IsPIC, bool Is64BitMode) {
2811 const MachineOperand &Op3 = MI.getOperand(Op+3);
2812 int DispVal = 0;
2813 const MachineOperand *DispForReloc = 0;
2814 unsigned FinalSize = 0;
2815
2816 // Figure out what sort of displacement we have to handle here.
2817 if (Op3.isGlobal()) {
2818 DispForReloc = &Op3;
2819 } else if (Op3.isCPI()) {
2820 if (Is64BitMode || IsPIC) {
2821 DispForReloc = &Op3;
2822 } else {
2823 DispVal = 1;
2824 }
2825 } else if (Op3.isJTI()) {
2826 if (Is64BitMode || IsPIC) {
2827 DispForReloc = &Op3;
2828 } else {
2829 DispVal = 1;
2830 }
2831 } else {
2832 DispVal = 1;
2833 }
2834
2835 const MachineOperand &Base = MI.getOperand(Op);
2836 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2837
2838 unsigned BaseReg = Base.getReg();
2839
2840 // Is a SIB byte needed?
2841 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
2842 IndexReg.getReg() == 0 &&
2843 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2844 if (BaseReg == 0) { // Just a displacement?
2845 // Emit special case [disp32] encoding
2846 ++FinalSize;
2847 FinalSize += getDisplacementFieldSize(DispForReloc);
2848 } else {
2849 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2850 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2851 // Emit simple indirect register encoding... [EAX] f.e.
2852 ++FinalSize;
2853 // Be pessimistic and assume it's a disp32, not a disp8
2854 } else {
2855 // Emit the most general non-SIB encoding: [REG+disp32]
2856 ++FinalSize;
2857 FinalSize += getDisplacementFieldSize(DispForReloc);
2858 }
2859 }
2860
2861 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
2862 assert(IndexReg.getReg() != X86::ESP &&
2863 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2864
2865 bool ForceDisp32 = false;
2866 if (BaseReg == 0 || DispForReloc) {
2867 // Emit the normal disp32 encoding.
2868 ++FinalSize;
2869 ForceDisp32 = true;
2870 } else {
2871 ++FinalSize;
2872 }
2873
2874 FinalSize += sizeSIBByte();
2875
2876 // Do we need to output a displacement?
2877 if (DispVal != 0 || ForceDisp32) {
2878 FinalSize += getDisplacementFieldSize(DispForReloc);
2879 }
2880 }
2881 return FinalSize;
2882 }
2883
2884
2885 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2886 const TargetInstrDesc *Desc,
2887 bool IsPIC, bool Is64BitMode) {
2888
2889 unsigned Opcode = Desc->Opcode;
2890 unsigned FinalSize = 0;
2891
2892 // Emit the lock opcode prefix as needed.
2893 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2894
2895 // Emit segment override opcode prefix as needed.
2896 switch (Desc->TSFlags & X86II::SegOvrMask) {
2897 case X86II::FS:
2898 case X86II::GS:
2899 ++FinalSize;
2900 break;
2901 default: llvm_unreachable("Invalid segment!");
2902 case 0: break; // No segment override!
2903 }
2904
2905 // Emit the repeat opcode prefix as needed.
2906 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2907
2908 // Emit the operand size opcode prefix as needed.
2909 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2910
2911 // Emit the address size opcode prefix as needed.
2912 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2913
2914 bool Need0FPrefix = false;
2915 switch (Desc->TSFlags & X86II::Op0Mask) {
2916 case X86II::TB: // Two-byte opcode prefix
2917 case X86II::T8: // 0F 38
2918 case X86II::TA: // 0F 3A
2919 Need0FPrefix = true;
2920 break;
2921 case X86II::REP: break; // already handled.
2922 case X86II::XS: // F3 0F
2923 ++FinalSize;
2924 Need0FPrefix = true;
2925 break;
2926 case X86II::XD: // F2 0F
2927 ++FinalSize;
2928 Need0FPrefix = true;
2929 break;
2930 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2931 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2932 ++FinalSize;
2933 break; // Two-byte opcode prefix
2934 default: llvm_unreachable("Invalid prefix!");
2935 case 0: break; // No prefix!
2936 }
2937
2938 if (Is64BitMode) {
2939 // REX prefix
2940 unsigned REX = X86InstrInfo::determineREX(MI);
2941 if (REX)
2942 ++FinalSize;
2943 }
2944
2945 // 0x0F escape code must be emitted just before the opcode.
2946 if (Need0FPrefix)
2947 ++FinalSize;
2948
2949 switch (Desc->TSFlags & X86II::Op0Mask) {
2950 case X86II::T8: // 0F 38
2951 ++FinalSize;
2952 break;
2953 case X86II::TA: // 0F 3A
2954 ++FinalSize;
2955 break;
2956 }
2957
2958 // If this is a two-address instruction, skip one of the register operands.
2959 unsigned NumOps = Desc->getNumOperands();
2960 unsigned CurOp = 0;
2961 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
2962 CurOp++;
2963 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
2964 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
2965 --NumOps;
2966
2967 switch (Desc->TSFlags & X86II::FormMask) {
2968 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
2969 case X86II::Pseudo:
2970 // Remember the current PC offset, this is the PIC relocation
2971 // base address.
2972 switch (Opcode) {
2973 default:
2974 break;
2975 case TargetInstrInfo::INLINEASM: {
2976 const MachineFunction *MF = MI.getParent()->getParent();
2977 const char *AsmStr = MI.getOperand(0).getSymbolName();
2978 const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo();
2979 FinalSize += AI->getInlineAsmLength(AsmStr);
2980 break;
2981 }
2982 case TargetInstrInfo::DBG_LABEL:
2983 case TargetInstrInfo::EH_LABEL:
2984 break;
2985 case TargetInstrInfo::IMPLICIT_DEF:
2986 case TargetInstrInfo::DECLARE:
2987 case X86::DWARF_LOC:
2988 case X86::FP_REG_KILL:
2989 break;
2990 case X86::MOVPC32r: {
2991 // This emits the "call" portion of this pseudo instruction.
2992 ++FinalSize;
2993 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2994 break;
2995 }
2996 }
2997 CurOp = NumOps;
2998 break;
2999 case X86II::RawFrm:
3000 ++FinalSize;
3001
3002 if (CurOp != NumOps) {
3003 const MachineOperand &MO = MI.getOperand(CurOp++);
3004 if (MO.isMBB()) {
3005 FinalSize += sizePCRelativeBlockAddress();
3006 } else if (MO.isGlobal()) {
3007 FinalSize += sizeGlobalAddress(false);
3008 } else if (MO.isSymbol()) {
3009 FinalSize += sizeExternalSymbolAddress(false);
3010 } else if (MO.isImm()) {
3011 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3012 } else {
3013 llvm_unreachable("Unknown RawFrm operand!");
3014 }
3015 }
3016 break;
3017
3018 case X86II::AddRegFrm:
3019 ++FinalSize;
3020 ++CurOp;
3021
3022 if (CurOp != NumOps) {
3023 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3024 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3025 if (MO1.isImm())
3026 FinalSize += sizeConstant(Size);
3027 else {
3028 bool dword = false;
3029 if (Opcode == X86::MOV64ri)
3030 dword = true;
3031 if (MO1.isGlobal()) {
3032 FinalSize += sizeGlobalAddress(dword);
3033 } else if (MO1.isSymbol())
3034 FinalSize += sizeExternalSymbolAddress(dword);
3035 else if (MO1.isCPI())
3036 FinalSize += sizeConstPoolAddress(dword);
3037 else if (MO1.isJTI())
3038 FinalSize += sizeJumpTableAddress(dword);
3039 }
3040 }
3041 break;
3042
3043 case X86II::MRMDestReg: {
3044 ++FinalSize;
3045 FinalSize += sizeRegModRMByte();
3046 CurOp += 2;
3047 if (CurOp != NumOps) {
3048 ++CurOp;
3049 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3050 }
3051 break;
3052 }
3053 case X86II::MRMDestMem: {
3054 ++FinalSize;
3055 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3056 CurOp += X86AddrNumOperands + 1;
3057 if (CurOp != NumOps) {
3058 ++CurOp;
3059 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3060 }
3061 break;
3062 }
3063
3064 case X86II::MRMSrcReg:
3065 ++FinalSize;
3066 FinalSize += sizeRegModRMByte();
3067 CurOp += 2;
3068 if (CurOp != NumOps) {
3069 ++CurOp;
3070 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3071 }
3072 break;
3073
3074 case X86II::MRMSrcMem: {
3075 int AddrOperands;
3076 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3077 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3078 AddrOperands = X86AddrNumOperands - 1; // No segment register
3079 else
3080 AddrOperands = X86AddrNumOperands;
3081
3082 ++FinalSize;
3083 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3084 CurOp += AddrOperands + 1;
3085 if (CurOp != NumOps) {
3086 ++CurOp;
3087 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3088 }
3089 break;
3090 }
3091
3092 case X86II::MRM0r: case X86II::MRM1r:
3093 case X86II::MRM2r: case X86II::MRM3r:
3094 case X86II::MRM4r: case X86II::MRM5r:
3095 case X86II::MRM6r: case X86II::MRM7r:
3096 ++FinalSize;
3097 if (Desc->getOpcode() == X86::LFENCE ||
3098 Desc->getOpcode() == X86::MFENCE) {
3099 // Special handling of lfence and mfence;
3100 FinalSize += sizeRegModRMByte();
3101 } else if (Desc->getOpcode() == X86::MONITOR ||
3102 Desc->getOpcode() == X86::MWAIT) {
3103 // Special handling of monitor and mwait.
3104 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3105 } else {
3106 ++CurOp;
3107 FinalSize += sizeRegModRMByte();
3108 }
3109
3110 if (CurOp != NumOps) {
3111 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3112 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3113 if (MO1.isImm())
3114 FinalSize += sizeConstant(Size);
3115 else {
3116 bool dword = false;
3117 if (Opcode == X86::MOV64ri32)
3118 dword = true;
3119 if (MO1.isGlobal()) {
3120 FinalSize += sizeGlobalAddress(dword);
3121 } else if (MO1.isSymbol())
3122 FinalSize += sizeExternalSymbolAddress(dword);
3123 else if (MO1.isCPI())
3124 FinalSize += sizeConstPoolAddress(dword);
3125 else if (MO1.isJTI())
3126 FinalSize += sizeJumpTableAddress(dword);
3127 }
3128 }
3129 break;
3130
3131 case X86II::MRM0m: case X86II::MRM1m:
3132 case X86II::MRM2m: case X86II::MRM3m:
3133 case X86II::MRM4m: case X86II::MRM5m:
3134 case X86II::MRM6m: case X86II::MRM7m: {
3135
3136 ++FinalSize;
3137 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3138 CurOp += X86AddrNumOperands;
3139
3140 if (CurOp != NumOps) {
3141 const MachineOperand &MO = MI.getOperand(CurOp++);
3142 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3143 if (MO.isImm())
3144 FinalSize += sizeConstant(Size);
3145 else {
3146 bool dword = false;
3147 if (Opcode == X86::MOV64mi32)
3148 dword = true;
3149 if (MO.isGlobal()) {
3150 FinalSize += sizeGlobalAddress(dword);
3151 } else if (MO.isSymbol())
3152 FinalSize += sizeExternalSymbolAddress(dword);
3153 else if (MO.isCPI())
3154 FinalSize += sizeConstPoolAddress(dword);
3155 else if (MO.isJTI())
3156 FinalSize += sizeJumpTableAddress(dword);
3157 }
3158 }
3159 break;
3160 }
3161
3162 case X86II::MRMInitReg:
3163 ++FinalSize;
3164 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3165 FinalSize += sizeRegModRMByte();
3166 ++CurOp;
3167 break;
3168 }
3169
3170 if (!Desc->isVariadic() && CurOp != NumOps) {
3171 std::string msg;
3172 raw_string_ostream Msg(msg);
3173 Msg << "Cannot determine size: " << MI;
3174 llvm_report_error(Msg.str());
3175 }
3176
3177
3178 return FinalSize;
3179 }
3180
3181
3182 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3183 const TargetInstrDesc &Desc = MI->getDesc();
3184 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3185 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3186 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3187 if (Desc.getOpcode() == X86::MOVPC32r)
3188 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3189 return Size;
3190 }
3191
3192 /// getGlobalBaseReg - Return a virtual register initialized with the
3193 /// the global base register value. Output instructions required to
3194 /// initialize the register in the function entry block, if necessary.
3195 ///
3196 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3197 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3198 "X86-64 PIC uses RIP relative addressing");
3199
3200 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3201 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3202 if (GlobalBaseReg != 0)
3203 return GlobalBaseReg;
3204
3205 // Insert the set of GlobalBaseReg into the first MBB of the function
3206 MachineBasicBlock &FirstMBB = MF->front();
3207 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3208 DebugLoc DL = DebugLoc::getUnknownLoc();
3209 if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3210 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3211 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3212
3213 const TargetInstrInfo *TII = TM.getInstrInfo();
3214 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3215 // only used in JIT code emission as displacement to pc.
3216 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3217
3218 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3219 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3220 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3221 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3222 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3223 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3224 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 0,
3225 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3226 } else {
3227 GlobalBaseReg = PC;
3228 }
3229
3230 X86FI->setGlobalBaseReg(GlobalBaseReg);
3231 return GlobalBaseReg;
3232 }
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