lib/Target/X86/X86RegisterInfo.cpp

   1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the X86 implementation of the TargetRegisterInfo class.
  11 // This file is responsible for the frame pointer elimination optimization
  12 // on X86.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "X86.h"
  17 #include "X86RegisterInfo.h"
  18 #include "X86InstrBuilder.h"
  19 #include "X86MachineFunctionInfo.h"
  20 #include "X86Subtarget.h"
  21 #include "X86TargetMachine.h"
  22 #include "llvm/Constants.h"
  23 #include "llvm/Function.h"
  24 #include "llvm/Type.h"
  25 #include "llvm/CodeGen/ValueTypes.h"
  26 #include "llvm/CodeGen/MachineInstrBuilder.h"
  27 #include "llvm/CodeGen/MachineFunction.h"
  28 #include "llvm/CodeGen/MachineFunctionPass.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/CodeGen/MachineLocation.h"
  31 #include "llvm/CodeGen/MachineModuleInfo.h"
  32 #include "llvm/CodeGen/MachineRegisterInfo.h"
  33 #include "llvm/Target/TargetAsmInfo.h"
  34 #include "llvm/Target/TargetFrameInfo.h"
  35 #include "llvm/Target/TargetInstrInfo.h"
  36 #include "llvm/Target/TargetMachine.h"
  37 #include "llvm/Target/TargetOptions.h"
  38 #include "llvm/ADT/BitVector.h"
  39 #include "llvm/ADT/STLExtras.h"
  40 #include "llvm/Support/Compiler.h"
  41 #include "llvm/Support/ErrorHandling.h"
  42 using namespace llvm;
  43
  44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
  45                                  const TargetInstrInfo &tii)
  46   : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
  47                          X86::ADJCALLSTACKDOWN64 :
  48                          X86::ADJCALLSTACKDOWN32,
  49                        tm.getSubtarget<X86Subtarget>().is64Bit() ?
  50                          X86::ADJCALLSTACKUP64 :
  51                          X86::ADJCALLSTACKUP32),
  52     TM(tm), TII(tii) {
  53   // Cache some information.
  54   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
  55   Is64Bit = Subtarget->is64Bit();
  56   IsWin64 = Subtarget->isTargetWin64();
  57   StackAlign = TM.getFrameInfo()->getStackAlignment();
  58   if (Is64Bit) {
  59     SlotSize = 8;
  60     StackPtr = X86::RSP;
  61     FramePtr = X86::RBP;
  62   } else {
  63     SlotSize = 4;
  64     StackPtr = X86::ESP;
  65     FramePtr = X86::EBP;
  66   }
  67 }
  68
  69 // getDwarfRegNum - This function maps LLVM register identifiers to the
  70 // Dwarf specific numbering, used in debug info and exception tables.
  71
  72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
  73   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
  74   unsigned Flavour = DWARFFlavour::X86_64;
  75   if (!Subtarget->is64Bit()) {
  76     if (Subtarget->isTargetDarwin()) {
  77       if (isEH)
  78         Flavour = DWARFFlavour::X86_32_DarwinEH;
  79       else
  80         Flavour = DWARFFlavour::X86_32_Generic;
  81     } else if (Subtarget->isTargetCygMing()) {
  82       // Unsupported by now, just quick fallback
  83       Flavour = DWARFFlavour::X86_32_Generic;
  84     } else {
  85       Flavour = DWARFFlavour::X86_32_Generic;
  86     }
  87   }
  88
  89   return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
  90 }
  91
  92 // getX86RegNum - This function maps LLVM register identifiers to their X86
  93 // specific numbering, which is used in various places encoding instructions.
  94 //
  95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
  96   switch(RegNo) {
  97   case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
  98   case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
  99   case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
 100   case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
 101   case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
 102     return N86::ESP;
 103   case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
 104     return N86::EBP;
 105   case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
 106     return N86::ESI;
 107   case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
 108     return N86::EDI;
 109
 110   case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
 111     return N86::EAX;
 112   case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
 113     return N86::ECX;
 114   case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
 115     return N86::EDX;
 116   case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
 117     return N86::EBX;
 118   case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
 119     return N86::ESP;
 120   case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
 121     return N86::EBP;
 122   case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
 123     return N86::ESI;
 124   case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
 125     return N86::EDI;
 126
 127   case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
 128   case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
 129     return RegNo-X86::ST0;
 130
 131   case X86::XMM0: case X86::XMM8: case X86::MM0:
 132     return 0;
 133   case X86::XMM1: case X86::XMM9: case X86::MM1:
 134     return 1;
 135   case X86::XMM2: case X86::XMM10: case X86::MM2:
 136     return 2;
 137   case X86::XMM3: case X86::XMM11: case X86::MM3:
 138     return 3;
 139   case X86::XMM4: case X86::XMM12: case X86::MM4:
 140     return 4;
 141   case X86::XMM5: case X86::XMM13: case X86::MM5:
 142     return 5;
 143   case X86::XMM6: case X86::XMM14: case X86::MM6:
 144     return 6;
 145   case X86::XMM7: case X86::XMM15: case X86::MM7:
 146     return 7;
 147
 148   default:
 149     assert(isVirtualRegister(RegNo) && "Unknown physical register!");
 150     llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
 151     return 0;
 152   }
 153 }
 154
 155 const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
 156   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
 157   if (Subtarget->is64Bit())
 158     return &X86::GR64RegClass;
 159   else
 160     return &X86::GR32RegClass;
 161 }
 162
 163 const TargetRegisterClass *
 164 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
 165   if (RC == &X86::CCRRegClass) {
 166     if (Is64Bit)
 167       return &X86::GR64RegClass;
 168     else
 169       return &X86::GR32RegClass;
 170   }
 171   return NULL;
 172 }
 173
 174 const unsigned *
 175 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
 176   bool callsEHReturn = false;
 177
 178   if (MF) {
 179     const MachineFrameInfo *MFI = MF->getFrameInfo();
 180     const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 181     callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
 182   }
 183
 184   static const unsigned CalleeSavedRegs32Bit[] = {
 185     X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
 186   };
 187
 188   static const unsigned CalleeSavedRegs32EHRet[] = {
 189     X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
 190   };
 191
 192   static const unsigned CalleeSavedRegs64Bit[] = {
 193     X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
 194   };
 195
 196   static const unsigned CalleeSavedRegs64EHRet[] = {
 197     X86::RAX, X86::RDX, X86::RBX, X86::R12,
 198     X86::R13, X86::R14, X86::R15, X86::RBP, 0
 199   };
 200
 201   static const unsigned CalleeSavedRegsWin64[] = {
 202     X86::RBX,   X86::RBP,   X86::RDI,   X86::RSI,
 203     X86::R12,   X86::R13,   X86::R14,   X86::R15,
 204     X86::XMM6,  X86::XMM7,  X86::XMM8,  X86::XMM9,
 205     X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
 206     X86::XMM14, X86::XMM15, 0
 207   };
 208
 209   if (Is64Bit) {
 210     if (IsWin64)
 211       return CalleeSavedRegsWin64;
 212     else
 213       return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
 214   } else {
 215     return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
 216   }
 217 }
 218
 219 const TargetRegisterClass* const*
 220 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
 221   bool callsEHReturn = false;
 222
 223   if (MF) {
 224     const MachineFrameInfo *MFI = MF->getFrameInfo();
 225     const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 226     callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
 227   }
 228
 229   static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
 230     &X86::GR32RegClass, &X86::GR32RegClass,
 231     &X86::GR32RegClass, &X86::GR32RegClass,  0
 232   };
 233   static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
 234     &X86::GR32RegClass, &X86::GR32RegClass,
 235     &X86::GR32RegClass, &X86::GR32RegClass,
 236     &X86::GR32RegClass, &X86::GR32RegClass,  0
 237   };
 238   static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
 239     &X86::GR64RegClass, &X86::GR64RegClass,
 240     &X86::GR64RegClass, &X86::GR64RegClass,
 241     &X86::GR64RegClass, &X86::GR64RegClass, 0
 242   };
 243   static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
 244     &X86::GR64RegClass, &X86::GR64RegClass,
 245     &X86::GR64RegClass, &X86::GR64RegClass,
 246     &X86::GR64RegClass, &X86::GR64RegClass,
 247     &X86::GR64RegClass, &X86::GR64RegClass, 0
 248   };
 249   static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
 250     &X86::GR64RegClass,  &X86::GR64RegClass,
 251     &X86::GR64RegClass,  &X86::GR64RegClass,
 252     &X86::GR64RegClass,  &X86::GR64RegClass,
 253     &X86::GR64RegClass,  &X86::GR64RegClass,
 254     &X86::VR128RegClass, &X86::VR128RegClass,
 255     &X86::VR128RegClass, &X86::VR128RegClass,
 256     &X86::VR128RegClass, &X86::VR128RegClass,
 257     &X86::VR128RegClass, &X86::VR128RegClass,
 258     &X86::VR128RegClass, &X86::VR128RegClass, 0
 259   };
 260
 261   if (Is64Bit) {
 262     if (IsWin64)
 263       return CalleeSavedRegClassesWin64;
 264     else
 265       return (callsEHReturn ?
 266               CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
 267   } else {
 268     return (callsEHReturn ?
 269             CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
 270   }
 271 }
 272
 273 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 274   BitVector Reserved(getNumRegs());
 275   // Set the stack-pointer register and its aliases as reserved.
 276   Reserved.set(X86::RSP);
 277   Reserved.set(X86::ESP);
 278   Reserved.set(X86::SP);
 279   Reserved.set(X86::SPL);
 280   // Set the frame-pointer register and its aliases as reserved if needed.
 281   if (hasFP(MF)) {
 282     Reserved.set(X86::RBP);
 283     Reserved.set(X86::EBP);
 284     Reserved.set(X86::BP);
 285     Reserved.set(X86::BPL);
 286   }
 287   // Mark the x87 stack registers as reserved, since they don't
 288   // behave normally with respect to liveness. We don't fully
 289   // model the effects of x87 stack pushes and pops after
 290   // stackification.
 291   Reserved.set(X86::ST0);
 292   Reserved.set(X86::ST1);
 293   Reserved.set(X86::ST2);
 294   Reserved.set(X86::ST3);
 295   Reserved.set(X86::ST4);
 296   Reserved.set(X86::ST5);
 297   Reserved.set(X86::ST6);
 298   Reserved.set(X86::ST7);
 299   return Reserved;
 300 }
 301
 302 //===----------------------------------------------------------------------===//
 303 // Stack Frame Processing methods
 304 //===----------------------------------------------------------------------===//
 305
 306 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
 307   unsigned MaxAlign = 0;
 308   for (int i = FFI->getObjectIndexBegin(),
 309          e = FFI->getObjectIndexEnd(); i != e; ++i) {
 310     if (FFI->isDeadObjectIndex(i))
 311       continue;
 312     unsigned Align = FFI->getObjectAlignment(i);
 313     MaxAlign = std::max(MaxAlign, Align);
 314   }
 315
 316   return MaxAlign;
 317 }
 318
 319 // hasFP - Return true if the specified function should have a dedicated frame
 320 // pointer register.  This is true if the function has variable sized allocas or
 321 // if frame pointer elimination is disabled.
 322 //
 323 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
 324   const MachineFrameInfo *MFI = MF.getFrameInfo();
 325   const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 326
 327   return (NoFramePointerElim ||
 328           needsStackRealignment(MF) ||
 329           MFI->hasVarSizedObjects() ||
 330           MFI->isFrameAddressTaken() ||
 331           MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
 332           (MMI && MMI->callsUnwindInit()));
 333 }
 334
 335 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
 336   const MachineFrameInfo *MFI = MF.getFrameInfo();
 337
 338   // FIXME: Currently we don't support stack realignment for functions with
 339   // variable-sized allocas
 340   return (RealignStack &&
 341           (MFI->getMaxAlignment() > StackAlign &&
 342            !MFI->hasVarSizedObjects()));
 343 }
 344
 345 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
 346   return !MF.getFrameInfo()->hasVarSizedObjects();
 347 }
 348
 349 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
 350                                            int &FrameIdx) const {
 351   if (Reg == FramePtr && hasFP(MF)) {
 352     FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
 353     return true;
 354   }
 355   return false;
 356 }
 357
 358
 359 int
 360 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
 361   int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
 362   uint64_t StackSize = MF.getFrameInfo()->getStackSize();
 363
 364   if (needsStackRealignment(MF)) {
 365     if (FI < 0)
 366       // Skip the saved EBP
 367       Offset += SlotSize;
 368     else {
 369       unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
 370       assert( (-(Offset + StackSize)) % Align == 0);
 371       Align = 0;
 372       return Offset + StackSize;
 373     }
 374
 375     // FIXME: Support tail calls
 376   } else {
 377     if (!hasFP(MF))
 378       return Offset + StackSize;
 379
 380     // Skip the saved EBP
 381     Offset += SlotSize;
 382
 383     // Skip the RETADDR move area
 384     X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
 385     int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
 386     if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
 387   }
 388
 389   return Offset;
 390 }
 391
 392 void X86RegisterInfo::
 393 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 394                               MachineBasicBlock::iterator I) const {
 395   if (!hasReservedCallFrame(MF)) {
 396     // If the stack pointer can be changed after prologue, turn the
 397     // adjcallstackup instruction into a 'sub ESP, <amt>' and the
 398     // adjcallstackdown instruction into 'add ESP, <amt>'
 399     // TODO: consider using push / pop instead of sub + store / add
 400     MachineInstr *Old = I;
 401     uint64_t Amount = Old->getOperand(0).getImm();
 402     if (Amount != 0) {
 403       // We need to keep the stack aligned properly.  To do this, we round the
 404       // amount of space needed for the outgoing arguments up to the next
 405       // alignment boundary.
 406       Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
 407
 408       MachineInstr *New = 0;
 409       if (Old->getOpcode() == getCallFrameSetupOpcode()) {
 410         New = BuildMI(MF, Old->getDebugLoc(),
 411                       TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
 412                       StackPtr).addReg(StackPtr).addImm(Amount);
 413       } else {
 414         assert(Old->getOpcode() == getCallFrameDestroyOpcode());
 415         // factor out the amount the callee already popped.
 416         uint64_t CalleeAmt = Old->getOperand(1).getImm();
 417         Amount -= CalleeAmt;
 418         if (Amount) {
 419           unsigned Opc = (Amount < 128) ?
 420             (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
 421             (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
 422           New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
 423             .addReg(StackPtr).addImm(Amount);
 424         }
 425       }
 426
 427       if (New) {
 428         // The EFLAGS implicit def is dead.
 429         New->getOperand(3).setIsDead();
 430
 431         // Replace the pseudo instruction with a new instruction...
 432         MBB.insert(I, New);
 433       }
 434     }
 435   } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
 436     // If we are performing frame pointer elimination and if the callee pops
 437     // something off the stack pointer, add it back.  We do this until we have
 438     // more advanced stack pointer tracking ability.
 439     if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
 440       unsigned Opc = (CalleeAmt < 128) ?
 441         (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
 442         (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
 443       MachineInstr *Old = I;
 444       MachineInstr *New =
 445         BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
 446                 StackPtr).addReg(StackPtr).addImm(CalleeAmt);
 447       // The EFLAGS implicit def is dead.
 448       New->getOperand(3).setIsDead();
 449
 450       MBB.insert(I, New);
 451     }
 452   }
 453
 454   MBB.erase(I);
 455 }
 456
 457 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 458                                           int SPAdj, RegScavenger *RS) const{
 459   assert(SPAdj == 0 && "Unexpected");
 460
 461   unsigned i = 0;
 462   MachineInstr &MI = *II;
 463   MachineFunction &MF = *MI.getParent()->getParent();
 464   while (!MI.getOperand(i).isFI()) {
 465     ++i;
 466     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
 467   }
 468
 469   int FrameIndex = MI.getOperand(i).getIndex();
 470
 471   unsigned BasePtr;
 472   if (needsStackRealignment(MF))
 473     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
 474   else
 475     BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
 476
 477   // This must be part of a four operand memory reference.  Replace the
 478   // FrameIndex with base register with EBP.  Add an offset to the offset.
 479   MI.getOperand(i).ChangeToRegister(BasePtr, false);
 480
 481   // Now add the frame object offset to the offset from EBP.
 482   if (MI.getOperand(i+3).isImm()) {
 483     // Offset is a 32-bit integer.
 484     int Offset = getFrameIndexOffset(MF, FrameIndex) +
 485       (int)(MI.getOperand(i+3).getImm());
 486
 487      MI.getOperand(i+3).ChangeToImmediate(Offset);
 488   } else {
 489     // Offset is symbolic. This is extremely rare.
 490     uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
 491                       (uint64_t)MI.getOperand(i+3).getOffset();
 492     MI.getOperand(i+3).setOffset(Offset);
 493   }
 494 }
 495
 496 void
 497 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
 498                                                       RegScavenger *RS) const {
 499   MachineFrameInfo *FFI = MF.getFrameInfo();
 500
 501   // Calculate and set max stack object alignment early, so we can decide
 502   // whether we will need stack realignment (and thus FP).
 503   unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
 504                                calculateMaxStackAlignment(FFI));
 505
 506   FFI->setMaxAlignment(MaxAlign);
 507
 508   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
 509   int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
 510   if (TailCallReturnAddrDelta < 0) {
 511     // create RETURNADDR area
 512     //   arg
 513     //   arg
 514     //   RETADDR
 515     //   { ...
 516     //     RETADDR area
 517     //     ...
 518     //   }
 519     //   [EBP]
 520     MF.getFrameInfo()->
 521       CreateFixedObject(-TailCallReturnAddrDelta,
 522                         (-1*SlotSize)+TailCallReturnAddrDelta);
 523   }
 524   if (hasFP(MF)) {
 525     assert((TailCallReturnAddrDelta <= 0) &&
 526            "The Delta should always be zero or negative");
 527     // Create a frame entry for the EBP register that must be saved.
 528     int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
 529                                                         (int)SlotSize * -2+
 530                                                        TailCallReturnAddrDelta);
 531     assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
 532            "Slot for EBP register must be last in order to be found!");
 533     FrameIdx = 0;
 534   }
 535 }
 536
 537 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
 538 /// stack pointer by a constant value.
 539 static
 540 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
 541                   unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
 542                   const TargetInstrInfo &TII) {
 543   bool isSub = NumBytes < 0;
 544   uint64_t Offset = isSub ? -NumBytes : NumBytes;
 545   unsigned Opc = isSub
 546     ? ((Offset < 128) ?
 547        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
 548        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
 549     : ((Offset < 128) ?
 550        (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
 551        (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
 552   uint64_t Chunk = (1LL << 31) - 1;
 553   DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
 554                  DebugLoc::getUnknownLoc());
 555
 556   while (Offset) {
 557     uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
 558     MachineInstr *MI =
 559       BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
 560          .addReg(StackPtr).addImm(ThisVal);
 561     // The EFLAGS implicit def is dead.
 562     MI->getOperand(3).setIsDead();
 563     Offset -= ThisVal;
 564   }
 565 }
 566
 567 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
 568 static
 569 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
 570                       unsigned StackPtr, uint64_t *NumBytes = NULL) {
 571   if (MBBI == MBB.begin()) return;
 572
 573   MachineBasicBlock::iterator PI = prior(MBBI);
 574   unsigned Opc = PI->getOpcode();
 575   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
 576        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
 577       PI->getOperand(0).getReg() == StackPtr) {
 578     if (NumBytes)
 579       *NumBytes += PI->getOperand(2).getImm();
 580     MBB.erase(PI);
 581   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
 582               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
 583              PI->getOperand(0).getReg() == StackPtr) {
 584     if (NumBytes)
 585       *NumBytes -= PI->getOperand(2).getImm();
 586     MBB.erase(PI);
 587   }
 588 }
 589
 590 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
 591 static
 592 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
 593                         MachineBasicBlock::iterator &MBBI,
 594                         unsigned StackPtr, uint64_t *NumBytes = NULL) {
 595   return;
 596
 597   if (MBBI == MBB.end()) return;
 598
 599   MachineBasicBlock::iterator NI = next(MBBI);
 600   if (NI == MBB.end()) return;
 601
 602   unsigned Opc = NI->getOpcode();
 603   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
 604        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
 605       NI->getOperand(0).getReg() == StackPtr) {
 606     if (NumBytes)
 607       *NumBytes -= NI->getOperand(2).getImm();
 608     MBB.erase(NI);
 609     MBBI = NI;
 610   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
 611               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
 612              NI->getOperand(0).getReg() == StackPtr) {
 613     if (NumBytes)
 614       *NumBytes += NI->getOperand(2).getImm();
 615     MBB.erase(NI);
 616     MBBI = NI;
 617   }
 618 }
 619
 620 /// mergeSPUpdates - Checks the instruction before/after the passed
 621 /// instruction. If it is an ADD/SUB instruction it is deleted
 622 /// argument and the stack adjustment is returned as a positive value for ADD
 623 /// and a negative for SUB.
 624 static int mergeSPUpdates(MachineBasicBlock &MBB,
 625                            MachineBasicBlock::iterator &MBBI,
 626                            unsigned StackPtr,
 627                            bool doMergeWithPrevious) {
 628
 629   if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
 630       (!doMergeWithPrevious && MBBI == MBB.end()))
 631     return 0;
 632
 633   int Offset = 0;
 634
 635   MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
 636   MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
 637   unsigned Opc = PI->getOpcode();
 638   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
 639        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
 640       PI->getOperand(0).getReg() == StackPtr){
 641     Offset += PI->getOperand(2).getImm();
 642     MBB.erase(PI);
 643     if (!doMergeWithPrevious) MBBI = NI;
 644   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
 645               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
 646              PI->getOperand(0).getReg() == StackPtr) {
 647     Offset -= PI->getOperand(2).getImm();
 648     MBB.erase(PI);
 649     if (!doMergeWithPrevious) MBBI = NI;
 650   }
 651
 652   return Offset;
 653 }
 654
 655 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
 656                                                 unsigned LabelId,
 657                                                 unsigned FramePtr) const {
 658   MachineFrameInfo *MFI = MF.getFrameInfo();
 659   MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 660   if (!MMI) return;
 661
 662   // Add callee saved registers to move list.
 663   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
 664   if (CSI.empty()) return;
 665
 666   std::vector<MachineMove> &Moves = MMI->getFrameMoves();
 667   const TargetData *TD = MF.getTarget().getTargetData();
 668   bool HasFP = hasFP(MF);
 669
 670   // Calculate amount of bytes used for return address storing
 671   int stackGrowth =
 672     (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
 673      TargetFrameInfo::StackGrowsUp ?
 674      TD->getPointerSize() : -TD->getPointerSize());
 675
 676   // FIXME: This is dirty hack. The code itself is pretty mess right now.
 677   // It should be rewritten from scratch and generalized sometimes.
 678
 679   // Determine maximum offset (minumum due to stack growth)
 680   int64_t MaxOffset = 0;
 681   for (std::vector<CalleeSavedInfo>::const_iterator
 682          I = CSI.begin(), E = CSI.end(); I != E; ++I)
 683     MaxOffset = std::min(MaxOffset,
 684                          MFI->getObjectOffset(I->getFrameIdx()));
 685
 686   // Calculate offsets.
 687   int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
 688   for (std::vector<CalleeSavedInfo>::const_iterator
 689          I = CSI.begin(), E = CSI.end(); I != E; ++I) {
 690     int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
 691     unsigned Reg = I->getReg();
 692     Offset = MaxOffset - Offset + saveAreaOffset;
 693
 694     MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
 695     MachineLocation CSSrc(Reg);
 696     Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
 697   }
 698 }
 699
 700 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
 701   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
 702   MachineFrameInfo *MFI = MF.getFrameInfo();
 703   const Function* Fn = MF.getFunction();
 704   const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
 705   MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 706   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
 707   MachineBasicBlock::iterator MBBI = MBB.begin();
 708   bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
 709                           !Fn->doesNotThrow() ||
 710                           UnwindTablesMandatory;
 711   bool HasFP = hasFP(MF);
 712   DebugLoc DL;
 713
 714   // Get the number of bytes to allocate from the FrameInfo.
 715   uint64_t StackSize = MFI->getStackSize();
 716
 717   // Get desired stack alignment
 718   uint64_t MaxAlign  = MFI->getMaxAlignment();
 719
 720   // Add RETADDR move area to callee saved frame size.
 721   int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
 722   if (TailCallReturnAddrDelta < 0)
 723     X86FI->setCalleeSavedFrameSize(
 724           X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
 725
 726   // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
 727   // function, and use up to 128 bytes of stack space, don't have a frame
 728   // pointer, calls, or dynamic alloca then we do not need to adjust the
 729   // stack pointer (we fit in the Red Zone).
 730   bool DisableRedZone = Fn->hasFnAttr(Attribute::NoRedZone);
 731   if (Is64Bit && !DisableRedZone &&
 732       !needsStackRealignment(MF) &&
 733       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
 734       !MFI->hasCalls() &&                          // No calls.
 735       !Subtarget->isTargetWin64()) {               // Win64 has no Red Zone
 736     uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
 737     if (HasFP) MinSize += SlotSize;
 738     StackSize = std::max(MinSize,
 739                          StackSize > 128 ? StackSize - 128 : 0);
 740     MFI->setStackSize(StackSize);
 741   }
 742
 743   // Insert stack pointer adjustment for later moving of return addr.  Only
 744   // applies to tail call optimized functions where the callee argument stack
 745   // size is bigger than the callers.
 746   if (TailCallReturnAddrDelta < 0) {
 747     MachineInstr *MI =
 748       BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
 749               StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
 750     // The EFLAGS implicit def is dead.
 751     MI->getOperand(3).setIsDead();
 752   }
 753
 754   //  uint64_t StackSize = MFI->getStackSize();
 755   std::vector<MachineMove> &Moves = MMI->getFrameMoves();
 756   const TargetData *TD = MF.getTarget().getTargetData();
 757   int stackGrowth =
 758     (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
 759      TargetFrameInfo::StackGrowsUp ?
 760      TD->getPointerSize() : -TD->getPointerSize());
 761
 762   uint64_t NumBytes = 0;
 763   if (HasFP) {
 764     // Calculate required stack adjustment
 765     uint64_t FrameSize = StackSize - SlotSize;
 766     if (needsStackRealignment(MF))
 767       FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
 768
 769     NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
 770
 771     // Get the offset of the stack slot for the EBP register, which is
 772     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
 773     // Update the frame offset adjustment.
 774     MFI->setOffsetAdjustment(-NumBytes);
 775
 776     // Save EBP/RBP into the appropriate stack slot...
 777     BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
 778       .addReg(FramePtr, RegState::Kill);
 779
 780     if (needsFrameMoves) {
 781       // Mark effective beginning of when frame pointer becomes valid.
 782       unsigned FrameLabelId = MMI->NextLabelID();
 783       BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
 784
 785       // Define the current CFA rule to use the provided offset.
 786       if (StackSize) {
 787         MachineLocation SPDst(MachineLocation::VirtualFP);
 788         MachineLocation SPSrc(MachineLocation::VirtualFP,
 789                               HasFP ? 2 * stackGrowth :
 790                                       -StackSize + stackGrowth);
 791         Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
 792       } else {
 793         // FIXME: Verify & implement for FP
 794         MachineLocation SPDst(StackPtr);
 795         MachineLocation SPSrc(StackPtr, stackGrowth);
 796         Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
 797       }
 798
 799       // Change the rule for the FramePtr to be an "offset" rule.
 800       MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
 801       MachineLocation FPSrc(FramePtr);
 802       Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
 803     }
 804
 805     // Update EBP with the new base value...
 806     BuildMI(MBB, MBBI, DL,
 807             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
 808         .addReg(StackPtr);
 809
 810     if (needsFrameMoves) {
 811       unsigned FrameLabelId = MMI->NextLabelID();
 812       BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
 813
 814       // Define the current CFA to use the EBP/RBP register.
 815       MachineLocation FPDst(FramePtr);
 816       MachineLocation FPSrc(MachineLocation::VirtualFP);
 817       Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
 818     }
 819
 820     // Mark the FramePtr as live-in in every block except the entry.
 821     for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
 822          I != E; ++I)
 823       I->addLiveIn(FramePtr);
 824
 825     // Realign stack
 826     if (needsStackRealignment(MF)) {
 827       MachineInstr *MI =
 828         BuildMI(MBB, MBBI, DL,
 829                 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
 830                 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
 831
 832       // The EFLAGS implicit def is dead.
 833       MI->getOperand(3).setIsDead();
 834     }
 835   } else {
 836     NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
 837   }
 838
 839   // Skip the callee-saved push instructions.
 840   bool RegsSaved = false;
 841   while (MBBI != MBB.end() &&
 842          (MBBI->getOpcode() == X86::PUSH32r ||
 843           MBBI->getOpcode() == X86::PUSH64r)) {
 844     RegsSaved = true;
 845     ++MBBI;
 846   }
 847
 848   if (RegsSaved && needsFrameMoves) {
 849     // Mark end of callee-saved push instructions.
 850     unsigned LabelId = MMI->NextLabelID();
 851     BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
 852
 853     // Emit DWARF info specifying the offsets of the callee-saved registers.
 854     emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
 855   }
 856
 857   if (MBBI != MBB.end())
 858     DL = MBBI->getDebugLoc();
 859
 860   // Adjust stack pointer: ESP -= numbytes.
 861   if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
 862     // Check, whether EAX is livein for this function.
 863     bool isEAXAlive = false;
 864     for (MachineRegisterInfo::livein_iterator
 865            II = MF.getRegInfo().livein_begin(),
 866            EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
 867       unsigned Reg = II->first;
 868       isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
 869                     Reg == X86::AH || Reg == X86::AL);
 870     }
 871
 872     // Function prologue calls _alloca to probe the stack when allocating more
 873     // than 4k bytes in one go. Touching the stack at 4K increments is necessary
 874     // to ensure that the guard pages used by the OS virtual memory manager are
 875     // allocated in correct sequence.
 876     if (!isEAXAlive) {
 877       BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
 878         .addImm(NumBytes);
 879       BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
 880         .addExternalSymbol("_alloca");
 881     } else {
 882       // Save EAX
 883       BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
 884         .addReg(X86::EAX, RegState::Kill);
 885
 886       // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
 887       // allocated bytes for EAX.
 888       BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
 889         .addImm(NumBytes - 4);
 890       BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
 891         .addExternalSymbol("_alloca");
 892
 893       // Restore EAX
 894       MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
 895                                               X86::EAX),
 896                                       StackPtr, false, NumBytes - 4);
 897       MBB.insert(MBBI, MI);
 898     }
 899   } else if (NumBytes) {
 900     // If there is an SUB32ri of ESP immediately before this instruction, merge
 901     // the two. This can be the case when tail call elimination is enabled and
 902     // the callee has more arguments then the caller.
 903     NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
 904
 905     // If there is an ADD32ri or SUB32ri of ESP immediately after this
 906     // instruction, merge the two instructions.
 907     mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
 908
 909     if (NumBytes)
 910       emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
 911   }
 912
 913   if (!HasFP && needsFrameMoves && NumBytes) {
 914     // Mark end of stack pointer adjustment.
 915     unsigned LabelId = MMI->NextLabelID();
 916     BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
 917
 918     // Define the current CFA rule to use the provided offset.
 919     if (StackSize) {
 920       MachineLocation SPDst(MachineLocation::VirtualFP);
 921       MachineLocation SPSrc(MachineLocation::VirtualFP,
 922                             -StackSize + stackGrowth);
 923       Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
 924     } else {
 925       // FIXME: Verify & implement for FP
 926       MachineLocation SPDst(StackPtr);
 927       MachineLocation SPSrc(StackPtr, stackGrowth);
 928       Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
 929     }
 930   }
 931 }
 932
 933 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
 934                                    MachineBasicBlock &MBB) const {
 935   const MachineFrameInfo *MFI = MF.getFrameInfo();
 936   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
 937   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 938   unsigned RetOpcode = MBBI->getOpcode();
 939   DebugLoc DL = MBBI->getDebugLoc();
 940
 941   switch (RetOpcode) {
 942   case X86::RET:
 943   case X86::RETI:
 944   case X86::TCRETURNdi:
 945   case X86::TCRETURNri:
 946   case X86::TCRETURNri64:
 947   case X86::TCRETURNdi64:
 948   case X86::EH_RETURN:
 949   case X86::EH_RETURN64:
 950   case X86::TAILJMPd:
 951   case X86::TAILJMPr:
 952   case X86::TAILJMPm: break;  // These are ok
 953   default:
 954     llvm_unreachable("Can only insert epilog into returning blocks");
 955   }
 956
 957   // Get the number of bytes to allocate from the FrameInfo
 958   uint64_t StackSize = MFI->getStackSize();
 959   uint64_t MaxAlign  = MFI->getMaxAlignment();
 960   unsigned CSSize = X86FI->getCalleeSavedFrameSize();
 961   uint64_t NumBytes = 0;
 962
 963   if (hasFP(MF)) {
 964     // Calculate required stack adjustment
 965     uint64_t FrameSize = StackSize - SlotSize;
 966     if (needsStackRealignment(MF))
 967       FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
 968
 969     NumBytes = FrameSize - CSSize;
 970
 971     // pop EBP.
 972     BuildMI(MBB, MBBI, DL,
 973             TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
 974   } else {
 975     NumBytes = StackSize - CSSize;
 976   }
 977
 978   // Skip the callee-saved pop instructions.
 979   MachineBasicBlock::iterator LastCSPop = MBBI;
 980   while (MBBI != MBB.begin()) {
 981     MachineBasicBlock::iterator PI = prior(MBBI);
 982     unsigned Opc = PI->getOpcode();
 983     if (Opc != X86::POP32r && Opc != X86::POP64r &&
 984         !PI->getDesc().isTerminator())
 985       break;
 986     --MBBI;
 987   }
 988
 989   DL = MBBI->getDebugLoc();
 990
 991   // If there is an ADD32ri or SUB32ri of ESP immediately before this
 992   // instruction, merge the two instructions.
 993   if (NumBytes || MFI->hasVarSizedObjects())
 994     mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
 995
 996   // If dynamic alloca is used, then reset esp to point to the last callee-saved
 997   // slot before popping them off! Same applies for the case, when stack was
 998   // realigned
 999   if (needsStackRealignment(MF)) {
1000     // We cannot use LEA here, because stack pointer was realigned. We need to
1001     // deallocate local frame back
1002     if (CSSize) {
1003       emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1004       MBBI = prior(LastCSPop);
1005     }
1006
1007     BuildMI(MBB, MBBI, DL,
1008             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1009             StackPtr).addReg(FramePtr);
1010   } else if (MFI->hasVarSizedObjects()) {
1011     if (CSSize) {
1012       unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1013       MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1014                                          FramePtr, false, -CSSize);
1015       MBB.insert(MBBI, MI);
1016     } else
1017       BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1018               StackPtr).addReg(FramePtr);
1019
1020   } else {
1021     // adjust stack pointer back: ESP += numbytes
1022     if (NumBytes)
1023       emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1024   }
1025
1026   // We're returning from function via eh_return.
1027   if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1028     MBBI = prior(MBB.end());
1029     MachineOperand &DestAddr  = MBBI->getOperand(0);
1030     assert(DestAddr.isReg() && "Offset should be in register!");
1031     BuildMI(MBB, MBBI, DL,
1032             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1033             StackPtr).addReg(DestAddr.getReg());
1034   // Tail call return: adjust the stack pointer and jump to callee
1035   } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1036              RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1037     MBBI = prior(MBB.end());
1038     MachineOperand &JumpTarget = MBBI->getOperand(0);
1039     MachineOperand &StackAdjust = MBBI->getOperand(1);
1040     assert(StackAdjust.isImm() && "Expecting immediate value.");
1041
1042     // Adjust stack pointer.
1043     int StackAdj = StackAdjust.getImm();
1044     int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1045     int Offset = 0;
1046     assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1047     // Incoporate the retaddr area.
1048     Offset = StackAdj-MaxTCDelta;
1049     assert(Offset >= 0 && "Offset should never be negative");
1050
1051     if (Offset) {
1052       // Check for possible merge with preceeding ADD instruction.
1053       Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1054       emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1055     }
1056
1057     // Jump to label or value in register.
1058     if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1059       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1060         addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1061     else if (RetOpcode== X86::TCRETURNri64)
1062       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1063     else
1064        BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1065
1066     // Delete the pseudo instruction TCRETURN.
1067     MBB.erase(MBBI);
1068   } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1069              (X86FI->getTCReturnAddrDelta() < 0)) {
1070     // Add the return addr area delta back since we are not tail calling.
1071     int delta = -1*X86FI->getTCReturnAddrDelta();
1072     MBBI = prior(MBB.end());
1073     // Check for possible merge with preceeding ADD instruction.
1074     delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1075     emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1076   }
1077 }
1078
1079 unsigned X86RegisterInfo::getRARegister() const {
1080   if (Is64Bit)
1081     return X86::RIP;  // Should have dwarf #16
1082   else
1083     return X86::EIP;  // Should have dwarf #8
1084 }
1085
1086 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1087   return hasFP(MF) ? FramePtr : StackPtr;
1088 }
1089
1090 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1091                                                                          const {
1092   // Calculate amount of bytes used for return address storing
1093   int stackGrowth = (Is64Bit ? -8 : -4);
1094
1095   // Initial state of the frame pointer is esp+4.
1096   MachineLocation Dst(MachineLocation::VirtualFP);
1097   MachineLocation Src(StackPtr, stackGrowth);
1098   Moves.push_back(MachineMove(0, Dst, Src));
1099
1100   // Add return address to move list
1101   MachineLocation CSDst(StackPtr, stackGrowth);
1102   MachineLocation CSSrc(getRARegister());
1103   Moves.push_back(MachineMove(0, CSDst, CSSrc));
1104 }
1105
1106 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1107   llvm_unreachable("What is the exception register");
1108   return 0;
1109 }
1110
1111 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1112   llvm_unreachable("What is the exception handler register");
1113   return 0;
1114 }
1115
1116 namespace llvm {
1117 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1118   switch (VT.getSimpleVT()) {
1119   default: return Reg;
1120   case MVT::i8:
1121     if (High) {
1122       switch (Reg) {
1123       default: return 0;
1124       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1125         return X86::AH;
1126       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1127         return X86::DH;
1128       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1129         return X86::CH;
1130       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1131         return X86::BH;
1132       }
1133     } else {
1134       switch (Reg) {
1135       default: return 0;
1136       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1137         return X86::AL;
1138       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1139         return X86::DL;
1140       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1141         return X86::CL;
1142       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1143         return X86::BL;
1144       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1145         return X86::SIL;
1146       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1147         return X86::DIL;
1148       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1149         return X86::BPL;
1150       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1151         return X86::SPL;
1152       case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1153         return X86::R8B;
1154       case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1155         return X86::R9B;
1156       case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1157         return X86::R10B;
1158       case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1159         return X86::R11B;
1160       case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1161         return X86::R12B;
1162       case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1163         return X86::R13B;
1164       case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1165         return X86::R14B;
1166       case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1167         return X86::R15B;
1168       }
1169     }
1170   case MVT::i16:
1171     switch (Reg) {
1172     default: return Reg;
1173     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1174       return X86::AX;
1175     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1176       return X86::DX;
1177     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1178       return X86::CX;
1179     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1180       return X86::BX;
1181     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1182       return X86::SI;
1183     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1184       return X86::DI;
1185     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1186       return X86::BP;
1187     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1188       return X86::SP;
1189     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1190       return X86::R8W;
1191     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1192       return X86::R9W;
1193     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1194       return X86::R10W;
1195     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1196       return X86::R11W;
1197     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1198       return X86::R12W;
1199     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1200       return X86::R13W;
1201     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1202       return X86::R14W;
1203     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1204       return X86::R15W;
1205     }
1206   case MVT::i32:
1207     switch (Reg) {
1208     default: return Reg;
1209     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1210       return X86::EAX;
1211     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1212       return X86::EDX;
1213     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1214       return X86::ECX;
1215     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1216       return X86::EBX;
1217     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1218       return X86::ESI;
1219     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1220       return X86::EDI;
1221     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1222       return X86::EBP;
1223     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1224       return X86::ESP;
1225     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1226       return X86::R8D;
1227     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1228       return X86::R9D;
1229     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1230       return X86::R10D;
1231     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1232       return X86::R11D;
1233     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1234       return X86::R12D;
1235     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1236       return X86::R13D;
1237     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1238       return X86::R14D;
1239     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1240       return X86::R15D;
1241     }
1242   case MVT::i64:
1243     switch (Reg) {
1244     default: return Reg;
1245     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1246       return X86::RAX;
1247     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1248       return X86::RDX;
1249     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1250       return X86::RCX;
1251     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1252       return X86::RBX;
1253     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1254       return X86::RSI;
1255     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1256       return X86::RDI;
1257     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1258       return X86::RBP;
1259     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1260       return X86::RSP;
1261     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1262       return X86::R8;
1263     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1264       return X86::R9;
1265     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1266       return X86::R10;
1267     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1268       return X86::R11;
1269     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1270       return X86::R12;
1271     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1272       return X86::R13;
1273     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1274       return X86::R14;
1275     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1276       return X86::R15;
1277     }
1278   }
1279
1280   return Reg;
1281 }
1282 }
1283
1284 #include "X86GenRegisterInfo.inc"
1285
1286 namespace {
1287   struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1288     static char ID;
1289     MSAC() : MachineFunctionPass(&ID) {}
1290
1291     virtual bool runOnMachineFunction(MachineFunction &MF) {
1292       MachineFrameInfo *FFI = MF.getFrameInfo();
1293       MachineRegisterInfo &RI = MF.getRegInfo();
1294
1295       // Calculate max stack alignment of all already allocated stack objects.
1296       unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1297
1298       // Be over-conservative: scan over all vreg defs and find, whether vector
1299       // registers are used. If yes - there is probability, that vector register
1300       // will be spilled and thus stack needs to be aligned properly.
1301       for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1302            RegNum < RI.getLastVirtReg(); ++RegNum)
1303         MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1304
1305       FFI->setMaxAlignment(MaxAlign);
1306
1307       return false;
1308     }
1309
1310     virtual const char *getPassName() const {
1311       return "X86 Maximal Stack Alignment Calculator";
1312     }
1313   };
1314
1315   char MSAC::ID = 0;
1316 }
1317
1318 FunctionPass*
1319 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }