lib/Target/Blackfin/BlackfinRegisterInfo.cpp

   1 //===- BlackfinRegisterInfo.cpp - Blackfin Register Information -*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Blackfin implementation of the TargetRegisterInfo
  11 // class.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "Blackfin.h"
  16 #include "BlackfinRegisterInfo.h"
  17 #include "BlackfinSubtarget.h"
  18 #include "llvm/Support/Debug.h"
  19 #include "llvm/Support/ErrorHandling.h"
  20 #include "llvm/CodeGen/MachineInstrBuilder.h"
  21 #include "llvm/CodeGen/MachineFunction.h"
  22 #include "llvm/CodeGen/MachineFrameInfo.h"
  23 #include "llvm/CodeGen/MachineLocation.h"
  24 #include "llvm/CodeGen/RegisterScavenging.h"
  25 #include "llvm/Target/TargetFrameInfo.h"
  26 #include "llvm/Target/TargetMachine.h"
  27 #include "llvm/Target/TargetOptions.h"
  28 #include "llvm/Target/TargetInstrInfo.h"
  29 #include "llvm/Type.h"
  30 #include "llvm/ADT/BitVector.h"
  31 #include "llvm/ADT/STLExtras.h"
  32 using namespace llvm;
  33
  34 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
  35                                            const TargetInstrInfo &tii)
  36   : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
  37     Subtarget(st),
  38     TII(tii) {}
  39
  40 const unsigned*
  41 BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
  42   using namespace BF;
  43   static const unsigned CalleeSavedRegs[] = {
  44     FP,
  45     R4, R5, R6, R7,
  46     P3, P4, P5,
  47     0 };
  48   return  CalleeSavedRegs;
  49 }
  50
  51 BitVector
  52 BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  53   using namespace BF;
  54   BitVector Reserved(getNumRegs());
  55   Reserved.set(AZ);
  56   Reserved.set(AN);
  57   Reserved.set(AQ);
  58   Reserved.set(AC0);
  59   Reserved.set(AC1);
  60   Reserved.set(AV0);
  61   Reserved.set(AV0S);
  62   Reserved.set(AV1);
  63   Reserved.set(AV1S);
  64   Reserved.set(V);
  65   Reserved.set(VS);
  66   Reserved.set(CYCLES).set(CYCLES2);
  67   Reserved.set(L0);
  68   Reserved.set(L1);
  69   Reserved.set(L2);
  70   Reserved.set(L3);
  71   Reserved.set(SP);
  72   Reserved.set(RETS);
  73   if (hasFP(MF))
  74     Reserved.set(FP);
  75   return Reserved;
  76 }
  77
  78 // hasFP - Return true if the specified function should have a dedicated frame
  79 // pointer register.  This is true if the function has variable sized allocas or
  80 // if frame pointer elimination is disabled.
  81 bool BlackfinRegisterInfo::hasFP(const MachineFunction &MF) const {
  82   const MachineFrameInfo *MFI = MF.getFrameInfo();
  83   return DisableFramePointerElim(MF) ||
  84     MFI->adjustsStack() || MFI->hasVarSizedObjects();
  85 }
  86
  87 bool BlackfinRegisterInfo::
  88 requiresRegisterScavenging(const MachineFunction &MF) const {
  89   return true;
  90 }
  91
  92 // Emit instructions to add delta to D/P register. ScratchReg must be of the
  93 // same class as Reg (P).
  94 void BlackfinRegisterInfo::adjustRegister(MachineBasicBlock &MBB,
  95                                           MachineBasicBlock::iterator I,
  96                                           DebugLoc DL,
  97                                           unsigned Reg,
  98                                           unsigned ScratchReg,
  99                                           int delta) const {
 100   if (!delta)
 101     return;
 102   if (isInt<7>(delta)) {
 103     BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
 104       .addReg(Reg)              // No kill on two-addr operand
 105       .addImm(delta);
 106     return;
 107   }
 108
 109   // We must load delta into ScratchReg and add that.
 110   loadConstant(MBB, I, DL, ScratchReg, delta);
 111   if (BF::PRegClass.contains(Reg)) {
 112     assert(BF::PRegClass.contains(ScratchReg) &&
 113            "ScratchReg must be a P register");
 114     BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
 115       .addReg(Reg, RegState::Kill)
 116       .addReg(ScratchReg, RegState::Kill);
 117   } else {
 118     assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register");
 119     assert(BF::DRegClass.contains(ScratchReg) &&
 120            "ScratchReg must be a D register");
 121     BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
 122       .addReg(Reg, RegState::Kill)
 123       .addReg(ScratchReg, RegState::Kill);
 124   }
 125 }
 126
 127 // Emit instructions to load a constant into D/P register
 128 void BlackfinRegisterInfo::loadConstant(MachineBasicBlock &MBB,
 129                                         MachineBasicBlock::iterator I,
 130                                         DebugLoc DL,
 131                                         unsigned Reg,
 132                                         int value) const {
 133   if (isInt<7>(value)) {
 134     BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
 135     return;
 136   }
 137
 138   if (isUInt<16>(value)) {
 139     BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
 140     return;
 141   }
 142
 143   if (isInt<16>(value)) {
 144     BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
 145     return;
 146   }
 147
 148   // We must split into halves
 149   BuildMI(MBB, I, DL,
 150           TII.get(BF::LOAD16i), getSubReg(Reg, BF::hi16))
 151     .addImm((value >> 16) & 0xffff)
 152     .addReg(Reg, RegState::ImplicitDefine);
 153   BuildMI(MBB, I, DL,
 154           TII.get(BF::LOAD16i), getSubReg(Reg, BF::lo16))
 155     .addImm(value & 0xffff)
 156     .addReg(Reg, RegState::ImplicitKill)
 157     .addReg(Reg, RegState::ImplicitDefine);
 158 }
 159
 160 void BlackfinRegisterInfo::
 161 eliminateCallFramePseudoInstr(MachineFunction &MF,
 162                               MachineBasicBlock &MBB,
 163                               MachineBasicBlock::iterator I) const {
 164   if (!hasReservedCallFrame(MF)) {
 165     int64_t Amount = I->getOperand(0).getImm();
 166     if (Amount != 0) {
 167       assert(Amount%4 == 0 && "Unaligned call frame size");
 168       if (I->getOpcode() == BF::ADJCALLSTACKDOWN) {
 169         adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, -Amount);
 170       } else {
 171         assert(I->getOpcode() == BF::ADJCALLSTACKUP &&
 172                "Unknown call frame pseudo instruction");
 173         adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, Amount);
 174       }
 175     }
 176   }
 177   MBB.erase(I);
 178 }
 179
 180 /// findScratchRegister - Find a 'free' register. Try for a call-clobbered
 181 /// register first and then a spilled callee-saved register if that fails.
 182 static unsigned findScratchRegister(MachineBasicBlock::iterator II,
 183                                     RegScavenger *RS,
 184                                     const TargetRegisterClass *RC,
 185                                     int SPAdj) {
 186   assert(RS && "Register scavenging must be on");
 187   unsigned Reg = RS->FindUnusedReg(RC);
 188   if (Reg == 0)
 189     Reg = RS->scavengeRegister(RC, II, SPAdj);
 190   return Reg;
 191 }
 192
 193 void
 194 BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 195                                           int SPAdj, RegScavenger *RS) const {
 196   MachineInstr &MI = *II;
 197   MachineBasicBlock &MBB = *MI.getParent();
 198   MachineFunction &MF = *MBB.getParent();
 199   DebugLoc DL = MI.getDebugLoc();
 200
 201   unsigned FIPos;
 202   for (FIPos=0; !MI.getOperand(FIPos).isFI(); ++FIPos) {
 203     assert(FIPos < MI.getNumOperands() &&
 204            "Instr doesn't have FrameIndex operand!");
 205   }
 206   int FrameIndex = MI.getOperand(FIPos).getIndex();
 207   assert(FIPos+1 < MI.getNumOperands() && MI.getOperand(FIPos+1).isImm());
 208   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex)
 209     + MI.getOperand(FIPos+1).getImm();
 210   unsigned BaseReg = BF::FP;
 211   if (hasFP(MF)) {
 212     assert(SPAdj==0 && "Unexpected SP adjust in function with frame pointer");
 213   } else {
 214     BaseReg = BF::SP;
 215     Offset += MF.getFrameInfo()->getStackSize() + SPAdj;
 216   }
 217
 218   bool isStore = false;
 219
 220   switch (MI.getOpcode()) {
 221   case BF::STORE32fi:
 222     isStore = true;
 223   case BF::LOAD32fi: {
 224     assert(Offset%4 == 0 && "Unaligned i32 stack access");
 225     assert(FIPos==1 && "Bad frame index operand");
 226     MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
 227     MI.getOperand(FIPos+1).setImm(Offset);
 228     if (isUInt<6>(Offset)) {
 229       MI.setDesc(TII.get(isStore
 230                          ? BF::STORE32p_uimm6m4
 231                          : BF::LOAD32p_uimm6m4));
 232       return;
 233     }
 234     if (BaseReg == BF::FP && isUInt<7>(-Offset)) {
 235       MI.setDesc(TII.get(isStore
 236                          ? BF::STORE32fp_nimm7m4
 237                          : BF::LOAD32fp_nimm7m4));
 238       MI.getOperand(FIPos+1).setImm(-Offset);
 239       return;
 240     }
 241     if (isInt<18>(Offset)) {
 242       MI.setDesc(TII.get(isStore
 243                          ? BF::STORE32p_imm18m4
 244                          : BF::LOAD32p_imm18m4));
 245       return;
 246     }
 247     // Use RegScavenger to calculate proper offset...
 248     MI.dump();
 249     llvm_unreachable("Stack frame offset too big");
 250     break;
 251   }
 252   case BF::ADDpp: {
 253     assert(MI.getOperand(0).isReg() && "ADD instruction needs a register");
 254     unsigned DestReg = MI.getOperand(0).getReg();
 255     // We need to produce a stack offset in a P register. We emit:
 256     // P0 = offset;
 257     // P0 = BR + P0;
 258     assert(FIPos==1 && "Bad frame index operand");
 259     loadConstant(MBB, II, DL, DestReg, Offset);
 260     MI.getOperand(1).ChangeToRegister(DestReg, false, false, true);
 261     MI.getOperand(2).ChangeToRegister(BaseReg, false);
 262     break;
 263   }
 264   case BF::STORE16fi:
 265     isStore = true;
 266   case BF::LOAD16fi: {
 267     assert(Offset%2 == 0 && "Unaligned i16 stack access");
 268     assert(FIPos==1 && "Bad frame index operand");
 269     // We need a P register to use as an address
 270     unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj);
 271     assert(ScratchReg && "Could not scavenge register");
 272     loadConstant(MBB, II, DL, ScratchReg, Offset);
 273     BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg)
 274       .addReg(ScratchReg, RegState::Kill)
 275       .addReg(BaseReg);
 276     MI.setDesc(TII.get(isStore ? BF::STORE16pi : BF::LOAD16pi));
 277     MI.getOperand(1).ChangeToRegister(ScratchReg, false, false, true);
 278     MI.RemoveOperand(2);
 279     break;
 280   }
 281   case BF::STORE8fi: {
 282     // This is an AnyCC spill, we need a scratch register.
 283     assert(FIPos==1 && "Bad frame index operand");
 284     MachineOperand SpillReg = MI.getOperand(0);
 285     unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
 286     assert(ScratchReg && "Could not scavenge register");
 287     if (SpillReg.getReg()==BF::NCC) {
 288       BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg)
 289         .addOperand(SpillReg);
 290       BuildMI(MBB, II, DL, TII.get(BF::BITTGL), ScratchReg)
 291         .addReg(ScratchReg).addImm(0);
 292     } else {
 293       BuildMI(MBB, II, DL, TII.get(BF::MOVECC_zext), ScratchReg)
 294         .addOperand(SpillReg);
 295     }
 296     // STORE D
 297     MI.setDesc(TII.get(BF::STORE8p_imm16));
 298     MI.getOperand(0).ChangeToRegister(ScratchReg, false, false, true);
 299     MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
 300     MI.getOperand(FIPos+1).setImm(Offset);
 301     break;
 302   }
 303   case BF::LOAD8fi: {
 304     // This is an restore, we need a scratch register.
 305     assert(FIPos==1 && "Bad frame index operand");
 306     MachineOperand SpillReg = MI.getOperand(0);
 307     unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
 308     assert(ScratchReg && "Could not scavenge register");
 309     MI.setDesc(TII.get(BF::LOAD32p_imm16_8z));
 310     MI.getOperand(0).ChangeToRegister(ScratchReg, true);
 311     MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
 312     MI.getOperand(FIPos+1).setImm(Offset);
 313     ++II;
 314     if (SpillReg.getReg()==BF::CC) {
 315       // CC = D
 316       BuildMI(MBB, II, DL, TII.get(BF::MOVECC_nz), BF::CC)
 317         .addReg(ScratchReg, RegState::Kill);
 318     } else {
 319       // Restore NCC (CC = D==0)
 320       BuildMI(MBB, II, DL, TII.get(BF::SETEQri_not), BF::NCC)
 321         .addReg(ScratchReg, RegState::Kill)
 322         .addImm(0);
 323     }
 324     break;
 325   }
 326   default:
 327     llvm_unreachable("Cannot eliminate frame index");
 328     break;
 329   }
 330 }
 331
 332 void BlackfinRegisterInfo::
 333 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
 334                                      RegScavenger *RS) const {
 335   MachineFrameInfo *MFI = MF.getFrameInfo();
 336   const TargetRegisterClass *RC = BF::DPRegisterClass;
 337   if (requiresRegisterScavenging(MF)) {
 338     // Reserve a slot close to SP or frame pointer.
 339     RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
 340                                                        RC->getAlignment(),
 341                                                        false));
 342   }
 343 }
 344
 345 // Emit a prologue that sets up a stack frame.
 346 // On function entry, R0-R2 and P0 may hold arguments.
 347 // R3, P1, and P2 may be used as scratch registers
 348 void BlackfinRegisterInfo::emitPrologue(MachineFunction &MF) const {
 349   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
 350   MachineBasicBlock::iterator MBBI = MBB.begin();
 351   MachineFrameInfo *MFI = MF.getFrameInfo();
 352   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
 353
 354   int FrameSize = MFI->getStackSize();
 355   if (FrameSize%4) {
 356     FrameSize = (FrameSize+3) & ~3;
 357     MFI->setStackSize(FrameSize);
 358   }
 359
 360   if (!hasFP(MF)) {
 361     assert(!MFI->adjustsStack() &&
 362            "FP elimination on a non-leaf function is not supported");
 363     adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
 364     return;
 365   }
 366
 367   // emit a LINK instruction
 368   if (FrameSize <= 0x3ffff) {
 369     BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
 370     return;
 371   }
 372
 373   // Frame is too big, do a manual LINK:
 374   // [--SP] = RETS;
 375   // [--SP] = FP;
 376   // FP = SP;
 377   // P1 = -FrameSize;
 378   // SP = SP + P1;
 379   BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
 380     .addReg(BF::RETS, RegState::Kill);
 381   BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
 382     .addReg(BF::FP, RegState::Kill);
 383   BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
 384     .addReg(BF::SP);
 385   loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
 386   BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
 387     .addReg(BF::SP, RegState::Kill)
 388     .addReg(BF::P1, RegState::Kill);
 389
 390 }
 391
 392 void BlackfinRegisterInfo::emitEpilogue(MachineFunction &MF,
 393                                         MachineBasicBlock &MBB) const {
 394   MachineFrameInfo *MFI = MF.getFrameInfo();
 395   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 396   DebugLoc dl = MBBI->getDebugLoc();
 397
 398   int FrameSize = MFI->getStackSize();
 399   assert(FrameSize%4 == 0 && "Misaligned frame size");
 400
 401   if (!hasFP(MF)) {
 402     assert(!MFI->adjustsStack() &&
 403            "FP elimination on a non-leaf function is not supported");
 404     adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
 405     return;
 406   }
 407
 408   // emit an UNLINK instruction
 409   BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
 410 }
 411
 412 unsigned BlackfinRegisterInfo::getRARegister() const {
 413   return BF::RETS;
 414 }
 415
 416 unsigned
 417 BlackfinRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
 418   return hasFP(MF) ? BF::FP : BF::SP;
 419 }
 420
 421 unsigned BlackfinRegisterInfo::getEHExceptionRegister() const {
 422   llvm_unreachable("What is the exception register");
 423   return 0;
 424 }
 425
 426 unsigned BlackfinRegisterInfo::getEHHandlerRegister() const {
 427   llvm_unreachable("What is the exception handler register");
 428   return 0;
 429 }
 430
 431 int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 432   llvm_unreachable("What is the dwarf register number");
 433   return -1;
 434 }
 435
 436 #include "BlackfinGenRegisterInfo.inc"
 437