Fixed some bugs in register stack pass.
[llvm/zpu.git] / lib / Target / TargetSubtarget.cpp
blobedb76f971533202a9ad815fde7df3105a00cf4b2
1 //===-- TargetSubtarget.cpp - General Target Information -------------------==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the general parts of a Subtarget.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetSubtarget.h"
15 #include "llvm/ADT/SmallVector.h"
16 using namespace llvm;
18 //---------------------------------------------------------------------------
19 // TargetSubtarget Class
21 TargetSubtarget::TargetSubtarget() {}
23 TargetSubtarget::~TargetSubtarget() {}
25 bool TargetSubtarget::enablePostRAScheduler(
26 CodeGenOpt::Level OptLevel,
27 AntiDepBreakMode& Mode,
28 RegClassVector& CriticalPathRCs) const {
29 Mode = ANTIDEP_NONE;
30 CriticalPathRCs.clear();
31 return false;