lib/Target/X86/X86.td

   1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, refered to
  11 // here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget features.
  21 //===----------------------------------------------------------------------===//
  22
  23 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  24                                       "Enable conditional move instructions">;
  25
  26
  27 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  28                                       "Enable MMX instructions">;
  29 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  30                                       "Enable SSE instructions",
  31                                       // SSE codegen depends on cmovs, and all
  32                                       // SSE1+ processors support them.
  33                                       [FeatureMMX, FeatureCMOV]>;
  34 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  35                                       "Enable SSE2 instructions",
  36                                       [FeatureSSE1]>;
  37 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  38                                       "Enable SSE3 instructions",
  39                                       [FeatureSSE2]>;
  40 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  41                                       "Enable SSSE3 instructions",
  42                                       [FeatureSSE3]>;
  43 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
  44                                       "Enable SSE 4.1 instructions",
  45                                       [FeatureSSSE3]>;
  46 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
  47                                       "Enable SSE 4.2 instructions",
  48                                       [FeatureSSE41]>;
  49 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  50                                       "Enable 3DNow! instructions">;
  51 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  52                                       "Enable 3DNow! Athlon instructions",
  53                                       [Feature3DNow]>;
  54 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  55 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  56 // without disabling 64-bit mode.
  57 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  58                                       "Support 64-bit instructions",
  59                                       [FeatureCMOV]>;
  60 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  61                                        "Bit testing of memory is slow">;
  62 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  63                                         "IsUAMemFast", "true",
  64                                         "Fast unaligned memory access">;
  65 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  66                                       "Support SSE 4a instructions">;
  67
  68 def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
  69                                       "Enable AVX instructions">;
  70 def FeatureCLMUL   : SubtargetFeature<"clmul", "HasCLMUL", "true",
  71                                "Enable carry-less multiplication instructions">;
  72 def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
  73                                      "Enable three-operand fused multiple-add">;
  74 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
  75                                       "Enable four-operand fused multiple-add">;
  76 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
  77                                           "HasVectorUAMem", "true",
  78                  "Allow unaligned memory operands on vector/SIMD instructions">;
  79 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
  80                                       "Enable AES instructions">;
  81
  82 //===----------------------------------------------------------------------===//
  83 // X86 processors supported.
  84 //===----------------------------------------------------------------------===//
  85
  86 class Proc<string Name, list<SubtargetFeature> Features>
  87  : Processor<Name, NoItineraries, Features>;
  88
  89 def : Proc<"generic",         []>;
  90 def : Proc<"i386",            []>;
  91 def : Proc<"i486",            []>;
  92 def : Proc<"i586",            []>;
  93 def : Proc<"pentium",         []>;
  94 def : Proc<"pentium-mmx",     [FeatureMMX]>;
  95 def : Proc<"i686",            []>;
  96 def : Proc<"pentiumpro",      [FeatureCMOV]>;
  97 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
  98 def : Proc<"pentium3",        [FeatureSSE1]>;
  99 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 100 def : Proc<"pentium4",        [FeatureSSE2]>;
 101 def : Proc<"x86-64",          [FeatureSSE2,   Feature64Bit, FeatureSlowBTMem]>;
 102 def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
 103 def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
 104 def : Proc<"nocona",          [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
 105 def : Proc<"core2",           [FeatureSSSE3,  Feature64Bit, FeatureSlowBTMem]>;
 106 def : Proc<"penryn",          [FeatureSSE41,  Feature64Bit, FeatureSlowBTMem]>;
 107 def : Proc<"atom",            [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
 108 // "Arrandale" along with corei3 and corei5
 109 def : Proc<"corei7",          [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem,
 110                                FeatureFastUAMem, FeatureAES]>;
 111 def : Proc<"nehalem",         [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem,
 112                                FeatureFastUAMem]>;
 113 // Westmere is a similar machine to nehalem with some additional features.
 114 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 115 def : Proc<"westmere",         [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem,
 116                                 FeatureFastUAMem, FeatureAES]>;
 117 // Sandy Bridge does not have FMA
 118 // FIXME: Wikipedia says it does... it should have AES as well.
 119 def : Proc<"sandybridge",     [FeatureSSE42,  FeatureAVX,   Feature64Bit]>;
 120
 121 def : Proc<"k6",              [FeatureMMX]>;
 122 def : Proc<"k6-2",            [FeatureMMX,    Feature3DNow]>;
 123 def : Proc<"k6-3",            [FeatureMMX,    Feature3DNow]>;
 124 def : Proc<"athlon",          [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
 125 def : Proc<"athlon-tbird",    [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
 126 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 127 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 128 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 129 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 130                                FeatureSlowBTMem]>;
 131 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 132                                FeatureSlowBTMem]>;
 133 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 134                                FeatureSlowBTMem]>;
 135 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 136                                FeatureSlowBTMem]>;
 137 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 138                                FeatureSlowBTMem]>;
 139 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 140                                FeatureSlowBTMem]>;
 141 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 142                                FeatureSlowBTMem]>;
 143 def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
 144                                Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
 145 def : Proc<"barcelona",       [FeatureSSE3,   FeatureSSE4A,
 146                                Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
 147 def : Proc<"istanbul",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
 148                                Feature3DNowA]>;
 149 def : Proc<"shanghai",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
 150                                Feature3DNowA]>;
 151
 152 def : Proc<"winchip-c6",      [FeatureMMX]>;
 153 def : Proc<"winchip2",        [FeatureMMX, Feature3DNow]>;
 154 def : Proc<"c3",              [FeatureMMX, Feature3DNow]>;
 155 def : Proc<"c3-2",            [FeatureSSE1]>;
 156
 157 //===----------------------------------------------------------------------===//
 158 // Register File Description
 159 //===----------------------------------------------------------------------===//
 160
 161 include "X86RegisterInfo.td"
 162
 163 //===----------------------------------------------------------------------===//
 164 // Instruction Descriptions
 165 //===----------------------------------------------------------------------===//
 166
 167 include "X86InstrInfo.td"
 168
 169 def X86InstrInfo : InstrInfo;
 170
 171 //===----------------------------------------------------------------------===//
 172 // Calling Conventions
 173 //===----------------------------------------------------------------------===//
 174
 175 include "X86CallingConv.td"
 176
 177
 178 //===----------------------------------------------------------------------===//
 179 // Assembly Parser
 180 //===----------------------------------------------------------------------===//
 181
 182 // Currently the X86 assembly parser only supports ATT syntax.
 183 def ATTAsmParser : AsmParser {
 184   string AsmParserClassName = "ATTAsmParser";
 185   int Variant = 0;
 186
 187   // Discard comments in assembly strings.
 188   string CommentDelimiter = "#";
 189
 190   // Recognize hard coded registers.
 191   string RegisterPrefix = "%";
 192 }
 193
 194 //===----------------------------------------------------------------------===//
 195 // Assembly Printers
 196 //===----------------------------------------------------------------------===//
 197
 198 // The X86 target supports two different syntaxes for emitting machine code.
 199 // This is controlled by the -x86-asm-syntax={att|intel}
 200 def ATTAsmWriter : AsmWriter {
 201   string AsmWriterClassName  = "ATTInstPrinter";
 202   int Variant = 0;
 203   bit isMCAsmWriter = 1;
 204 }
 205 def IntelAsmWriter : AsmWriter {
 206   string AsmWriterClassName  = "IntelInstPrinter";
 207   int Variant = 1;
 208   bit isMCAsmWriter = 1;
 209 }
 210
 211 def X86 : Target {
 212   // Information about the instructions...
 213   let InstructionSet = X86InstrInfo;
 214
 215   let AssemblyParsers = [ATTAsmParser];
 216
 217   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 218 }