lib/Target/ZPU/ZPUISelLowering.h

   1 //===-- ZPUISelLowering.h - ZPU DAG Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that ZPU uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef ZPUISELLOWERING_H
  16 #define ZPUISELLOWERING_H
  17
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/Target/TargetLowering.h"
  20 #include "ZPU.h"
  21
  22 namespace llvm {
  23   namespace ZPUISD {
  24     enum NodeType {
  25       // Start the numbering from where ISD NodeType finishes.
  26       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  27
  28       // Jump and link (call)
  29       JmpLink,
  30
  31       // Get the Higher 16 bits from a 32-bit immediate
  32       // No relation with ZPU Hi register
  33       Hi,
  34
  35       // Get the Lower 16 bits from a 32-bit immediate
  36       // No relation with ZPU Lo register
  37       Lo,
  38
  39       // Handle gp_rel (small data/bss sections) relocation.
  40       GPRel,
  41
  42       // Conditional Move
  43       CMov,
  44
  45       // Select CC Pseudo Instruction
  46       SelectCC,
  47
  48       // Floating Point Select CC Pseudo Instruction
  49       FPSelectCC,
  50
  51       // Floating Point Branch Conditional
  52       FPBrcond,
  53
  54       // Floating Point Compare
  55       FPCmp,
  56
  57       // Floating Point Rounding
  58       FPRound,
  59
  60       Wrapper,                   // Address wrapper
  61
  62           LESSTHAN,
  63
  64           LESSTHANEQ,
  65
  66           ULESSTHAN,
  67
  68           ULESSTHANEQ,
  69
  70           EQ,
  71
  72           NEQ,
  73
  74       // Return
  75       Ret
  76     };
  77   }
  78
  79   //===--------------------------------------------------------------------===//
  80   // TargetLowering Implementation
  81   //===--------------------------------------------------------------------===//
  82
  83   class ZPUTargetLowering : public TargetLowering  {
  84   public:
  85     explicit ZPUTargetLowering(ZPUTargetMachine &TM);
  86
  87     /// LowerOperation - Provide custom lowering hooks for some operations.
  88     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  89
  90     /// getTargetNodeName - This method returns the name of a target specific
  91     //  DAG node.
  92     virtual const char *getTargetNodeName(unsigned Opcode) const;
  93
  94     /// getSetCCResultType - get the ISD::SETCC result ValueType
  95     MVT::SimpleValueType getSetCCResultType(EVT VT) const;
  96
  97     /// getFunctionAlignment - Return the Log2 alignment of this function.
  98     virtual unsigned getFunctionAlignment(const Function *F) const;
  99   private:
 100
 101
 102     // Lower Operand helpers
 103     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 104                             CallingConv::ID CallConv, bool isVarArg,
 105                             const SmallVectorImpl<ISD::InputArg> &Ins,
 106                             DebugLoc dl, SelectionDAG &DAG,
 107                             SmallVectorImpl<SDValue> &InVals) const;
 108
 109 #if 0
 110     // Lower Operand specifics
 111     SDValue LowerANDOR(SDValue Op, SelectionDAG &DAG) const;
 112     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 113     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 114     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 115     SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
 116     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 117     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 118     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 119     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 120     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 121 #endif
 122     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
 123
 124     virtual SDValue
 125       LowerFormalArguments(SDValue Chain,
 126                            CallingConv::ID CallConv, bool isVarArg,
 127                            const SmallVectorImpl<ISD::InputArg> &Ins,
 128                            DebugLoc dl, SelectionDAG &DAG,
 129                            SmallVectorImpl<SDValue> &InVals) const;
 130
 131     virtual SDValue
 132       LowerCall(SDValue Chain, SDValue Callee,
 133                 CallingConv::ID CallConv, bool isVarArg,
 134                 bool &isTailCall,
 135                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 136                 const SmallVectorImpl<SDValue> &OutVals,
 137                 const SmallVectorImpl<ISD::InputArg> &Ins,
 138                 DebugLoc dl, SelectionDAG &DAG,
 139                 SmallVectorImpl<SDValue> &InVals) const;
 140
 141     virtual SDValue
 142       LowerReturn(SDValue Chain,
 143                   CallingConv::ID CallConv, bool isVarArg,
 144                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 145                   const SmallVectorImpl<SDValue> &OutVals,
 146                   DebugLoc dl, SelectionDAG &DAG) const;
 147
 148     virtual MachineBasicBlock *
 149       EmitInstrWithCustomInserter(MachineInstr *MI,
 150                                   MachineBasicBlock *MBB) const;
 151
 152     // Inline asm support
 153     ConstraintType getConstraintType(const std::string &Constraint) const;
 154
 155     /// Examine constraint string and operand type and determine a weight value.
 156     /// The operand object must already have been set up with the operand type.
 157     ConstraintWeight getSingleConstraintMatchWeight(
 158       AsmOperandInfo &info, const char *constraint) const;
 159
 160     std::pair<unsigned, const TargetRegisterClass*>
 161               getRegForInlineAsmConstraint(const std::string &Constraint,
 162               EVT VT) const;
 163
 164     std::vector<unsigned>
 165     getRegClassForInlineAsmConstraint(const std::string &Constraint,
 166               EVT VT) const;
 167
 168     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
 169
 170     /// isFPImmLegal - Returns true if the target can instruction select the
 171     /// specified FP immediate natively. If false, the legalizer will
 172     /// materialize the FP immediate as a load from a constant pool.
 173     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
 174     SDValue LowerGlobalAddress(SDValue Op,
 175                                                        SelectionDAG &DAG)  const;
 176   };
 177 }
 178
 179 #endif // ZPUISELLOWERING_H