Fixed some bugs in register stack pass.

[llvm/zpu.git] / test / CodeGen / CellSPU / fcmp64.ll

; RUN: llc < %s -march=cellspu > %t1.s

define i1 @fcmp_eq_setcc_f64(double %arg1, double %arg2) nounwind {
entry:
       %A = fcmp oeq double %arg1, %arg2
       ret i1 %A
}