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Fixed some bugs in register stack pass.
[llvm/zpu.git]
/
test
/
CodeGen
/
X86
/
sse-align-7.ll
blob
5784481c5ae9a29d6dcad2881d7ce5197da7d35c
1
; RUN: llc < %s -march=x86-64 | grep movaps | count 1
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define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
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store <2 x i64> %x, <2 x i64>* %p
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ret void
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}