Fixed some bugs in register stack pass.

[llvm/zpu.git] / test / CodeGen / X86 / sse-align-9.ll

; RUN: llc < %s -march=x86-64 | grep movup | count 2

define <4 x float> @foo(<4 x float>* %p) nounwind {
  %t = load <4 x float>* %p, align 4
  ret <4 x float> %t
}
define <2 x double> @bar(<2 x double>* %p) nounwind {
  %t = load <2 x double>* %p, align 8
  ret <2 x double> %t
}