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4 <head>
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10 <body>
13 Writing an LLVM Compiler Backend
14 </div>
16 <ol>
18 <ul>
23 </ul>
27 <ul>
31 </ul></li>
33 <ul>
37 </ul></li>
39 <ul>
41 <ul>
46 </ul></li>
48 </ul></li>
52 <ul>
55 </ul></li>
56 </ol>
61 </div>
63 <!-- *********************************************************************** -->
66 </div>
67 <!-- *********************************************************************** -->
71 <p>
72 This document describes techniques for writing compiler backends that convert
73 the LLVM Intermediate Representation (IR) to code for a specified machine or
74 other languages. Code intended for a specific machine can take the form of
75 either assembly code or binary code (usable for a JIT compiler).
76 </p>
78 <p>
79 The backend of LLVM features a target-independent code generator that may create
80 output for several types of target CPUs — including X86, PowerPC, Alpha,
81 and SPARC. The backend may also be used to generate code targeted at SPUs of the
82 Cell processor or GPUs to support the execution of compute kernels.
83 </p>
85 <p>
86 The document focuses on existing examples found in subdirectories
88 document focuses on the example of creating a static compiler (one that emits
89 text assembly) for a SPARC target, because SPARC has fairly standard
90 characteristics, such as a RISC instruction set and straightforward calling
91 conventions.
92 </p>
94 </div>
98 </div>
102 <p>
103 The audience for this document is anyone who needs to write an LLVM backend to
104 generate code for a specific hardware or software target.
105 </p>
107 </div>
111 </div>
115 <p>
116 These essential documents must be read before reading this document:
117 </p>
119 <ul>
125 (classes and code generation algorithms) for translating the LLVM internal
126 representation into machine code for a specified target. Pay particular
127 attention to the descriptions of code generation stages: Instruction
128 Selection, Scheduling and Formation, SSA-based Optimization, Register
129 Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations,
130 and Code Emission.</li>
135 support LLVM code generation. TableGen processes input from a target
137 used for code generation.</li>
141 several SelectionDAG processing steps.</li>
142 </ul>
144 <p>
145 To follow the SPARC examples in this document, have a copy of
149 Reference Manual</a></i>. For more about the GNU Assembler format
153 machine dependent features.
154 </p>
156 </div>
160 </div>
164 <p>
165 To write a compiler backend for LLVM that converts the LLVM IR to code for a
166 specified target (machine or other language), follow these steps:
167 </p>
169 <ul>
170 <li>Create a subclass of the TargetMachine class that describes characteristics
171 of your target machine. Copy existing examples of specific TargetMachine
172 class and header files; for example, start with
174 change the file names for your target. Similarly, change code that
177 <li>Describe the register set of the target. Use TableGen to generate code for
178 register definition, register aliases, and register classes from a
180 additional code for a subclass of the TargetRegisterInfo class that
181 represents the class register file data used for register allocation and
182 also describes the interactions between registers.</li>
184 <li>Describe the instruction set of the target. Use TableGen to generate code
185 for target-specific instructions from target-specific versions of
187 write additional code for a subclass of the TargetInstrInfo class to
188 represent machine instructions supported by the target machine. </li>
190 <li>Describe the selection and conversion of the LLVM IR from a Directed Acyclic
191 Graph (DAG) representation of instructions to native target-specific
192 instructions. Use TableGen to generate code that matches patterns and
193 selects instructions based on additional information in a target-specific
196 to perform pattern matching and DAG-to-DAG instruction selection. Also write
198 data types that are not supported natively in a SelectionDAG. </li>
200 <li>Write code for an assembly printer that converts LLVM IR to a GAS format for
201 your target machine. You should add assembly strings to the instructions
203 should also write code for a subclass of AsmPrinter that performs the
204 LLVM-to-assembly conversion and a trivial subclass of TargetAsmInfo.</li>
206 <li>Optionally, add support for subtargets (i.e., variants with different
207 capabilities). You should also write code for a subclass of the
211 <li>Optionally, add JIT support and create a machine code emitter (subclass of
212 TargetJITInfo) that is used to emit binary code directly into memory. </li>
213 </ul>
215 <p>
217 then implement them later. Initially, you may not know which private members
218 that the class will need and which components will need to be subclassed.
219 </p>
221 </div>
225 </div>
229 <p>
230 To actually create your compiler backend, you need to create and modify a few
231 files. The absolute minimum is discussed here. But to actually use the LLVM
232 target-independent code generator, you must perform the steps described in
234 Target-Independent Code Generator</a> document.
235 </p>
237 <p>
239 the files related to your target. If your target is called "Dummy," create the
241 </p>
243 <p>
244 In this new
253 target).
254 </p>
256 <p>
260 </p>
262 <p>
263 To make your target actually do something, you need to implement a subclass of
267 target independent code generator, you should do what all current machine
270 </p>
272 <p>
273 To get LLVM to actually build and link your target, you need to add it to
277 target to the lists there (some creativity required), and then
280 </p>
282 </div>
284 <!-- *********************************************************************** -->
287 </div>
288 <!-- *********************************************************************** -->
292 <p>
295 class should be specialized by a concrete target class that implements the
299 processes numerous command-line options.
300 </p>
302 <p>
305 should name the files that you create to reflect your specific target. For
308 </p>
310 <p>
318 characteristics, such as data type size and alignment requirements.
319 </p>
321 <p>
322 For instance, for the SPARC target, the header file
325 </p>
328 <pre>
329 namespace llvm {
331 class Module;
333 class SparcTargetMachine : public LLVMTargetMachine {
334 const TargetData DataLayout; // Calculates type size & alignment
335 SparcSubtarget Subtarget;
336 SparcInstrInfo InstrInfo;
337 TargetFrameInfo FrameInfo;
339 protected:
340 virtual const TargetAsmInfo *createTargetAsmInfo() const;
342 public:
345 virtual const SparcInstrInfo *getInstrInfo() const {return &InstrInfo; }
346 virtual const TargetFrameInfo *getFrameInfo() const {return &FrameInfo; }
347 virtual const TargetSubtarget *getSubtargetImpl() const{return &Subtarget; }
348 virtual const TargetRegisterInfo *getRegisterInfo() const {
349 return &InstrInfo.getRegisterInfo();
350 }
351 virtual const TargetData *getTargetData() const { return &DataLayout; }
352 static unsigned getModuleMatchQuality(const Module &M);
354 // Pass Pipeline Configuration
355 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
356 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
357 };
359 } // end namespace llvm
360 </pre>
361 </div>
363 </div>
368 <ul>
374 </ul>
378 <ul>
381 </ul>
383 <p>
386 machine, including characteristics such as pointer size, alignment, and
387 endianness. For example, the constructor for SparcTargetMachine contains the
388 following:
389 </p>
392 <pre>
394 : DataLayout("E-p:32:32-f128:128:128"),
395 Subtarget(M, FS), InstrInfo(Subtarget),
397 }
398 </pre>
399 </div>
401 </div>
407 <ul>
412 preferred alignment. If only two figures follow "<tt>p:</tt>", then the
413 first value is pointer size, and the second value is both ABI and preferred
414 alignment.</li>
419 followed by ABI alignment and preferred alignment. "<tt>f</tt>" is followed
420 by three values: the first indicates the size of a long double, then ABI
421 alignment, and then ABI preferred alignment.</li>
422 </ul>
424 </div>
426 <!-- *********************************************************************** -->
429 </div>
430 <!-- *********************************************************************** -->
434 <p>
436 what other LLVM tools use to be able to lookup and use your target at
438 there are helper templates which should take care of the work for you.</p>
440 <p>
442 represent the target during registration. Then, in the target's TargetInfo
443 library, the target should define that object and use
444 the <tt>RegisterTarget</tt> template to register the target. For example, the Sparc registration code looks like this:
445 </p>
448 <pre>
449 Target llvm::TheSparcTarget;
451 extern "C" void LLVMInitializeSparcTargetInfo() {
454 }
455 </pre>
456 </div>
458 <p>
460 target triple. In addition, most targets will also register additional features
461 which are available in separate libraries. These registration steps are
462 separate, because some clients may wish to only link in some parts of the target
463 -- the JIT code generator does not require the use of the assembler printer, for
464 example. Here is an example of registering the Sparc assembly printer:
465 </p>
468 <pre>
469 extern "C" void LLVMInitializeSparcAsmPrinter() {
471 }
472 </pre>
473 </div>
475 <p>
476 For more information, see
478 </p>
480 </div>
482 <!-- *********************************************************************** -->
485 </div>
486 <!-- *********************************************************************** -->
490 <p>
491 You should describe a concrete target-specific class that represents the
494 file data that is used for register allocation. It also describes the
495 interactions between registers.
496 </p>
498 <p>
499 You also need to define register classes to categorize related registers. A
500 register class should be added for groups of registers that are all treated the
501 same way for some instruction. Typical examples are register classes for
502 integer, floating-point, or vector registers. A register allocator allows an
503 instruction to use any register in a specified register class to perform the
504 instruction in a similar manner. Register classes allocate virtual registers to
505 instructions from these sets, and register classes let the target-independent
506 register allocator automatically choose the actual registers.
507 </p>
509 <p>
510 Much of the code for registers, including register definition, register aliases,
515 </p>
517 </div>
519 <!-- ======================================================================= -->
522 </div>
526 <p>
532 specify any aliases.
533 </p>
536 <pre>
538 string Namespace = "";
539 string AsmName = n;
540 string Name = n;
541 int SpillSize = 0;
542 int SpillAlignment = 0;
546 }
547 </pre>
548 </div>
550 <p>
552 definitions that utilize the Register class, such as:
553 </p>
556 <pre>
558 </pre>
559 </div>
561 <p>
564 information writer to identify a register. For register
566 different modes: the first element is for X86-64, the second for exception
568 that indicates the gcc number is undefined, and -2 indicates the register number
569 is invalid for this mode.
570 </p>
572 <p>
575 </p>
578 <pre>
579 static const unsigned GR8[] = { X86::AL, ... };
581 const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
583 const TargetRegisterDesc RegisterDescriptors[] = {
584 ...
586 </pre>
587 </div>
589 <p>
593 </p>
596 <pre>
597 struct TargetRegisterDesc {
598 const char *AsmName; // Assembly language name for the register
599 const char *Name; // Printable name for the reg (for debugging)
600 const unsigned *AliasSet; // Register Alias Set
601 const unsigned *SubRegs; // Sub-register set
602 const unsigned *ImmSubRegs; // Immediate sub-register set
603 const unsigned *SuperRegs; // Super-register set
604 };</pre>
605 </div>
607 <p>
612 example, other definitions establish the registers "<tt>AX</tt>",
615 set.
616 </p>
618 <p>
623 </p>
626 <pre>
627 class RegisterWithSubRegs<string n,
629 let SubRegs = subregs;
630 }
631 </pre>
632 </div>
634 <p>
638 numbers, which is a feature common to these subclasses. Note the use of
641 </p>
644 <pre>
647 let Namespace = "SP";
648 }
649 // Ri - 32-bit integer registers
652 let Num = num;
653 }
654 // Rf - 32-bit floating-point registers
657 let Num = num;
658 }
659 // Rd - Slots in the FP register file for 64-bit
660 floating-point values.
663 let Num = num;
664 let SubRegs = subregs;
665 }
666 </pre>
667 </div>
669 <p>
672 </p>
675 <pre>
679 ...
684 ...
689 </pre>
690 </div>
692 <p>
694 double-precision floating-point registers that are aliases for pairs of
695 single-precision floating-point sub-registers. In addition to aliases, the
696 sub-register and super-register relationships of the defined register are in
697 fields of a register's TargetRegisterDesc.
698 </p>
700 </div>
702 <!-- ======================================================================= -->
705 </div>
709 <p>
711 define an object that represents a group of related registers and also defines
712 the default allocation order of the registers. A target description file
714 classes using the following class:
715 </p>
718 <pre>
719 class RegisterClass<string namespace,
722 string Namespace = namespace;
724 int Size = 0; // spill size, in bits; zero lets tblgen pick the size
725 int Alignment = alignment;
727 // CopyCost is the cost of copying a value between two registers
728 // default value 1 means a single instruction
729 // A negative value means copying is extremely expensive or impossible
730 int CopyCost = 1;
733 // for register classes that are subregisters of this class
736 code MethodProtos = [{}]; // to insert arbitrary code
737 code MethodBodies = [{}];
738 }
739 </pre>
740 </div>
744 <ul>
754 data in different configurations. For example a register that can process a
759 alignment required of the registers when they are stored or loaded to
760 memory.</li>
765 register allocator.</li>
766 </ul>
768 <p>
771 classes, the first argument defines the namespace with the string
774 a group of 16 double-precision registers
777 code into generated output.
778 </p>
781 <pre>
783 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,
784 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
787 [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15]>;
788
790 [L0, L1, L2, L3, L4, L5, L6, L7,
791 I0, I1, I2, I3, I4, I5,
792 O0, O1, O2, O3, O4, O5, O7,
793 G1,
794 // Non-allocatable regs:
795 G2, G3, G4,
796 O6, // stack ptr
797 I6, // frame ptr
798 I7, // return address
799 G0, // constant zero
800 G5, G6, G7 // reserved for kernel
801 ]> {
802 let MethodProtos = [{
803 iterator allocation_order_end(const MachineFunction &MF) const;
804 }];
805 let MethodBodies = [{
806 IntRegsClass::iterator
807 IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
808 return end() - 10 // Don't allocate special registers
809 -1;
810 }
811 }];
812 }
813 </pre>
814 </div>
816 <p>
818 that are intended for inclusion in other source code that you write.
820 which should be included in the header file for the implementation of the SPARC
824 base. It also specifies types, based upon the defined register
826 </p>
828 <p>
831 register implementation. The code below shows only the generated integer
832 registers and associated register classes. The order of registers
834 the target description file. Take special note of the use
838 </p>
841 <pre> // IntRegs Register Class...
842 static const unsigned IntRegs[] = {
843 SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5,
844 SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3,
845 SP::I4, SP::I5, SP::O0, SP::O1, SP::O2, SP::O3,
846 SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3,
847 SP::G4, SP::O6, SP::I6, SP::I7, SP::G0, SP::G5,
848 SP::G6, SP::G7,
849 };
851 // IntRegsVTs Register Class Value Types...
852 static const MVT::ValueType IntRegsVTs[] = {
853 MVT::i32, MVT::Other
854 };
856 namespace SP { // Register class instances
857 DFPRegsClass DFPRegsRegClass;
858 FPRegsClass FPRegsRegClass;
859 IntRegsClass IntRegsRegClass;
860 ...
861 // IntRegs Sub-register Classess...
862 static const TargetRegisterClass* const IntRegsSubRegClasses [] = {
863 NULL
864 };
865 ...
866 // IntRegs Super-register Classess...
867 static const TargetRegisterClass* const IntRegsSuperRegClasses [] = {
868 NULL
869 };
870 ...
871 // IntRegs Register Class sub-classes...
872 static const TargetRegisterClass* const IntRegsSubclasses [] = {
873 NULL
874 };
875 ...
876 // IntRegs Register Class super-classes...
877 static const TargetRegisterClass* const IntRegsSuperclasses [] = {
878 NULL
879 };
880 ...
881 IntRegsClass::iterator
882 IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
883 return end()-10 // Don't allocate special registers
884 -1;
885 }
887 IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID,
888 IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses,
890 }
891 </pre>
892 </div>
894 </div>
896 <!-- ======================================================================= -->
900 </div>
904 <p>
908 overridden. Here is a list of functions that are overridden for the SPARC
910 </p>
912 <ul>
914 in the order of the desired callee-save stack frame offset.</li>
917 register numbers, indicating if a particular register is unavailable.</li>
920 a dedicated frame pointer register.</li>
923 destroy pseudo instructions are used, this can be called to eliminate
924 them.</li>
927 instructions that may use them.</li>
932 </ul>
934 </div>
936 <!-- *********************************************************************** -->
939 </div>
941 <!-- *********************************************************************** -->
944 <p>
945 During the early stages of code generation, the LLVM IR code is converted to a
948 requirements, and operation properties. For example, is an operation
949 commutative, does an operation load from memory. The various operation node
952 </p>
954 <p>
956 generate much of the code for instruction definition:
957 </p>
959 <ul>
971 target-specific instructions.</li>
974 templates, condition codes, and instructions of an instruction set. For
975 architecture modifications, a different file name may be used. For example,
978 </ul>
980 <p>
983 input files, but its contents are only directly important for subtargets.
984 </p>
986 <p>
988 represents machine instructions supported by a target machine.
990 each of which describes one instruction. An instruction descriptor defines:</p>
992 <ul>
1002 </ul>
1004 <p>
1006 for more complex instruction classes.
1007 </p>
1010 <pre>class Instruction {
1011 string Namespace = "";
1012 dag OutOperandList; // An dag containing the MI def operand list.
1013 dag InOperandList; // An dag containing the MI use operand list.
1014 string AsmString = ""; // The .s format to print the instruction with.
1019 ... remainder not shown for space ...
1020 }
1021 </pre>
1022 </div>
1024 <p>
1026 representing a target-specific instruction that is defined
1028 instructions from the architecture manual of the target machine (such as the
1029 SPARC Architecture Manual for the SPARC target).
1030 </p>
1032 <p>
1033 A single instruction from the architecture manual is often modeled as multiple
1034 target instructions, depending upon its operands. For example, a manual might
1035 describe an add instruction that takes a register or an immediate operand. An
1038 </p>
1040 <p>
1041 You should define a class for each instruction category and define each opcode
1042 as a subclass of the category with appropriate parameters such as the fixed
1043 binary encoding of opcodes and extended opcodes. You should map the register
1044 bits to the bits of the instruction in which they are encoded (for the
1045 JIT). Also you should specify how the instruction should be printed when the
1046 automatic assembly printer is used.
1047 </p>
1049 <p>
1050 As is described in the SPARC Architecture Manual, Version 8, there are three
1053 high bits of a register) instructions. Format 3 is for other instructions.
1054 </p>
1056 <p>
1059 classes are specified for more precise formats: for example
1065 synthetic SPARC instructions.
1066 </p>
1068 <p>
1074 operation value for this category of operation. The second parameter
1079 </p>
1083 "ld [$addr], $dst",
1084 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
1085 </pre>
1086 </div>
1088 <p>
1089 The fourth parameter is the input source, which uses the address
1091 </p>
1095 let PrintMethod = "printMemOperand";
1096 let MIOperandInfo = (ops IntRegs, IntRegs);
1097 }
1098 </pre>
1099 </div>
1101 <p>
1102 The fifth parameter is a string that is used by the assembly printer and can be
1103 left as an empty string until the assembly printer interface is implemented. The
1104 sixth and final parameter is the pattern used to match the instruction during
1105 the SelectionDAG Select Phase described in
1107 Target-Independent Code Generator</a>). This parameter is detailed in the next
1109 </p>
1111 <p>
1112 Instruction class definitions are not overloaded for different operand types, so
1113 separate versions of instructions are needed for register, memory, or immediate
1114 value operands. For example, to perform a Load Integer instruction for a Word
1115 from an immediate operand to a register, the following instruction class is
1116 defined:
1117 </p>
1121 "ld [$addr], $dst",
1122 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
1123 </pre>
1124 </div>
1126 <p>
1127 Writing these definitions for so many similar instructions can involve a lot of
1129 creation of templates to define several instruction classes at once (using
1133 </p>
1138 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1139 !strconcat(OpcStr, " $b, $c, $dst"),
1140 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
1142 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
1143 !strconcat(OpcStr, " $b, $c, $dst"),
1144 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
1145 }
1146 </pre>
1147 </div>
1149 <p>
1153 </p>
1156 <pre>
1159 </pre>
1160 </div>
1162 <p>
1164 are referenced by branch instructions. The following definitions
1168 than' condition for floats.
1169 </p>
1172 <pre>
1176 ...
1180 ...
1181 </pre>
1182 </div>
1184 <p>
1189 </p>
1191 </div>
1193 <!-- ======================================================================= -->
1196 </div>
1200 <p>
1201 The code generator backend maps instruction operands to fields in the
1202 instruction. Operands are assigned to unbound fields in the instruction in the
1203 order they are defined. Fields are bound when they are assigned a value. For
1206 </p>
1209 <pre>
1211 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1212 "xnor $b, $c, $dst",
1213 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
1214 </pre>
1215 </div>
1217 <p>
1220 </p>
1223 <pre>
1226 let Namespace = "SP";
1229 dag OutOperandList = outs;
1230 dag InOperandList = ins;
1231 let AsmString = asmstr;
1232 let Pattern = pattern;
1233 }
1234 </pre>
1235 </div>
1240 <pre>
1250 }
1251 </pre>
1252 </div>
1254 <p>
1258 </p>
1261 <pre>
1266 let op = opVal;
1267 let op3 = op3val;
1271 }
1272 </pre>
1273 </div>
1275 <p>
1281 </p>
1283 </div>
1285 <!-- ======================================================================= -->
1289 </div>
1293 <p>
1297 overridden. Here's a list of functions that are overridden for the SPARC
1299 </p>
1301 <ul>
1303 a direct load from a stack slot, return the register number of the
1307 a direct store to a stack slot, return the register number of the
1311 registers.</li>
1314 slot.</li>
1317 slot.</li>
1324 load or store instruction for the specified operand(s).</li>
1325 </ul>
1327 </div>
1329 <!-- ======================================================================= -->
1332 </div>
1335 <p>
1336 Performance can be improved by combining instructions or by eliminating
1340 a machine basic block (MBB) for opportunities for improvement, such as branch
1345 instructions.
1346 </p>
1348 <p>
1352 implementation is shown below.
1353 </p>
1357 <ul>
1359 examined.</li>
1363 the destination.</li>
1369 operands to evaluate a condition for a conditional branch.</li>
1370 </ul>
1372 <p>
1373 In the simplest case, if a block ends without a branch, then it falls through to
1377 function parameters and the code for the simplest case.
1378 </p>
1384 {
1385 MachineBasicBlock::iterator I = MBB.end();
1386 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
1387 return false;
1388 </pre>
1389 </div>
1391 <p>
1392 If a block ends with a single unconditional branch instruction, then
1395 </p>
1398 <pre>
1399 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
1401 return false;
1402 }
1403 </pre>
1404 </div>
1406 <p>
1407 If a block ends with two unconditional branches, then the second branch is never
1408 reached. In that situation, as shown below, remove the last branch instruction
1410 </p>
1413 <pre>
1414 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
1415 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
1417 I = LastInst;
1418 I->eraseFromParent();
1419 return false;
1420 }
1421 </pre>
1422 </div>
1424 <p>
1425 A block may end with a single conditional branch instruction that falls through
1426 to successor block if the condition evaluates to false. In that case,
1430 </p>
1433 <pre>
1434 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
1435 // Block ends with fall-through condbranch.
1439 return false;
1440 }
1441 </pre>
1442 </div>
1444 <p>
1445 If a block ends with both a conditional branch and an ensuing unconditional
1447 branch destination (assuming it corresponds to a conditional evaluation of
1452 </p>
1455 <pre>
1456 unsigned SecondLastOpc = SecondLastInst->getOpcode();
1458 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
1459 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
1464 return false;
1465 }
1466 </pre>
1467 </div>
1469 <p>
1470 For the last two cases (ending with a single conditional branch or ending with
1471 one conditional and one unconditional branch), the operands returned in
1473 create new branches or perform other operations. An implementation
1476 </p>
1478 <p>
1482 return true if it encounters a terminator it cannot handle, such as an indirect
1483 branch.
1484 </p>
1486 </div>
1488 <!-- *********************************************************************** -->
1491 </div>
1492 <!-- *********************************************************************** -->
1496 <p>
1499 instructions. During code generation, instruction selection passes are performed
1500 to convert non-native DAG instructions into native target-specific
1502 match patterns and perform DAG-to-DAG instruction selection. Optionally, a pass
1504 operations for branch instructions. Later, the code in
1507 </p>
1509 <p>
1510 TableGen generates code for instruction selection using the following target
1511 description input files:
1512 </p>
1514 <ul>
1520 conventions for the target architecture, and it generates
1523 </ul>
1525 <p>
1526 The implementation of an instruction selection pass must include a header that
1529 selection pass into the queue of passes to run.
1530 </p>
1532 <p>
1537 SelectionDAG Instruction Selection Process</a>.
1538 </p>
1540 <p>
1541 To describe instruction selector behavior, you should add patterns for lowering
1545 the last parameter describes a pattern with the store DAG operator.
1546 </p>
1549 <pre>
1552 </pre>
1553 </div>
1555 <p>
1558 </p>
1561 <pre>
1563 </pre>
1564 </div>
1566 <p>
1568 function defined in an implementation of the Instructor Selector (such
1570 </p>
1572 <p>
1574 defined below:
1575 </p>
1578 <pre>
1579 def store : PatFrag<(ops node:$val, node:$ptr),
1580 (st node:$val, node:$ptr), [{
1583 ST->getAddressingMode() == ISD::UNINDEXED;
1584 return false;
1585 }]>;
1586 </pre>
1587 </div>
1589 <p>
1594 </p>
1597 <pre>
1598 SDNode *SelectCode(SDValue N) {
1599 ...
1601 switch (N.getOpcode()) {
1602 case ISD::STORE: {
1603 switch (NVT) {
1604 default:
1605 return Select_ISD_STORE(N);
1606 break;
1607 }
1608 break;
1609 }
1610 ...
1611 </pre>
1612 </div>
1614 <p>
1619 instruction.
1620 </p>
1623 <pre>
1624 SDNode *Select_ISD_STORE(const SDValue &N) {
1625 SDValue Chain = N.getOperand(0);
1626 if (Predicate_store(N.getNode())) {
1627 SDValue N1 = N.getOperand(1);
1628 SDValue N2 = N.getOperand(2);
1629 SDValue CPTmp0;
1630 SDValue CPTmp1;
1632 // Pattern: (st:void IntRegs:i32:$src,
1634 // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
1636 if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &&
1639 return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
1640 }
1641 ...
1642 </pre>
1643 </div>
1645 </div>
1647 <!-- ======================================================================= -->
1650 </div>
1654 <p>
1655 The Legalize phase converts a DAG to use types and operations that are natively
1656 supported by the target. For natively unsupported types and operations, you need
1657 to add code to the target-specific XXXTargetLowering implementation to convert
1658 unsupported types and operations to supported ones.
1659 </p>
1661 <p>
1664 register classes are associated with them. The code for the register classes are
1667 constructor for the SparcTargetLowering class (in
1669 </p>
1672 <pre>
1673 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
1674 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
1675 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
1676 </pre>
1677 </div>
1679 <p>
1683 native support, add a callback to the constructor for the XXXTargetLowering
1684 class, so the instruction selection process knows what to do. The TargetLowering
1686 </p>
1688 <ul>
1702 </ul>
1704 <p>
1708 to see what methods are specifically supported.
1709 </p>
1711 <p>
1712 These callbacks are used to determine that an operation does or does not work
1713 with a specified type (or types). And in all cases, the third parameter is
1717 </p>
1719 </div>
1721 <!-- _______________________________________________________________________ -->
1724 </div>
1728 <p>
1729 For an operation without native support for a given type, the specified type may
1730 be promoted to a larger type that is supported. For example, SPARC does not
1734 </p>
1737 <pre>
1738 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1739 </pre>
1740 </div>
1742 </div>
1744 <!-- _______________________________________________________________________ -->
1747 </div>
1751 <p>
1752 For a type without native support, a value may need to be broken down further,
1753 rather than promoted. For an operation without native support, a combination of
1754 other operations may be used to similar effect. In SPARC, the floating-point
1755 sine and cosine trig operations are supported by expansion to other operations,
1758 </p>
1761 <pre>
1762 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1763 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1764 </pre>
1765 </div>
1767 </div>
1769 <!-- _______________________________________________________________________ -->
1772 </div>
1776 <p>
1777 For some operations, simple type promotion or operation expansion may be
1778 insufficient. In some cases, a special intrinsic function must be implemented.
1779 </p>
1781 <p>
1782 For example, a constant value may require special treatment, or an operation may
1783 require spilling and restoring registers in the stack and working with register
1784 allocators.
1785 </p>
1787 <p>
1789 conversion from a floating point value to a signed integer, first the
1791 parameter:
1792 </p>
1795 <pre>
1796 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1797 </pre>
1798 </div>
1800 <p>
1802 case statement should be added to indicate what function to call. In the
1805 </p>
1808 <pre>
1809 SDValue SparcTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1810 switch (Op.getOpcode()) {
1811 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1812 ...
1813 }
1814 }
1815 </pre>
1816 </div>
1818 <p>
1820 register to convert the floating-point value to an integer.
1821 </p>
1824 <pre>
1825 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
1826 assert(Op.getValueType() == MVT::i32);
1827 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
1828 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1829 }
1830 </pre>
1831 </div>
1833 </div>
1835 <!-- _______________________________________________________________________ -->
1838 </div>
1842 <p>
1847 natively supported only for SPARC v9. The following code enables
1849 </p>
1852 <pre>
1853 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1854 ...
1856 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1857 case ISD::SETULT: return SPCC::ICC_CS;
1858 case ISD::SETULE: return SPCC::ICC_LEU;
1859 case ISD::SETUGT: return SPCC::ICC_GU;
1860 case ISD::SETUGE: return SPCC::ICC_CC;
1861 }
1862 }
1863 </pre>
1864 </div>
1866 </div>
1868 <!-- ======================================================================= -->
1871 </div>
1875 <p>
1877 uses interfaces (such as CCIfType and CCAssignToReg) that are defined in
1883 </p>
1885 <ul>
1888 <li>Where parameters and return values are placed (that is, on the stack or in
1889 registers).</li>
1894 </ul>
1896 <p>
1903 </p>
1906 <pre>
1908 </pre>
1909 </div>
1911 <p>
1913 return-value calling convention (RetCC_Sparc32) and a basic 32-bit C calling
1915 (shown below) indicates which registers are used for specified scalar return
1919 </p>
1922 <pre>
1923 def RetCC_Sparc32 : CallingConv<[
1927 ]>;
1928 </pre>
1929 </div>
1931 <p>
1934 specified size and alignment. In the example below, the first parameter, 4,
1935 indicates the size of the slot, and the second parameter, also 4, indicates the
1936 stack alignment along 4-byte units. (Special cases: if size is zero, then the
1937 ABI size is used; if alignment is zero, then the ABI alignment is used.)
1938 </p>
1941 <pre>
1942 def CC_Sparc32 : CallingConv<[
1943 // All arguments get passed in integer registers if there is space.
1946 ]>;
1947 </pre>
1948 </div>
1950 <p>
1952 specified sub-calling convention, and, if a match is found, it is invoked. In
1957 </p>
1960 <pre>
1961 def RetCC_X86_32_C : CallingConv<[
1965 ]>;
1966 </pre>
1967 </div>
1969 <p>
1971 current calling convention. If the name identifies the current calling
1972 convention, then a specified action is invoked. In the following example (in
1976 </p>
1979 <pre>
1980 def RetCC_X86_32 : CallingConv<[
1984 ]>;
1985 </pre>
1986 </div>
1990 <ul>
1992 apply the action.</li>
2001 not take a variable number of arguments, apply the action.</li>
2007 slot with the minimum specified size and alignment.</li>
2010 the specified type.</li>
2013 convention that is supported.</li>
2014 </ul>
2016 </div>
2018 <!-- *********************************************************************** -->
2021 </div>
2022 <!-- *********************************************************************** -->
2026 <p>
2027 During the code emission stage, the code generator may utilize an LLVM pass to
2028 produce assembly output. To do this, you want to implement the code for a
2029 printer that converts LLVM IR to a GAS-format assembly language for your target
2030 machine, using the following steps:
2031 </p>
2033 <ul>
2034 <li>Define all the assembly strings for your target, adding them to the
2046 methods.</li>
2049 class that performs the LLVM-to-assembly conversion.</li>
2050 </ul>
2052 <p>
2058 </p>
2061 <pre>
2062 SparcTargetAsmInfo::SparcTargetAsmInfo(const SparcTargetMachine &TM) {
2063 Data16bitsDirective = "\t.half\t";
2064 Data32bitsDirective = "\t.word\t";
2065 Data64bitsDirective = 0; // .xword is only supported by V9.
2066 ZeroDirective = "\t.skip\t";
2067 CommentString = "!";
2069 }
2070 </pre>
2071 </div>
2073 <p>
2077 </p>
2079 <p>
2080 A target-specific implementation of AsmPrinter is written in
2082 converts the LLVM to printable assembly. The implementation must include the
2086 </p>
2089 <pre>
2090 #include "llvm/CodeGen/AsmPrinter.h"
2091 #include "llvm/CodeGen/MachineFunctionPass.h"
2092 </pre>
2093 </div>
2095 <p>
2099 variable names.
2100 </p>
2102 <p>
2108 generally do the following to process each machine function:
2109 </p>
2111 <ul>
2115 which have been spilled to memory.</li>
2118 function.</li>
2122 <li>Print out the code for the function, including basic block labels and the
2124 </ul>
2126 <p>
2131 </p>
2133 <ul>
2147 </ul>
2149 <p>
2152 generally adequate for printing assembly and do not need to be
2153 overridden.
2154 </p>
2156 <p>
2158 statement for the type of operand: register, immediate, basic block, external
2159 symbol, global address, constant pool index, or jump table index. For an
2161 should be implemented to generate the proper output. Similarly,
2163 </p>
2166 it should be called to shut down the assembly printer. During
2168 output.
2169 </p>
2171 </div>
2173 <!-- *********************************************************************** -->
2176 </div>
2177 <!-- *********************************************************************** -->
2181 <p>
2182 Subtarget support is used to inform the code generation process of instruction
2183 set variations for a given chip set. For example, the LLVM SPARC implementation
2184 provided covers three major versions of the SPARC microprocessor architecture:
2186 architecture), and the UltraSPARC architecture. V8 has 16 double-precision
2188 quad-precision registers. V8 is also purely big-endian. V9 has 32
2189 double-precision floating-point registers that are also usable as 16
2190 quad-precision registers, but cannot be used as single-precision registers. The
2191 UltraSPARC architecture combines V9 with UltraSPARC Visual Instruction Set
2192 extensions.
2193 </p>
2195 <p>
2196 If subtarget support is needed, you should implement a target-specific
2197 XXXSubtarget class for your architecture. This class should process the
2199 </p>
2201 <p>
2206 attribute set by the feature, the value of the attribute, and a description of
2207 the feature. (The fifth parameter is a list of features whose presence is
2208 implied, and its default value is an empty array.)
2209 </p>
2212 <pre>
2213 class SubtargetFeature<string n, string a, string v, string d,
2215 string Name = n;
2216 string Attribute = a;
2217 string Value = v;
2218 string Desc = d;
2220 }
2221 </pre>
2222 </div>
2224 <p>
2226 following features.
2227 </p>
2230 <pre>
2238 </pre>
2239 </div>
2241 <p>
2243 define particular SPARC processor subtypes that may have the previously
2244 described features.
2245 </p>
2248 <pre>
2251
2265 </pre>
2266 </div>
2268 <p>
2270 SparcGenSubtarget.inc specifies enum values to identify the features, arrays of
2271 constants to represent the CPU features and CPU subtypes, and the
2272 ParseSubtargetFeatures method that parses the features string that sets
2275 implementation of the XXXSubtarget method should follow this pseudocode:
2276 </p>
2279 <pre>
2281 // Set the default features
2282 // Determine default and user specified characteristics of the CPU
2283 // Call ParseSubtargetFeatures(FS, CPU) to parse the features string
2284 // Perform any additional operations
2285 }
2286 </pre>
2287 </div>
2289 </div>
2291 <!-- *********************************************************************** -->
2294 </div>
2295 <!-- *********************************************************************** -->
2299 <p>
2300 The implementation of a target machine optionally includes a Just-In-Time (JIT)
2301 code generator that emits machine code and auxiliary structures as binary output
2302 that can be written directly to memory. To do this, implement JIT code
2303 generation by performing the following steps:
2304 </p>
2306 <ul>
2308 pass that transforms target-machine instructions into relocatable machine
2309 code.</li>
2312 target-specific code-generation activities, such as emitting machine code
2313 and stubs.</li>
2317 </ul>
2319 <p>
2320 There are several different approaches to writing the JIT support code. For
2321 instance, TableGen and target descriptor files may be used for creating a JIT
2322 code generator, but are not mandatory. For the Alpha and PowerPC target
2324 contains the binary coding of machine instructions and the
2326 implementations do not.
2327 </p>
2329 <p>
2333 that write data (in bytes, words, strings, etc.) to the output stream.
2334 </p>
2336 </div>
2338 <!-- ======================================================================= -->
2341 </div>
2345 <p>
2347 is implemented as a function pass (subclass
2353 implemented with case statements on the instruction types defined in
2356 statements:
2357 </p>
2360 <pre>
2362 case X86II::Pseudo: // for not yet implemented instructions
2363 ... // or pseudo-instructions
2364 break;
2365 case X86II::RawFrm: // for instructions with a fixed opcode value
2366 ...
2367 break;
2368 case X86II::AddRegFrm: // for instructions that have one register operand
2369 ... // added to their opcode
2370 break;
2371 case X86II::MRMDestReg:// for instructions that use the Mod/RM byte
2372 ... // to specify a destination (register)
2373 break;
2374 case X86II::MRMDestMem:// for instructions that use the Mod/RM byte
2375 ... // to specify a destination (memory)
2376 break;
2377 case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte
2378 ... // to specify a source (register)
2379 break;
2380 case X86II::MRMSrcMem: // for instructions that use the Mod/RM byte
2381 ... // to specify a source (memory)
2382 break;
2383 case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
2384 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
2385 case X86II::MRM4r: case X86II::MRM5r: // use the Mod/RM byte and a field
2386 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
2387 ...
2388 break;
2389 case X86II::MRM0m: case X86II::MRM1m: // for instructions that operate on
2390 case X86II::MRM2m: case X86II::MRM3m: // a MEMORY r/m operand and
2391 case X86II::MRM4m: case X86II::MRM5m: // use the Mod/RM byte and a field
2392 case X86II::MRM6m: case X86II::MRM7m: // to hold extended opcode data
2393 ...
2394 break;
2395 case X86II::MRMInitReg: // for instructions whose source and
2396 ... // destination are the same register
2397 break;
2398 }
2399 </pre>
2400 </div>
2402 <p>
2403 The implementations of these case statements often first emit the opcode and
2404 then get the operand(s). Then depending upon the operand, helper methods may be
2416 </p>
2419 <pre>
2420 case X86II::AddRegFrm:
2421 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
2423 if (CurOp != NumOps) {
2424 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2425 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2426 if (MO1.isImmediate())
2427 emitConstant(MO1.getImm(), Size);
2428 else {
2429 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
2430 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
2431 if (Opcode == X86::MOV64ri)
2432 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
2433 if (MO1.isGlobalAddress()) {
2435 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
2436 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
2437 NeedStub, isLazy);
2438 } else if (MO1.isExternalSymbol())
2439 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
2440 else if (MO1.isConstantPoolIndex())
2441 emitConstPoolAddress(MO1.getIndex(), rt);
2442 else if (MO1.isJumpTableIndex())
2443 emitJumpTableAddress(MO1.getIndex(), rt);
2444 }
2445 }
2446 break;
2447 </pre>
2448 </div>
2450 <p>
2453 relocate addresses (for example, a global address with a PIC base offset). The
2457 addresses for referenced global symbols.
2458 </p>
2460 <p>
2462 for the X86 addresses. In all four cases, the relocated value is added to the
2465 </p>
2468 <pre>
2469 enum RelocationType {
2470 reloc_pcrel_word = 0, // add reloc value after adjusting for the PC loc
2471 reloc_picrel_word = 1, // add reloc value after adjusting for the PIC base
2472 reloc_absolute_word = 2, // absolute relocation; no additional adjustment
2473 reloc_absolute_dword = 3 // absolute relocation; no additional adjustment
2474 };
2475 </pre>
2476 </div>
2478 </div>
2480 <!-- ======================================================================= -->
2483 </div>
2487 <p>
2489 code-generation activities, such as emitting machine code and stubs. At minimum,
2491 </p>
2493 <ul>
2495 target a function that is used for compilation.</li>
2498 address for a callback function.</li>
2501 on relocation types.</li>
2503 <li>Callback function that are wrappers to a function stub that is used when the
2504 real target is not initially known.</li>
2505 </ul>
2507 <p>
2510 callback function that will be used a function wrapper. For the Alpha target
2512 implementation is simply:
2513 </p>
2516 <pre>
2517 TargetJITInfo::LazyResolverFn AlphaJITInfo::getLazyResolverFunction(
2518 JITCompilerFn F) {
2519 JITCompilerFunction = F;
2520 return AlphaCompilationCallback;
2521 }
2522 </pre>
2523 </div>
2525 <p>
2527 little more complication, because it returns a different callback function for
2528 processors with SSE instructions and XMM registers.
2529 </p>
2531 <p>
2532 The callback function initially saves and later restores the callee register
2533 values, incoming arguments, and frame and return address. The callback function
2534 needs low-level access to the registers or stack, so it is typically implemented
2535 with assembler.
2536 </p>
2538 </div>
2540 <!-- *********************************************************************** -->
2542 <hr>
2543 <address>
2549 <a href="http://www.woo.com">Mason Woo</a> and <a href="http://misha.brukman.net">Misha Brukman</a><br>
2551 <br>
2552 Last modified: $Date$
2553 </address>
2555 </body>
2556 </html>