zpu: wip eke out some simple instructions for load/store/add
[llvm/zpu.git] / lib / Target / PowerPC / PPCCodeEmitter.cpp
blob5298dda6bee076576da68bfb01c36552e058b9cd
1 //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -------*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
11 // JIT-compile bitcode to native PowerPC.
13 //===----------------------------------------------------------------------===//
15 #include "PPCTargetMachine.h"
16 #include "PPCRelocations.h"
17 #include "PPC.h"
18 #include "llvm/Module.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/CodeGen/JITCodeEmitter.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetOptions.h"
27 using namespace llvm;
29 namespace {
30 class PPCCodeEmitter : public MachineFunctionPass {
31 TargetMachine &TM;
32 JITCodeEmitter &MCE;
33 MachineModuleInfo *MMI;
35 void getAnalysisUsage(AnalysisUsage &AU) const {
36 AU.addRequired<MachineModuleInfo>();
37 MachineFunctionPass::getAnalysisUsage(AU);
40 static char ID;
42 /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
43 /// its address in the function into this pointer.
44 void *MovePCtoLROffset;
45 public:
47 PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
48 : MachineFunctionPass(ID), TM(tm), MCE(mce) {}
50 /// getBinaryCodeForInstr - This function, generated by the
51 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
52 /// machine instructions.
54 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
56 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
58 unsigned getMachineOpValue(const MachineInstr &MI,
59 const MachineOperand &MO) const;
61 const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
63 /// runOnMachineFunction - emits the given MachineFunction to memory
64 ///
65 bool runOnMachineFunction(MachineFunction &MF);
67 /// emitBasicBlock - emits the given MachineBasicBlock to memory
68 ///
69 void emitBasicBlock(MachineBasicBlock &MBB);
73 char PPCCodeEmitter::ID = 0;
75 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
76 /// to the specified MCE object.
77 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
78 JITCodeEmitter &JCE) {
79 return new PPCCodeEmitter(TM, JCE);
82 bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
83 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
84 MF.getTarget().getRelocationModel() != Reloc::Static) &&
85 "JIT relocation model must be set to static or default!");
87 MMI = &getAnalysis<MachineModuleInfo>();
88 MCE.setModuleInfo(MMI);
89 do {
90 MovePCtoLROffset = 0;
91 MCE.startFunction(MF);
92 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
93 emitBasicBlock(*BB);
94 } while (MCE.finishFunction(MF));
96 return false;
99 void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
100 MCE.StartMachineBasicBlock(&MBB);
102 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
103 const MachineInstr &MI = *I;
104 MCE.processDebugLoc(MI.getDebugLoc(), true);
105 switch (MI.getOpcode()) {
106 default:
107 MCE.emitWordBE(getBinaryCodeForInstr(MI));
108 break;
109 case TargetOpcode::PROLOG_LABEL:
110 case TargetOpcode::EH_LABEL:
111 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
112 break;
113 case TargetOpcode::IMPLICIT_DEF:
114 case TargetOpcode::KILL:
115 break; // pseudo opcode, no side effects
116 case PPC::MovePCtoLR:
117 case PPC::MovePCtoLR8:
118 assert(TM.getRelocationModel() == Reloc::PIC_);
119 MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
120 MCE.emitWordBE(0x48000005); // bl 1
121 break;
123 MCE.processDebugLoc(MI.getDebugLoc(), false);
127 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
128 const MachineOperand &MO) const {
130 unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
131 // or things that get fixed up later by the JIT.
132 if (MO.isReg()) {
133 rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg());
135 // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
136 // register, not the register number directly.
137 if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
138 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
139 rv = 0x80 >> rv;
141 } else if (MO.isImm()) {
142 rv = MO.getImm();
143 } else if (MO.isGlobal() || MO.isSymbol() ||
144 MO.isCPI() || MO.isJTI()) {
145 unsigned Reloc = 0;
146 if (MI.getOpcode() == PPC::BL_Darwin || MI.getOpcode() == PPC::BL8_Darwin ||
147 MI.getOpcode() == PPC::BL_SVR4 || MI.getOpcode() == PPC::BL8_ELF ||
148 MI.getOpcode() == PPC::TAILB || MI.getOpcode() == PPC::TAILB8)
149 Reloc = PPC::reloc_pcrel_bx;
150 else {
151 if (TM.getRelocationModel() == Reloc::PIC_) {
152 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
154 switch (MI.getOpcode()) {
155 default: MI.dump(); llvm_unreachable("Unknown instruction for relocation!");
156 case PPC::LIS:
157 case PPC::LIS8:
158 case PPC::ADDIS:
159 case PPC::ADDIS8:
160 Reloc = PPC::reloc_absolute_high; // Pointer to symbol
161 break;
162 case PPC::LI:
163 case PPC::LI8:
164 case PPC::LA:
165 // Loads.
166 case PPC::LBZ:
167 case PPC::LBZ8:
168 case PPC::LHA:
169 case PPC::LHA8:
170 case PPC::LHZ:
171 case PPC::LHZ8:
172 case PPC::LWZ:
173 case PPC::LWZ8:
174 case PPC::LFS:
175 case PPC::LFD:
177 // Stores.
178 case PPC::STB:
179 case PPC::STB8:
180 case PPC::STH:
181 case PPC::STH8:
182 case PPC::STW:
183 case PPC::STW8:
184 case PPC::STFS:
185 case PPC::STFD:
186 Reloc = PPC::reloc_absolute_low;
187 break;
189 case PPC::LWA:
190 case PPC::LD:
191 case PPC::STD:
192 case PPC::STD_32:
193 Reloc = PPC::reloc_absolute_low_ix;
194 break;
198 MachineRelocation R;
199 if (MO.isGlobal()) {
200 R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
201 const_cast<GlobalValue *>(MO.getGlobal()), 0,
202 isa<Function>(MO.getGlobal()));
203 } else if (MO.isSymbol()) {
204 R = MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
205 Reloc, MO.getSymbolName(), 0);
206 } else if (MO.isCPI()) {
207 R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
208 Reloc, MO.getIndex(), 0);
209 } else {
210 assert(MO.isJTI());
211 R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
212 Reloc, MO.getIndex(), 0);
215 // If in PIC mode, we need to encode the negated address of the
216 // 'movepctolr' into the unrelocated field. After relocation, we'll have
217 // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
218 // field, we get &gv. This doesn't happen for branch relocations, which are
219 // always implicitly pc relative.
220 if (TM.getRelocationModel() == Reloc::PIC_ && Reloc != PPC::reloc_pcrel_bx){
221 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
222 R.setConstantVal(-(intptr_t)MovePCtoLROffset - 4);
224 MCE.addRelocation(R);
226 } else if (MO.isMBB()) {
227 unsigned Reloc = 0;
228 unsigned Opcode = MI.getOpcode();
229 if (Opcode == PPC::B || Opcode == PPC::BL_Darwin ||
230 Opcode == PPC::BLA_Darwin|| Opcode == PPC::BL_SVR4 ||
231 Opcode == PPC::BLA_SVR4)
232 Reloc = PPC::reloc_pcrel_bx;
233 else // BCC instruction
234 Reloc = PPC::reloc_pcrel_bcx;
236 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
237 Reloc, MO.getMBB()));
238 } else {
239 #ifndef NDEBUG
240 errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
241 #endif
242 llvm_unreachable(0);
245 return rv;
248 #include "PPCGenCodeEmitter.inc"