lib/Target/SystemZ/SystemZISelLowering.h

   1 //==-- SystemZISelLowering.h - SystemZ DAG Lowering Interface ----*- C++ -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
  16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
  17
  18 #include "SystemZ.h"
  19 #include "SystemZRegisterInfo.h"
  20 #include "llvm/CodeGen/SelectionDAG.h"
  21 #include "llvm/Target/TargetLowering.h"
  22
  23 namespace llvm {
  24   namespace SystemZISD {
  25     enum {
  26       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  27
  28       /// Return with a flag operand. Operand 0 is the chain operand.
  29       RET_FLAG,
  30
  31       /// CALL - These operations represent an abstract call
  32       /// instruction, which includes a bunch of information.
  33       CALL,
  34
  35       /// PCRelativeWrapper - PC relative address
  36       PCRelativeWrapper,
  37
  38       /// CMP, UCMP - Compare instruction
  39       CMP,
  40       UCMP,
  41
  42       /// BRCOND - Conditional branch. Operand 0 is chain operand, operand 1 is
  43       /// the block to branch if condition is true, operand 2 is condition code
  44       /// and operand 3 is the flag operand produced by a CMP instruction.
  45       BRCOND,
  46
  47       /// SELECT - Operands 0 and 1 are selection variables, operand 2 is
  48       /// condition code and operand 3 is the flag operand.
  49       SELECT
  50     };
  51   }
  52
  53   class SystemZSubtarget;
  54   class SystemZTargetMachine;
  55
  56   class SystemZTargetLowering : public TargetLowering {
  57   public:
  58     explicit SystemZTargetLowering(SystemZTargetMachine &TM);
  59
  60     /// LowerOperation - Provide custom lowering hooks for some operations.
  61     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  62
  63     /// getTargetNodeName - This method returns the name of a target specific
  64     /// DAG node.
  65     virtual const char *getTargetNodeName(unsigned Opcode) const;
  66
  67     /// getFunctionAlignment - Return the Log2 alignment of this function.
  68     virtual unsigned getFunctionAlignment(const Function *F) const {
  69       return 1;
  70     }
  71
  72     std::pair<unsigned, const TargetRegisterClass*>
  73     getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
  74     TargetLowering::ConstraintType
  75     getConstraintType(const std::string &Constraint) const;
  76
  77     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
  78     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
  79     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
  80     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
  81     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
  82
  83     SDValue EmitCmp(SDValue LHS, SDValue RHS,
  84                     ISD::CondCode CC, SDValue &SystemZCC,
  85                     SelectionDAG &DAG) const;
  86
  87
  88     MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
  89                                                    MachineBasicBlock *BB) const;
  90
  91     /// isFPImmLegal - Returns true if the target can instruction select the
  92     /// specified FP immediate natively. If false, the legalizer will
  93     /// materialize the FP immediate as a load from a constant pool.
  94     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
  95
  96   private:
  97     SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
  98                            CallingConv::ID CallConv, bool isVarArg,
  99                            bool isTailCall,
 100                            const SmallVectorImpl<ISD::OutputArg> &Outs,
 101                            const SmallVectorImpl<SDValue> &OutVals,
 102                            const SmallVectorImpl<ISD::InputArg> &Ins,
 103                            DebugLoc dl, SelectionDAG &DAG,
 104                            SmallVectorImpl<SDValue> &InVals) const;
 105
 106     SDValue LowerCCCArguments(SDValue Chain,
 107                               CallingConv::ID CallConv,
 108                               bool isVarArg,
 109                               const SmallVectorImpl<ISD::InputArg> &Ins,
 110                               DebugLoc dl,
 111                               SelectionDAG &DAG,
 112                               SmallVectorImpl<SDValue> &InVals) const;
 113
 114     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 115                             CallingConv::ID CallConv, bool isVarArg,
 116                             const SmallVectorImpl<ISD::InputArg> &Ins,
 117                             DebugLoc dl, SelectionDAG &DAG,
 118                             SmallVectorImpl<SDValue> &InVals) const;
 119
 120     virtual SDValue
 121       LowerFormalArguments(SDValue Chain,
 122                            CallingConv::ID CallConv, bool isVarArg,
 123                            const SmallVectorImpl<ISD::InputArg> &Ins,
 124                            DebugLoc dl, SelectionDAG &DAG,
 125                            SmallVectorImpl<SDValue> &InVals) const;
 126     virtual SDValue
 127       LowerCall(SDValue Chain, SDValue Callee,
 128                 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
 129                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 130                 const SmallVectorImpl<SDValue> &OutVals,
 131                 const SmallVectorImpl<ISD::InputArg> &Ins,
 132                 DebugLoc dl, SelectionDAG &DAG,
 133                 SmallVectorImpl<SDValue> &InVals) const;
 134
 135     virtual SDValue
 136       LowerReturn(SDValue Chain,
 137                   CallingConv::ID CallConv, bool isVarArg,
 138                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 139                   const SmallVectorImpl<SDValue> &OutVals,
 140                   DebugLoc dl, SelectionDAG &DAG) const;
 141
 142     const SystemZSubtarget &Subtarget;
 143     const SystemZTargetMachine &TM;
 144     const SystemZRegisterInfo *RegInfo;
 145   };
 146 } // namespace llvm
 147
 148 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H