lib/Target/ZPU/ZPU.td

   1 //===- ZPU.td - Describe the ZPU Target Machine ----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is the top level entry point for the ZPU target.
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // Register File, Calling Conv, Instruction Descriptions
  20 //===----------------------------------------------------------------------===//
  21
  22 include "ZPURegisterInfo.td"
  23 include "ZPUInstrInfo.td"
  24 include "ZPUCallingConv.td"
  25
  26 def ZPUInstrInfo : InstrInfo;
  27
  28
  29 def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
  30                                 "Enable 'byte/half swap' instructions.">;
  31
  32 class Proc<string Name, list<SubtargetFeature> Features>
  33  : Processor<Name, NoItineraries, Features>;
  34
  35 def FeatureZPU1       : SubtargetFeature<"zpu11", "ZPUArchVersion", "ZPU1",
  36                                 "ZPU ISA Support">;
  37
  38 def : Proc<"zpu1", [FeatureZPU1]>;
  39
  40
  41 def ZPU : Target {
  42   let InstructionSet = ZPUInstrInfo;
  43 }