lib/Target/ZPU/ZPUInstrInfo.cpp

   1 //===- ZPUInstrInfo.cpp - ZPU Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the ZPU implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ZPUInstrInfo.h"
  15 #include "ZPUTargetMachine.h"
  16 #include "llvm/ADT/STLExtras.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineRegisterInfo.h"
  19 #include "llvm/Support/ErrorHandling.h"
  20 #include "ZPUGenInstrInfo.inc"
  21
  22 using namespace llvm;
  23
  24 ZPUInstrInfo::ZPUInstrInfo(ZPUTargetMachine &tm)
  25   : TargetInstrInfoImpl(ZPUInsts, array_lengthof(ZPUInsts)),
  26     TM(tm), RI(*this)
  27 {}
  28
  29 /// isLoadFromStackSlot - If the specified machine instruction is a direct
  30 /// load from a stack slot, return the virtual or physical register number of
  31 /// the destination along with the FrameIndex of the loaded stack slot.  If
  32 /// not, return 0.  This predicate must return 0 if the instruction has
  33 /// any side effects other than loading from the stack slot.
  34 unsigned ZPUInstrInfo::
  35 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
  36 {
  37
  38
  39   return 0;
  40 }
  41
  42 /// isStoreToStackSlot - If the specified machine instruction is a direct
  43 /// store to a stack slot, return the virtual or physical register number of
  44 /// the source reg along with the FrameIndex of the loaded stack slot.  If
  45 /// not, return 0.  This predicate must return 0 if the instruction has
  46 /// any side effects other than storing to the stack slot.
  47 unsigned ZPUInstrInfo::
  48 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
  49 {
  50   return 0;
  51 }
  52
  53 /// insertNoop - If data hazard condition is found insert the target nop
  54 /// instruction.
  55 void ZPUInstrInfo::
  56 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
  57 {
  58 }
  59
  60 void ZPUInstrInfo::
  61 copyPhysReg(MachineBasicBlock &MBB,
  62             MachineBasicBlock::iterator I, DebugLoc DL,
  63             unsigned DestReg, unsigned SrcReg,
  64             bool KillSrc) const {
  65 }
  66
  67 void ZPUInstrInfo::
  68 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  69                     unsigned SrcReg, bool isKill, int FI,
  70                     const TargetRegisterClass *RC,
  71                     const TargetRegisterInfo *TRI) const {
  72 }
  73
  74 void ZPUInstrInfo::
  75 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  76                      unsigned DestReg, int FI,
  77                      const TargetRegisterClass *RC,
  78                      const TargetRegisterInfo *TRI) const
  79 {
  80 }
  81