zpu: managed to compile program that writes constant to global variable
[llvm/zpu.git] / lib / CodeGen / SimpleRegisterCoalescing.h
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1 //===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements a simple register copy coalescing phase.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
15 #define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/RegisterCoalescer.h"
20 #include "llvm/ADT/BitVector.h"
22 namespace llvm {
23 class SimpleRegisterCoalescing;
24 class LiveVariables;
25 class TargetRegisterInfo;
26 class TargetInstrInfo;
27 class VirtRegMap;
28 class MachineLoopInfo;
30 /// CopyRec - Representation for copy instructions in coalescer queue.
31 ///
32 struct CopyRec {
33 MachineInstr *MI;
34 unsigned LoopDepth;
35 CopyRec(MachineInstr *mi, unsigned depth)
36 : MI(mi), LoopDepth(depth) {}
39 class SimpleRegisterCoalescing : public MachineFunctionPass,
40 public RegisterCoalescer {
41 MachineFunction* mf_;
42 MachineRegisterInfo* mri_;
43 const TargetMachine* tm_;
44 const TargetRegisterInfo* tri_;
45 const TargetInstrInfo* tii_;
46 LiveIntervals *li_;
47 const MachineLoopInfo* loopInfo;
48 AliasAnalysis *AA;
50 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
52 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
53 ///
54 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
56 /// ReMatCopies - Keep track of copies eliminated due to remat.
57 ///
58 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
60 /// ReMatDefs - Keep track of definition instructions which have
61 /// been remat'ed.
62 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
64 public:
65 static char ID; // Pass identifcation, replacement for typeid
66 SimpleRegisterCoalescing() : MachineFunctionPass(ID) {
67 initializeSimpleRegisterCoalescingPass(*PassRegistry::getPassRegistry());
70 struct InstrSlots {
71 enum {
72 LOAD = 0,
73 USE = 1,
74 DEF = 2,
75 STORE = 3,
76 NUM = 4
80 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
81 virtual void releaseMemory();
83 /// runOnMachineFunction - pass entry point
84 virtual bool runOnMachineFunction(MachineFunction&);
86 bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
87 // This runs as an independent pass, so don't do anything.
88 return false;
91 /// print - Implement the dump method.
92 virtual void print(raw_ostream &O, const Module* = 0) const;
94 private:
95 /// joinIntervals - join compatible live intervals
96 void joinIntervals();
98 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
99 /// copies that cannot yet be coalesced into the "TryAgain" list.
100 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
101 std::vector<CopyRec> &TryAgain);
103 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
104 /// which are the src/dst of the copy instruction CopyMI. This returns true
105 /// if the copy was successfully coalesced away. If it is not currently
106 /// possible to coalesce this interval, but it may be possible if other
107 /// things get coalesced, then it returns true by reference in 'Again'.
108 bool JoinCopy(CopyRec &TheCopy, bool &Again);
110 /// JoinIntervals - Attempt to join these two intervals. On failure, this
111 /// returns false. The output "SrcInt" will not have been modified, so we can
112 /// use this information below to update aliases.
113 bool JoinIntervals(CoalescerPair &CP);
115 /// Return true if the two specified registers belong to different register
116 /// classes. The registers may be either phys or virt regs.
117 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
119 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
120 /// the source value number is defined by a copy from the destination reg
121 /// see if we can merge these two destination reg valno# into a single
122 /// value number, eliminating a copy.
123 bool AdjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
125 /// HasOtherReachingDefs - Return true if there are definitions of IntB
126 /// other than BValNo val# that can reach uses of AValno val# of IntA.
127 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
128 VNInfo *AValNo, VNInfo *BValNo);
130 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
131 /// If the source value number is defined by a commutable instruction and
132 /// its other operand is coalesced to the copy dest register, see if we
133 /// can transform the copy into a noop by commuting the definition.
134 bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
136 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic
137 /// block as the copy instruction, trim the ive interval to the last use
138 /// and return true.
139 bool TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
140 MachineBasicBlock *CopyMBB,
141 LiveInterval &li, const LiveRange *LR);
143 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
144 /// computation, replace the copy by rematerialize the definition.
145 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
146 unsigned DstSubIdx, MachineInstr *CopyMI);
148 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
149 /// two virtual registers from different register classes.
150 bool isWinToJoinCrossClass(unsigned SrcReg,
151 unsigned DstReg,
152 const TargetRegisterClass *SrcRC,
153 const TargetRegisterClass *DstRC,
154 const TargetRegisterClass *NewRC);
156 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
157 /// update the subregister number if it is not zero. If DstReg is a
158 /// physical register and the existing subregister number of the def / use
159 /// being updated is not zero, make sure to set it to the correct physical
160 /// subregister.
161 void UpdateRegDefsUses(const CoalescerPair &CP);
163 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
164 /// Return true if live interval is removed.
165 bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
167 /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
168 /// extended by a dead copy. Mark the last use (if any) of the val# as kill
169 /// as ends the live range there. If there isn't another use, then this
170 /// live range is dead. Return true if live interval is removed.
171 bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
173 /// RemoveDeadDef - If a def of a live interval is now determined dead,
174 /// remove the val# it defines. If the live interval becomes empty, remove
175 /// it as well.
176 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
178 /// RemoveCopyFlag - If DstReg is no longer defined by CopyMI, clear the
179 /// VNInfo copy flag for DstReg and all aliases.
180 void RemoveCopyFlag(unsigned DstReg, const MachineInstr *CopyMI);
182 /// lastRegisterUse - Returns the last use of the specific register between
183 /// cycles Start and End or NULL if there are no uses.
184 MachineOperand *lastRegisterUse(SlotIndex Start, SlotIndex End,
185 unsigned Reg, SlotIndex &LastUseIdx) const;
188 } // End llvm namespace
190 #endif