lib/Target/Blackfin/Blackfin.td

   1 //===- Blackfin.td - Describe the Blackfin Target Machine --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // Blackfin Subtarget features.
  21 //===----------------------------------------------------------------------===//
  22
  23 def FeatureSDRAM : SubtargetFeature<"sdram", "sdram", "true",
  24     "Build for SDRAM">;
  25
  26 def FeatureICPLB : SubtargetFeature<"icplb", "icplb", "true",
  27     "Assume instruction cache lookaside buffers are enabled at runtime">;
  28
  29 //===----------------------------------------------------------------------===//
  30 // Bugs in the silicon becomes workarounds in the compiler.
  31 // See http://www.analog.com/ for the full list of IC anomalies.
  32 //===----------------------------------------------------------------------===//
  33
  34 def WA_MI_SHIFT : SubtargetFeature<"mi-shift-anomaly","wa_mi_shift", "true",
  35     "Work around 05000074 - "
  36     "Multi-Issue Instruction with dsp32shiftimm and P-reg Store">;
  37
  38 def WA_CSYNC : SubtargetFeature<"csync-anomaly","wa_csync", "true",
  39     "Work around 05000244 - "
  40     "If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control">;
  41
  42 def WA_SPECLD : SubtargetFeature<"specld-anomaly","wa_specld", "true",
  43     "Work around 05000245 - "
  44     "Access in the Shadow of a Conditional Branch">;
  45
  46 def WA_HWLOOP : SubtargetFeature<"hwloop-anomaly","wa_hwloop", "true",
  47     "Work around 05000257 - "
  48     "Interrupt/Exception During Short Hardware Loop">;
  49
  50 def WA_MMR_STALL : SubtargetFeature<"mmr-stall-anomaly","wa_mmr_stall", "true",
  51     "Work around 05000283 - "
  52     "System MMR Write Is Stalled Indefinitely when Killed">;
  53
  54 def WA_LCREGS : SubtargetFeature<"lcregs-anomaly","wa_lcregs", "true",
  55     "Work around 05000312 - "
  56     "SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted">;
  57
  58 def WA_KILLED_MMR : SubtargetFeature<"killed-mmr-anomaly",
  59                                      "wa_killed_mmr", "true",
  60     "Work around 05000315 - "
  61     "Killed System MMR Write Completes Erroneously on Next System MMR Access">;
  62
  63 def WA_RETS : SubtargetFeature<"rets-anomaly", "wa_rets", "true",
  64     "Work around 05000371 - "
  65     "Possible RETS Register Corruption when Subroutine Is under 5 Cycles">;
  66
  67 def WA_IND_CALL : SubtargetFeature<"ind-call-anomaly", "wa_ind_call", "true",
  68     "Work around 05000426 - "
  69     "Speculative Fetches of Indirect-Pointer Instructions">;
  70
  71 //===----------------------------------------------------------------------===//
  72 // Register File, Calling Conv, Instruction Descriptions
  73 //===----------------------------------------------------------------------===//
  74
  75 include "BlackfinRegisterInfo.td"
  76 include "BlackfinCallingConv.td"
  77 include "BlackfinIntrinsics.td"
  78 include "BlackfinInstrInfo.td"
  79
  80 def BlackfinInstrInfo : InstrInfo {}
  81
  82 //===----------------------------------------------------------------------===//
  83 // Blackfin processors supported.
  84 //===----------------------------------------------------------------------===//
  85
  86 class Proc<string Name, string Suffix, list<SubtargetFeature> Features>
  87  : Processor<!strconcat(Name, Suffix), NoItineraries, Features>;
  88
  89 def : Proc<"generic", "", []>;
  90
  91 multiclass Core<string Name,string Suffix,
  92                 list<SubtargetFeature> Features> {
  93   def : Proc<Name, Suffix, Features>;
  94   def : Proc<Name, "", Features>;
  95   def : Proc<Name, "-none", []>;
  96 }
  97
  98 multiclass CoreEdinburgh<string Name>
  99       : Core<Name, "-0.6", [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS]> {
 100   def : Proc<Name, "-0.5",
 101         [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
 102          WA_RETS]>;
 103   def : Proc<Name, "-0.4",
 104         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 105          WA_KILLED_MMR, WA_RETS]>;
 106   def : Proc<Name, "-0.3",
 107         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 108          WA_KILLED_MMR, WA_RETS]>;
 109   def : Proc<Name, "-any",
 110         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 111          WA_KILLED_MMR, WA_RETS]>;
 112 }
 113 multiclass CoreBraemar<string Name>
 114        : Core<Name, "-0.3",
 115          [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]> {
 116   def  : Proc<Name, "-0.2",
 117          [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 118           WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
 119   def  : Proc<Name, "-any",
 120          [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 121           WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
 122 }
 123 multiclass CoreStirling<string Name>
 124       : Core<Name, "-0.5", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
 125   def : Proc<Name, "-0.4",
 126         [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
 127   def : Proc<Name, "-0.3",
 128         [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
 129          WA_RETS, WA_IND_CALL]>;
 130   def : Proc<Name, "-any",
 131         [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
 132          WA_RETS, WA_IND_CALL]>;
 133 }
 134 multiclass CoreMoab<string Name>
 135       : Core<Name, "-0.3", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
 136   def : Proc<Name, "-0.2", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
 137   def : Proc<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
 138   def : Proc<Name, "-0.0",
 139         [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
 140   def : Proc<Name, "-any",
 141         [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
 142 }
 143 multiclass CoreTeton<string Name>
 144       : Core<Name, "-0.5",
 145         [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
 146          WA_RETS, WA_IND_CALL]> {
 147   def : Proc<Name, "-0.3",
 148         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 149          WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
 150   def : Proc<Name, "-any",
 151         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 152          WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
 153 }
 154 multiclass CoreKookaburra<string Name>
 155       : Core<Name, "-0.2", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
 156   def : Proc<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
 157   def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
 158   def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
 159 }
 160 multiclass CoreMockingbird<string Name>
 161       : Core<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
 162   def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
 163   def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
 164 }
 165 multiclass CoreBrodie<string Name>
 166       : Core<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
 167   def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
 168   def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
 169 }
 170
 171 defm BF512 : CoreBrodie<"bf512">;
 172 defm BF514 : CoreBrodie<"bf514">;
 173 defm BF516 : CoreBrodie<"bf516">;
 174 defm BF518 : CoreBrodie<"bf518">;
 175 defm BF522 : CoreMockingbird<"bf522">;
 176 defm BF523 : CoreKookaburra<"bf523">;
 177 defm BF524 : CoreMockingbird<"bf524">;
 178 defm BF525 : CoreKookaburra<"bf525">;
 179 defm BF526 : CoreMockingbird<"bf526">;
 180 defm BF527 : CoreKookaburra<"bf527">;
 181 defm BF531 : CoreEdinburgh<"bf531">;
 182 defm BF532 : CoreEdinburgh<"bf532">;
 183 defm BF533 : CoreEdinburgh<"bf533">;
 184 defm BF534 : CoreBraemar<"bf534">;
 185 defm BF536 : CoreBraemar<"bf536">;
 186 defm BF537 : CoreBraemar<"bf537">;
 187 defm BF538 : CoreStirling<"bf538">;
 188 defm BF539 : CoreStirling<"bf539">;
 189 defm BF542 : CoreMoab<"bf542">;
 190 defm BF544 : CoreMoab<"bf544">;
 191 defm BF548 : CoreMoab<"bf548">;
 192 defm BF549 : CoreMoab<"bf549">;
 193 defm BF561 : CoreTeton<"bf561">;
 194
 195 //===----------------------------------------------------------------------===//
 196 // Declare the target which we are implementing
 197 //===----------------------------------------------------------------------===//
 198
 199 def Blackfin : Target {
 200   // Pull in Instruction Info:
 201   let InstructionSet = BlackfinInstrInfo;
 202 }