1 //===- MBlaze.td - Describe the MBlaze Target Machine ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is the top level entry point for the MBlaze target.
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // Target-independent interfaces
14 //===----------------------------------------------------------------------===//
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // Register File, Calling Conv, Instruction Descriptions
20 //===----------------------------------------------------------------------===//
22 include "MBlazeRegisterInfo.td"
23 include "MBlazeSchedule.td"
24 include "MBlazeIntrinsics.td"
25 include "MBlazeInstrInfo.td"
26 include "MBlazeCallingConv.td"
28 def MBlazeInstrInfo : InstrInfo;
30 //===----------------------------------------------------------------------===//
31 // Microblaze Subtarget features //
32 //===----------------------------------------------------------------------===//
34 def FeaturePipe3 : SubtargetFeature<"pipe3", "HasPipe3", "true",
35 "Implements 3-stage pipeline">;
36 def FeatureBarrel : SubtargetFeature<"barrel", "HasBarrel", "true",
37 "Implements barrel shifter">;
38 def FeatureDiv : SubtargetFeature<"div", "HasDiv", "true",
39 "Implements hardware divider">;
40 def FeatureMul : SubtargetFeature<"mul", "HasMul", "true",
41 "Implements hardware multiplier">;
42 def FeatureFSL : SubtargetFeature<"fsl", "HasFSL", "true",
43 "Implements FSL instructions">;
44 def FeatureEFSL : SubtargetFeature<"efsl", "HasEFSL", "true",
45 "Implements extended FSL instructions">;
46 def FeatureMSRSet : SubtargetFeature<"msrset", "HasMSRSet", "true",
47 "Implements MSR register set and clear">;
48 def FeatureException : SubtargetFeature<"exception", "HasException", "true",
49 "Implements hardware exception support">;
50 def FeaturePatCmp : SubtargetFeature<"patcmp", "HasPatCmp", "true",
51 "Implements pattern compare instruction">;
52 def FeatureFPU : SubtargetFeature<"fpu", "HasFPU", "true",
53 "Implements floating point unit">;
54 def FeatureESR : SubtargetFeature<"esr", "HasESR", "true",
55 "Implements ESR and EAR registers">;
56 def FeaturePVR : SubtargetFeature<"pvr", "HasPVR", "true",
57 "Implements processor version register">;
58 def FeatureMul64 : SubtargetFeature<"mul64", "HasMul64", "true",
59 "Implements multiplier with 64-bit result">;
60 def FeatureSqrt : SubtargetFeature<"sqrt", "HasSqrt", "true",
61 "Implements sqrt and floating point convert">;
62 def FeatureMMU : SubtargetFeature<"mmu", "HasMMU", "true",
63 "Implements memory management unit">;
65 //===----------------------------------------------------------------------===//
66 // MBlaze processors supported.
67 //===----------------------------------------------------------------------===//
69 class Proc<string Name, list<SubtargetFeature> Features>
70 : Processor<Name, MBlazeGenericItineraries, Features>;
72 def : Proc<"v400", []>;
73 def : Proc<"v500", []>;
74 def : Proc<"v600", []>;
75 def : Proc<"v700", []>;
76 def : Proc<"v710", []>;
78 //===----------------------------------------------------------------------===//
79 // Instruction Descriptions
80 //===----------------------------------------------------------------------===//
82 def MBlazeAsmWriter : AsmWriter {
83 string AsmWriterClassName = "InstPrinter";
84 bit isMCAsmWriter = 1;
87 //===----------------------------------------------------------------------===//
89 //===----------------------------------------------------------------------===//
92 let InstructionSet = MBlazeInstrInfo;
93 let AssemblyWriters = [MBlazeAsmWriter];