lib/Target/MBlaze/MBlazeInstrInfo.h

   1 //===- MBlazeInstrInfo.h - MBlaze Instruction Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the MBlaze implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef MBLAZEINSTRUCTIONINFO_H
  15 #define MBLAZEINSTRUCTIONINFO_H
  16
  17 #include "MBlaze.h"
  18 #include "llvm/Support/ErrorHandling.h"
  19 #include "llvm/Target/TargetInstrInfo.h"
  20 #include "MBlazeRegisterInfo.h"
  21
  22 namespace llvm {
  23
  24 namespace MBlaze {
  25
  26   // MBlaze Branch Codes
  27   enum FPBranchCode {
  28     BRANCH_F,
  29     BRANCH_T,
  30     BRANCH_FL,
  31     BRANCH_TL,
  32     BRANCH_INVALID
  33   };
  34
  35   // MBlaze Condition Codes
  36   enum CondCode {
  37     // To be used with float branch True
  38     FCOND_F,
  39     FCOND_UN,
  40     FCOND_EQ,
  41     FCOND_UEQ,
  42     FCOND_OLT,
  43     FCOND_ULT,
  44     FCOND_OLE,
  45     FCOND_ULE,
  46     FCOND_SF,
  47     FCOND_NGLE,
  48     FCOND_SEQ,
  49     FCOND_NGL,
  50     FCOND_LT,
  51     FCOND_NGE,
  52     FCOND_LE,
  53     FCOND_NGT,
  54
  55     // To be used with float branch False
  56     // This conditions have the same mnemonic as the
  57     // above ones, but are used with a branch False;
  58     FCOND_T,
  59     FCOND_OR,
  60     FCOND_NEQ,
  61     FCOND_OGL,
  62     FCOND_UGE,
  63     FCOND_OGE,
  64     FCOND_UGT,
  65     FCOND_OGT,
  66     FCOND_ST,
  67     FCOND_GLE,
  68     FCOND_SNE,
  69     FCOND_GL,
  70     FCOND_NLT,
  71     FCOND_GE,
  72     FCOND_NLE,
  73     FCOND_GT,
  74
  75     // Only integer conditions
  76     COND_E,
  77     COND_GZ,
  78     COND_GEZ,
  79     COND_LZ,
  80     COND_LEZ,
  81     COND_NE,
  82     COND_INVALID
  83   };
  84
  85   // Turn condition code into conditional branch opcode.
  86   unsigned GetCondBranchFromCond(CondCode CC);
  87
  88   /// GetOppositeBranchCondition - Return the inverse of the specified cond,
  89   /// e.g. turning COND_E to COND_NE.
  90   CondCode GetOppositeBranchCondition(MBlaze::CondCode CC);
  91
  92   /// MBlazeCCToString - Map each FP condition code to its string
  93   inline static const char *MBlazeFCCToString(MBlaze::CondCode CC)
  94   {
  95     switch (CC) {
  96       default: llvm_unreachable("Unknown condition code");
  97       case FCOND_F:
  98       case FCOND_T:   return "f";
  99       case FCOND_UN:
 100       case FCOND_OR:  return "un";
 101       case FCOND_EQ:
 102       case FCOND_NEQ: return "eq";
 103       case FCOND_UEQ:
 104       case FCOND_OGL: return "ueq";
 105       case FCOND_OLT:
 106       case FCOND_UGE: return "olt";
 107       case FCOND_ULT:
 108       case FCOND_OGE: return "ult";
 109       case FCOND_OLE:
 110       case FCOND_UGT: return "ole";
 111       case FCOND_ULE:
 112       case FCOND_OGT: return "ule";
 113       case FCOND_SF:
 114       case FCOND_ST:  return "sf";
 115       case FCOND_NGLE:
 116       case FCOND_GLE: return "ngle";
 117       case FCOND_SEQ:
 118       case FCOND_SNE: return "seq";
 119       case FCOND_NGL:
 120       case FCOND_GL:  return "ngl";
 121       case FCOND_LT:
 122       case FCOND_NLT: return "lt";
 123       case FCOND_NGE:
 124       case FCOND_GE:  return "ge";
 125       case FCOND_LE:
 126       case FCOND_NLE: return "nle";
 127       case FCOND_NGT:
 128       case FCOND_GT:  return "gt";
 129     }
 130   }
 131 }
 132
 133 /// MBlazeII - This namespace holds all of the target specific flags that
 134 /// instruction info tracks.
 135 ///
 136 namespace MBlazeII {
 137   enum {
 138     // PseudoFrm - This represents an instruction that is a pseudo instruction
 139     // or one that has not been implemented yet.  It is illegal to code generate
 140     // it, but tolerated for intermediate implementation stages.
 141     FPseudo = 0,
 142     FRRR,
 143     FRRI,
 144     FCRR,
 145     FCRI,
 146     FRCR,
 147     FRCI,
 148     FCCR,
 149     FCCI,
 150     FRRCI,
 151     FRRC,
 152     FRCX,
 153     FRCS,
 154     FCRCS,
 155     FCRCX,
 156     FCX,
 157     FCR,
 158     FRIR,
 159     FC,
 160     FormMask = 63
 161
 162     //===------------------------------------------------------------------===//
 163     // MBlaze Specific MachineOperand flags.
 164     // MO_NO_FLAG,
 165
 166     /// MO_GOT - Represents the offset into the global offset table at which
 167     /// the address the relocation entry symbol resides during execution.
 168     // MO_GOT,
 169
 170     /// MO_GOT_CALL - Represents the offset into the global offset table at
 171     /// which the address of a call site relocation entry symbol resides
 172     /// during execution. This is different from the above since this flag
 173     /// can only be present in call instructions.
 174     // MO_GOT_CALL,
 175
 176     /// MO_GPREL - Represents the offset from the current gp value to be used
 177     /// for the relocatable object file being produced.
 178     // MO_GPREL,
 179
 180     /// MO_ABS_HILO - Represents the hi or low part of an absolute symbol
 181     /// address.
 182     // MO_ABS_HILO
 183
 184   };
 185 }
 186
 187 class MBlazeInstrInfo : public TargetInstrInfoImpl {
 188   MBlazeTargetMachine &TM;
 189   const MBlazeRegisterInfo RI;
 190 public:
 191   explicit MBlazeInstrInfo(MBlazeTargetMachine &TM);
 192
 193   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
 194   /// such, whenever a client has an instance of instruction info, it should
 195   /// always be able to get register info as well (through this method).
 196   ///
 197   virtual const MBlazeRegisterInfo &getRegisterInfo() const { return RI; }
 198
 199   /// isLoadFromStackSlot - If the specified machine instruction is a direct
 200   /// load from a stack slot, return the virtual or physical register number of
 201   /// the destination along with the FrameIndex of the loaded stack slot.  If
 202   /// not, return 0.  This predicate must return 0 if the instruction has
 203   /// any side effects other than loading from the stack slot.
 204   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
 205                                        int &FrameIndex) const;
 206
 207   /// isStoreToStackSlot - If the specified machine instruction is a direct
 208   /// store to a stack slot, return the virtual or physical register number of
 209   /// the source reg along with the FrameIndex of the loaded stack slot.  If
 210   /// not, return 0.  This predicate must return 0 if the instruction has
 211   /// any side effects other than storing to the stack slot.
 212   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
 213                                       int &FrameIndex) const;
 214
 215   /// Branch Analysis
 216   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 217                                 MachineBasicBlock *FBB,
 218                                 const SmallVectorImpl<MachineOperand> &Cond,
 219                                 DebugLoc DL) const;
 220   virtual void copyPhysReg(MachineBasicBlock &MBB,
 221                            MachineBasicBlock::iterator I, DebugLoc DL,
 222                            unsigned DestReg, unsigned SrcReg,
 223                            bool KillSrc) const;
 224   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
 225                                    MachineBasicBlock::iterator MBBI,
 226                                    unsigned SrcReg, bool isKill, int FrameIndex,
 227                                    const TargetRegisterClass *RC,
 228                                    const TargetRegisterInfo *TRI) const;
 229
 230   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
 231                                     MachineBasicBlock::iterator MBBI,
 232                                     unsigned DestReg, int FrameIndex,
 233                                     const TargetRegisterClass *RC,
 234                                     const TargetRegisterInfo *TRI) const;
 235
 236   /// Insert nop instruction when hazard condition is found
 237   virtual void insertNoop(MachineBasicBlock &MBB,
 238                           MachineBasicBlock::iterator MI) const;
 239
 240   /// getGlobalBaseReg - Return a virtual register initialized with the
 241   /// the global base register value. Output instructions required to
 242   /// initialize the register in the function entry block, if necessary.
 243   ///
 244   unsigned getGlobalBaseReg(MachineFunction *MF) const;
 245 };
 246
 247 }
 248
 249 #endif