lib/Target/Mips/MipsInstrInfo.cpp

   1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Mips implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "MipsInstrInfo.h"
  15 #include "MipsTargetMachine.h"
  16 #include "MipsMachineFunction.h"
  17 #include "llvm/ADT/STLExtras.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/MachineRegisterInfo.h"
  20 #include "llvm/Support/ErrorHandling.h"
  21 #include "MipsGenInstrInfo.inc"
  22
  23 using namespace llvm;
  24
  25 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
  26   : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
  27     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
  28
  29 static bool isZeroImm(const MachineOperand &op) {
  30   return op.isImm() && op.getImm() == 0;
  31 }
  32
  33 /// isLoadFromStackSlot - If the specified machine instruction is a direct
  34 /// load from a stack slot, return the virtual or physical register number of
  35 /// the destination along with the FrameIndex of the loaded stack slot.  If
  36 /// not, return 0.  This predicate must return 0 if the instruction has
  37 /// any side effects other than loading from the stack slot.
  38 unsigned MipsInstrInfo::
  39 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
  40 {
  41   if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
  42       (MI->getOpcode() == Mips::LDC1)) {
  43     if ((MI->getOperand(2).isFI()) && // is a stack slot
  44         (MI->getOperand(1).isImm()) &&  // the imm is zero
  45         (isZeroImm(MI->getOperand(1)))) {
  46       FrameIndex = MI->getOperand(2).getIndex();
  47       return MI->getOperand(0).getReg();
  48     }
  49   }
  50
  51   return 0;
  52 }
  53
  54 /// isStoreToStackSlot - If the specified machine instruction is a direct
  55 /// store to a stack slot, return the virtual or physical register number of
  56 /// the source reg along with the FrameIndex of the loaded stack slot.  If
  57 /// not, return 0.  This predicate must return 0 if the instruction has
  58 /// any side effects other than storing to the stack slot.
  59 unsigned MipsInstrInfo::
  60 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
  61 {
  62   if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
  63       (MI->getOpcode() == Mips::SDC1)) {
  64     if ((MI->getOperand(2).isFI()) && // is a stack slot
  65         (MI->getOperand(1).isImm()) &&  // the imm is zero
  66         (isZeroImm(MI->getOperand(1)))) {
  67       FrameIndex = MI->getOperand(2).getIndex();
  68       return MI->getOperand(0).getReg();
  69     }
  70   }
  71   return 0;
  72 }
  73
  74 /// insertNoop - If data hazard condition is found insert the target nop
  75 /// instruction.
  76 void MipsInstrInfo::
  77 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
  78 {
  79   DebugLoc DL;
  80   BuildMI(MBB, MI, DL, get(Mips::NOP));
  81 }
  82
  83 void MipsInstrInfo::
  84 copyPhysReg(MachineBasicBlock &MBB,
  85             MachineBasicBlock::iterator I, DebugLoc DL,
  86             unsigned DestReg, unsigned SrcReg,
  87             bool KillSrc) const {
  88   bool DestCPU = Mips::CPURegsRegClass.contains(DestReg);
  89   bool SrcCPU  = Mips::CPURegsRegClass.contains(SrcReg);
  90
  91   // CPU-CPU is the most common.
  92   if (DestCPU && SrcCPU) {
  93     BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
  94       .addReg(SrcReg, getKillRegState(KillSrc));
  95     return;
  96   }
  97
  98   // Copy to CPU from other registers.
  99   if (DestCPU) {
 100     if (Mips::CCRRegClass.contains(SrcReg))
 101       BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg)
 102         .addReg(SrcReg, getKillRegState(KillSrc));
 103     else if (Mips::FGR32RegClass.contains(SrcReg))
 104       BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg)
 105         .addReg(SrcReg, getKillRegState(KillSrc));
 106     else if (SrcReg == Mips::HI)
 107       BuildMI(MBB, I, DL, get(Mips::MFHI), DestReg);
 108     else if (SrcReg == Mips::LO)
 109       BuildMI(MBB, I, DL, get(Mips::MFLO), DestReg);
 110     else
 111       llvm_unreachable("Copy to CPU from invalid register");
 112     return;
 113   }
 114
 115   // Copy to other registers from CPU.
 116   if (SrcCPU) {
 117     if (Mips::CCRRegClass.contains(DestReg))
 118       BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg)
 119         .addReg(SrcReg, getKillRegState(KillSrc));
 120     else if (Mips::FGR32RegClass.contains(DestReg))
 121       BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg)
 122         .addReg(SrcReg, getKillRegState(KillSrc));
 123     else if (DestReg == Mips::HI)
 124       BuildMI(MBB, I, DL, get(Mips::MTHI))
 125         .addReg(SrcReg, getKillRegState(KillSrc));
 126     else if (DestReg == Mips::LO)
 127       BuildMI(MBB, I, DL, get(Mips::MTLO))
 128         .addReg(SrcReg, getKillRegState(KillSrc));
 129     else
 130       llvm_unreachable("Copy from CPU to invalid register");
 131     return;
 132   }
 133
 134   if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) {
 135     BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg)
 136       .addReg(SrcReg, getKillRegState(KillSrc));
 137     return;
 138   }
 139
 140   if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) {
 141     BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg)
 142       .addReg(SrcReg, getKillRegState(KillSrc));
 143     return;
 144   }
 145
 146   if (Mips::CCRRegClass.contains(DestReg, SrcReg)) {
 147     BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg)
 148       .addReg(SrcReg, getKillRegState(KillSrc));
 149     return;
 150   }
 151   llvm_unreachable("Cannot copy registers");
 152 }
 153
 154 void MipsInstrInfo::
 155 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 156                     unsigned SrcReg, bool isKill, int FI,
 157                     const TargetRegisterClass *RC,
 158                     const TargetRegisterInfo *TRI) const {
 159   DebugLoc DL;
 160   if (I != MBB.end()) DL = I->getDebugLoc();
 161
 162   if (RC == Mips::CPURegsRegisterClass)
 163     BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
 164           .addImm(0).addFrameIndex(FI);
 165   else if (RC == Mips::FGR32RegisterClass)
 166     BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
 167           .addImm(0).addFrameIndex(FI);
 168   else if (RC == Mips::AFGR64RegisterClass) {
 169     if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
 170       BuildMI(MBB, I, DL, get(Mips::SDC1))
 171         .addReg(SrcReg, getKillRegState(isKill))
 172         .addImm(0).addFrameIndex(FI);
 173     } else {
 174       const TargetRegisterInfo *TRI =
 175         MBB.getParent()->getTarget().getRegisterInfo();
 176       const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
 177       BuildMI(MBB, I, DL, get(Mips::SWC1))
 178         .addReg(SubSet[0], getKillRegState(isKill))
 179         .addImm(0).addFrameIndex(FI);
 180       BuildMI(MBB, I, DL, get(Mips::SWC1))
 181         .addReg(SubSet[1], getKillRegState(isKill))
 182         .addImm(4).addFrameIndex(FI);
 183     }
 184   } else
 185     llvm_unreachable("Register class not handled!");
 186 }
 187
 188 void MipsInstrInfo::
 189 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 190                      unsigned DestReg, int FI,
 191                      const TargetRegisterClass *RC,
 192                      const TargetRegisterInfo *TRI) const
 193 {
 194   DebugLoc DL;
 195   if (I != MBB.end()) DL = I->getDebugLoc();
 196
 197   if (RC == Mips::CPURegsRegisterClass)
 198     BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
 199   else if (RC == Mips::FGR32RegisterClass)
 200     BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
 201   else if (RC == Mips::AFGR64RegisterClass) {
 202     if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
 203       BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
 204     } else {
 205       const TargetRegisterInfo *TRI =
 206         MBB.getParent()->getTarget().getRegisterInfo();
 207       const unsigned *SubSet = TRI->getSubRegisters(DestReg);
 208       BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
 209         .addImm(0).addFrameIndex(FI);
 210       BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
 211         .addImm(4).addFrameIndex(FI);
 212     }
 213   } else
 214     llvm_unreachable("Register class not handled!");
 215 }
 216
 217 //===----------------------------------------------------------------------===//
 218 // Branch Analysis
 219 //===----------------------------------------------------------------------===//
 220
 221 /// GetCondFromBranchOpc - Return the Mips CC that matches
 222 /// the correspondent Branch instruction opcode.
 223 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
 224 {
 225   switch (BrOpc) {
 226   default: return Mips::COND_INVALID;
 227   case Mips::BEQ  : return Mips::COND_E;
 228   case Mips::BNE  : return Mips::COND_NE;
 229   case Mips::BGTZ : return Mips::COND_GZ;
 230   case Mips::BGEZ : return Mips::COND_GEZ;
 231   case Mips::BLTZ : return Mips::COND_LZ;
 232   case Mips::BLEZ : return Mips::COND_LEZ;
 233
 234   // We dont do fp branch analysis yet!
 235   case Mips::BC1T :
 236   case Mips::BC1F : return Mips::COND_INVALID;
 237   }
 238 }
 239
 240 /// GetCondBranchFromCond - Return the Branch instruction
 241 /// opcode that matches the cc.
 242 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
 243 {
 244   switch (CC) {
 245   default: llvm_unreachable("Illegal condition code!");
 246   case Mips::COND_E   : return Mips::BEQ;
 247   case Mips::COND_NE  : return Mips::BNE;
 248   case Mips::COND_GZ  : return Mips::BGTZ;
 249   case Mips::COND_GEZ : return Mips::BGEZ;
 250   case Mips::COND_LZ  : return Mips::BLTZ;
 251   case Mips::COND_LEZ : return Mips::BLEZ;
 252
 253   case Mips::FCOND_F:
 254   case Mips::FCOND_UN:
 255   case Mips::FCOND_EQ:
 256   case Mips::FCOND_UEQ:
 257   case Mips::FCOND_OLT:
 258   case Mips::FCOND_ULT:
 259   case Mips::FCOND_OLE:
 260   case Mips::FCOND_ULE:
 261   case Mips::FCOND_SF:
 262   case Mips::FCOND_NGLE:
 263   case Mips::FCOND_SEQ:
 264   case Mips::FCOND_NGL:
 265   case Mips::FCOND_LT:
 266   case Mips::FCOND_NGE:
 267   case Mips::FCOND_LE:
 268   case Mips::FCOND_NGT: return Mips::BC1T;
 269
 270   case Mips::FCOND_T:
 271   case Mips::FCOND_OR:
 272   case Mips::FCOND_NEQ:
 273   case Mips::FCOND_OGL:
 274   case Mips::FCOND_UGE:
 275   case Mips::FCOND_OGE:
 276   case Mips::FCOND_UGT:
 277   case Mips::FCOND_OGT:
 278   case Mips::FCOND_ST:
 279   case Mips::FCOND_GLE:
 280   case Mips::FCOND_SNE:
 281   case Mips::FCOND_GL:
 282   case Mips::FCOND_NLT:
 283   case Mips::FCOND_GE:
 284   case Mips::FCOND_NLE:
 285   case Mips::FCOND_GT: return Mips::BC1F;
 286   }
 287 }
 288
 289 /// GetOppositeBranchCondition - Return the inverse of the specified
 290 /// condition, e.g. turning COND_E to COND_NE.
 291 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
 292 {
 293   switch (CC) {
 294   default: llvm_unreachable("Illegal condition code!");
 295   case Mips::COND_E   : return Mips::COND_NE;
 296   case Mips::COND_NE  : return Mips::COND_E;
 297   case Mips::COND_GZ  : return Mips::COND_LEZ;
 298   case Mips::COND_GEZ : return Mips::COND_LZ;
 299   case Mips::COND_LZ  : return Mips::COND_GEZ;
 300   case Mips::COND_LEZ : return Mips::COND_GZ;
 301   case Mips::FCOND_F  : return Mips::FCOND_T;
 302   case Mips::FCOND_UN : return Mips::FCOND_OR;
 303   case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
 304   case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
 305   case Mips::FCOND_OLT: return Mips::FCOND_UGE;
 306   case Mips::FCOND_ULT: return Mips::FCOND_OGE;
 307   case Mips::FCOND_OLE: return Mips::FCOND_UGT;
 308   case Mips::FCOND_ULE: return Mips::FCOND_OGT;
 309   case Mips::FCOND_SF:  return Mips::FCOND_ST;
 310   case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
 311   case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
 312   case Mips::FCOND_NGL: return Mips::FCOND_GL;
 313   case Mips::FCOND_LT:  return Mips::FCOND_NLT;
 314   case Mips::FCOND_NGE: return Mips::FCOND_GE;
 315   case Mips::FCOND_LE:  return Mips::FCOND_NLE;
 316   case Mips::FCOND_NGT: return Mips::FCOND_GT;
 317   }
 318 }
 319
 320 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
 321                                   MachineBasicBlock *&TBB,
 322                                   MachineBasicBlock *&FBB,
 323                                   SmallVectorImpl<MachineOperand> &Cond,
 324                                   bool AllowModify) const
 325 {
 326   // If the block has no terminators, it just falls into the block after it.
 327   MachineBasicBlock::iterator I = MBB.end();
 328   if (I == MBB.begin())
 329     return false;
 330   --I;
 331   while (I->isDebugValue()) {
 332     if (I == MBB.begin())
 333       return false;
 334     --I;
 335   }
 336   if (!isUnpredicatedTerminator(I))
 337     return false;
 338
 339   // Get the last instruction in the block.
 340   MachineInstr *LastInst = I;
 341
 342   // If there is only one terminator instruction, process it.
 343   unsigned LastOpc = LastInst->getOpcode();
 344   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 345     if (!LastInst->getDesc().isBranch())
 346       return true;
 347
 348     // Unconditional branch
 349     if (LastOpc == Mips::J) {
 350       TBB = LastInst->getOperand(0).getMBB();
 351       return false;
 352     }
 353
 354     Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
 355     if (BranchCode == Mips::COND_INVALID)
 356       return true;  // Can't handle indirect branch.
 357
 358     // Conditional branch
 359     // Block ends with fall-through condbranch.
 360     if (LastOpc != Mips::COND_INVALID) {
 361       int LastNumOp = LastInst->getNumOperands();
 362
 363       TBB = LastInst->getOperand(LastNumOp-1).getMBB();
 364       Cond.push_back(MachineOperand::CreateImm(BranchCode));
 365
 366       for (int i=0; i<LastNumOp-1; i++) {
 367         Cond.push_back(LastInst->getOperand(i));
 368       }
 369
 370       return false;
 371     }
 372   }
 373
 374   // Get the instruction before it if it is a terminator.
 375   MachineInstr *SecondLastInst = I;
 376
 377   // If there are three terminators, we don't know what sort of block this is.
 378   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
 379     return true;
 380
 381   // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
 382   unsigned SecondLastOpc    = SecondLastInst->getOpcode();
 383   Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
 384
 385   if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
 386     int SecondNumOp = SecondLastInst->getNumOperands();
 387
 388     TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
 389     Cond.push_back(MachineOperand::CreateImm(BranchCode));
 390
 391     for (int i=0; i<SecondNumOp-1; i++) {
 392       Cond.push_back(SecondLastInst->getOperand(i));
 393     }
 394
 395     FBB = LastInst->getOperand(0).getMBB();
 396     return false;
 397   }
 398
 399   // If the block ends with two unconditional branches, handle it. The last
 400   // one is not executed, so remove it.
 401   if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
 402     TBB = SecondLastInst->getOperand(0).getMBB();
 403     I = LastInst;
 404     if (AllowModify)
 405       I->eraseFromParent();
 406     return false;
 407   }
 408
 409   // Otherwise, can't handle this.
 410   return true;
 411 }
 412
 413 unsigned MipsInstrInfo::
 414 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 415              MachineBasicBlock *FBB,
 416              const SmallVectorImpl<MachineOperand> &Cond,
 417              DebugLoc DL) const {
 418   // Shouldn't be a fall through.
 419   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 420   assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
 421          "Mips branch conditions can have two|three components!");
 422
 423   if (FBB == 0) { // One way branch.
 424     if (Cond.empty()) {
 425       // Unconditional branch?
 426       BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
 427     } else {
 428       // Conditional branch.
 429       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
 430       const TargetInstrDesc &TID = get(Opc);
 431
 432       if (TID.getNumOperands() == 3)
 433         BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
 434                           .addReg(Cond[2].getReg())
 435                           .addMBB(TBB);
 436       else
 437         BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
 438                           .addMBB(TBB);
 439
 440     }
 441     return 1;
 442   }
 443
 444   // Two-way Conditional branch.
 445   unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
 446   const TargetInstrDesc &TID = get(Opc);
 447
 448   if (TID.getNumOperands() == 3)
 449     BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
 450                       .addMBB(TBB);
 451   else
 452     BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addMBB(TBB);
 453
 454   BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
 455   return 2;
 456 }
 457
 458 unsigned MipsInstrInfo::
 459 RemoveBranch(MachineBasicBlock &MBB) const
 460 {
 461   MachineBasicBlock::iterator I = MBB.end();
 462   if (I == MBB.begin()) return 0;
 463   --I;
 464   while (I->isDebugValue()) {
 465     if (I == MBB.begin())
 466       return 0;
 467     --I;
 468   }
 469   if (I->getOpcode() != Mips::J &&
 470       GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
 471     return 0;
 472
 473   // Remove the branch.
 474   I->eraseFromParent();
 475
 476   I = MBB.end();
 477
 478   if (I == MBB.begin()) return 1;
 479   --I;
 480   if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
 481     return 1;
 482
 483   // Remove the branch.
 484   I->eraseFromParent();
 485   return 2;
 486 }
 487
 488 /// ReverseBranchCondition - Return the inverse opcode of the
 489 /// specified Branch instruction.
 490 bool MipsInstrInfo::
 491 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
 492 {
 493   assert( (Cond.size() == 3 || Cond.size() == 2) &&
 494           "Invalid Mips branch condition!");
 495   Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
 496   return false;
 497 }
 498
 499 /// getGlobalBaseReg - Return a virtual register initialized with the
 500 /// the global base register value. Output instructions required to
 501 /// initialize the register in the function entry block, if necessary.
 502 ///
 503 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
 504   MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
 505   unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
 506   if (GlobalBaseReg != 0)
 507     return GlobalBaseReg;
 508
 509   // Insert the set of GlobalBaseReg into the first MBB of the function
 510   MachineBasicBlock &FirstMBB = MF->front();
 511   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
 512   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 513   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 514
 515   GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
 516   BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
 517           GlobalBaseReg).addReg(Mips::GP);
 518   RegInfo.addLiveIn(Mips::GP);
 519
 520   MipsFI->setGlobalBaseReg(GlobalBaseReg);
 521   return GlobalBaseReg;
 522 }