lib/Target/Sparc/SparcISelLowering.h

   1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef SPARC_ISELLOWERING_H
  16 #define SPARC_ISELLOWERING_H
  17
  18 #include "llvm/Target/TargetLowering.h"
  19 #include "Sparc.h"
  20
  21 namespace llvm {
  22   namespace SPISD {
  23     enum {
  24       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  25       CMPICC,      // Compare two GPR operands, set icc.
  26       CMPFCC,      // Compare two FP operands, set fcc.
  27       BRICC,       // Branch to dest on icc condition
  28       BRFCC,       // Branch to dest on fcc condition
  29       SELECT_ICC,  // Select between two values using the current ICC flags.
  30       SELECT_FCC,  // Select between two values using the current FCC flags.
  31
  32       Hi, Lo,      // Hi/Lo operations, typically on a global address.
  33
  34       FTOI,        // FP to Int within a FP register.
  35       ITOF,        // Int to FP within a FP register.
  36
  37       CALL,        // A call instruction.
  38       RET_FLAG,    // Return with a flag operand.
  39       GLOBAL_BASE_REG // Global base reg for PIC
  40     };
  41   }
  42
  43   class SparcTargetLowering : public TargetLowering {
  44   public:
  45     SparcTargetLowering(TargetMachine &TM);
  46     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  47
  48     /// computeMaskedBitsForTargetNode - Determine which of the bits specified
  49     /// in Mask are known to be either zero or one and return them in the
  50     /// KnownZero/KnownOne bitsets.
  51     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
  52                                                 const APInt &Mask,
  53                                                 APInt &KnownZero,
  54                                                 APInt &KnownOne,
  55                                                 const SelectionDAG &DAG,
  56                                                 unsigned Depth = 0) const;
  57
  58     virtual MachineBasicBlock *
  59       EmitInstrWithCustomInserter(MachineInstr *MI,
  60                                   MachineBasicBlock *MBB) const;
  61
  62     virtual const char *getTargetNodeName(unsigned Opcode) const;
  63
  64     ConstraintType getConstraintType(const std::string &Constraint) const;
  65     std::pair<unsigned, const TargetRegisterClass*>
  66     getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
  67     std::vector<unsigned>
  68     getRegClassForInlineAsmConstraint(const std::string &Constraint,
  69                                       EVT VT) const;
  70
  71     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
  72
  73     /// getFunctionAlignment - Return the Log2 alignment of this function.
  74     virtual unsigned getFunctionAlignment(const Function *F) const;
  75
  76     virtual SDValue
  77       LowerFormalArguments(SDValue Chain,
  78                            CallingConv::ID CallConv,
  79                            bool isVarArg,
  80                            const SmallVectorImpl<ISD::InputArg> &Ins,
  81                            DebugLoc dl, SelectionDAG &DAG,
  82                            SmallVectorImpl<SDValue> &InVals) const;
  83
  84     virtual SDValue
  85       LowerCall(SDValue Chain, SDValue Callee,
  86                 CallingConv::ID CallConv, bool isVarArg,
  87                 bool &isTailCall,
  88                 const SmallVectorImpl<ISD::OutputArg> &Outs,
  89                 const SmallVectorImpl<SDValue> &OutVals,
  90                 const SmallVectorImpl<ISD::InputArg> &Ins,
  91                 DebugLoc dl, SelectionDAG &DAG,
  92                 SmallVectorImpl<SDValue> &InVals) const;
  93
  94     virtual SDValue
  95       LowerReturn(SDValue Chain,
  96                   CallingConv::ID CallConv, bool isVarArg,
  97                   const SmallVectorImpl<ISD::OutputArg> &Outs,
  98                   const SmallVectorImpl<SDValue> &OutVals,
  99                   DebugLoc dl, SelectionDAG &DAG) const;
 100
 101     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 102     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 103   };
 104 } // end namespace llvm
 105
 106 #endif    // SPARC_ISELLOWERING_H