lib/Target/TargetInstrInfo.cpp

   1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetInstrInfo.h"
  15 #include "llvm/Target/TargetInstrItineraries.h"
  16 #include "llvm/Target/TargetRegisterInfo.h"
  17 #include "llvm/CodeGen/SelectionDAGNodes.h"
  18 #include "llvm/MC/MCAsmInfo.h"
  19 #include "llvm/Support/ErrorHandling.h"
  20 using namespace llvm;
  21
  22 //===----------------------------------------------------------------------===//
  23 //  TargetOperandInfo
  24 //===----------------------------------------------------------------------===//
  25
  26 /// getRegClass - Get the register class for the operand, handling resolution
  27 /// of "symbolic" pointer register classes etc.  If this is not a register
  28 /// operand, this returns null.
  29 const TargetRegisterClass *
  30 TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
  31   if (isLookupPtrRegClass())
  32     return TRI->getPointerRegClass(RegClass);
  33   // Instructions like INSERT_SUBREG do not have fixed register classes.
  34   if (RegClass < 0)
  35     return 0;
  36   // Otherwise just look it up normally.
  37   return TRI->getRegClass(RegClass);
  38 }
  39
  40 //===----------------------------------------------------------------------===//
  41 //  TargetInstrInfo
  42 //===----------------------------------------------------------------------===//
  43
  44 TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
  45                                  unsigned numOpcodes)
  46   : Descriptors(Desc), NumOpcodes(numOpcodes) {
  47 }
  48
  49 TargetInstrInfo::~TargetInstrInfo() {
  50 }
  51
  52 unsigned
  53 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
  54                                 const MachineInstr *MI) const {
  55   if (!ItinData || ItinData->isEmpty())
  56     return 1;
  57
  58   unsigned Class = MI->getDesc().getSchedClass();
  59   unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
  60   if (UOps)
  61     return UOps;
  62
  63   // The # of u-ops is dynamically determined. The specific target should
  64   // override this function to return the right number.
  65   return 1;
  66 }
  67
  68 int
  69 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
  70                              const MachineInstr *DefMI, unsigned DefIdx,
  71                              const MachineInstr *UseMI, unsigned UseIdx) const {
  72   if (!ItinData || ItinData->isEmpty())
  73     return -1;
  74
  75   unsigned DefClass = DefMI->getDesc().getSchedClass();
  76   unsigned UseClass = UseMI->getDesc().getSchedClass();
  77   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
  78 }
  79
  80 int
  81 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
  82                                    SDNode *DefNode, unsigned DefIdx,
  83                                    SDNode *UseNode, unsigned UseIdx) const {
  84   if (!ItinData || ItinData->isEmpty())
  85     return -1;
  86
  87   if (!DefNode->isMachineOpcode())
  88     return -1;
  89
  90   unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
  91   if (!UseNode->isMachineOpcode())
  92     return ItinData->getOperandCycle(DefClass, DefIdx);
  93   unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
  94   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
  95 }
  96
  97 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
  98                                      const MachineInstr *MI,
  99                                      unsigned *PredCost) const {
 100   if (!ItinData || ItinData->isEmpty())
 101     return 1;
 102
 103   return ItinData->getStageLatency(MI->getDesc().getSchedClass());
 104 }
 105
 106 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
 107                                      SDNode *N) const {
 108   if (!ItinData || ItinData->isEmpty())
 109     return 1;
 110
 111   if (!N->isMachineOpcode())
 112     return 1;
 113
 114   return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
 115 }
 116
 117 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
 118                                        const MachineInstr *DefMI,
 119                                        unsigned DefIdx) const {
 120   if (!ItinData || ItinData->isEmpty())
 121     return false;
 122
 123   unsigned DefClass = DefMI->getDesc().getSchedClass();
 124   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
 125   return (DefCycle != -1 && DefCycle <= 1);
 126 }
 127
 128 /// insertNoop - Insert a noop into the instruction stream at the specified
 129 /// point.
 130 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
 131                                  MachineBasicBlock::iterator MI) const {
 132   llvm_unreachable("Target didn't implement insertNoop!");
 133 }
 134
 135
 136 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
 137   const TargetInstrDesc &TID = MI->getDesc();
 138   if (!TID.isTerminator()) return false;
 139
 140   // Conditional branch is a special case.
 141   if (TID.isBranch() && !TID.isBarrier())
 142     return true;
 143   if (!TID.isPredicable())
 144     return true;
 145   return !isPredicated(MI);
 146 }
 147
 148
 149 /// Measure the specified inline asm to determine an approximation of its
 150 /// length.
 151 /// Comments (which run till the next SeparatorChar or newline) do not
 152 /// count as an instruction.
 153 /// Any other non-whitespace text is considered an instruction, with
 154 /// multiple instructions separated by SeparatorChar or newlines.
 155 /// Variable-length instructions are not handled here; this function
 156 /// may be overloaded in the target code to do that.
 157 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
 158                                              const MCAsmInfo &MAI) const {
 159
 160
 161   // Count the number of instructions in the asm.
 162   bool atInsnStart = true;
 163   unsigned Length = 0;
 164   for (; *Str; ++Str) {
 165     if (*Str == '\n' || *Str == MAI.getSeparatorChar())
 166       atInsnStart = true;
 167     if (atInsnStart && !isspace(*Str)) {
 168       Length += MAI.getMaxInstLength();
 169       atInsnStart = false;
 170     }
 171     if (atInsnStart && strncmp(Str, MAI.getCommentString(),
 172                                strlen(MAI.getCommentString())) == 0)
 173       atInsnStart = false;
 174   }
 175
 176   return Length;
 177 }