lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp

   1 //===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file includes code for rendering MCInst instances as AT&T-style
  11 // assembly.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "asm-printer"
  16 #include "X86IntelInstPrinter.h"
  17 #include "X86InstComments.h"
  18 #include "llvm/MC/MCInst.h"
  19 #include "llvm/MC/MCAsmInfo.h"
  20 #include "llvm/MC/MCExpr.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "llvm/Support/FormattedStream.h"
  23 #include "X86GenInstrNames.inc"
  24 using namespace llvm;
  25
  26 // Include the auto-generated portion of the assembly writer.
  27 #define GET_INSTRUCTION_NAME
  28 #include "X86GenAsmWriter1.inc"
  29
  30 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
  31   printInstruction(MI, OS);
  32
  33   // If verbose assembly is enabled, we can print some informative comments.
  34   if (CommentStream)
  35     EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
  36 }
  37 StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
  38   return getInstructionName(Opcode);
  39 }
  40
  41 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
  42                                      raw_ostream &O) {
  43   switch (MI->getOperand(Op).getImm()) {
  44   default: assert(0 && "Invalid ssecc argument!");
  45   case 0: O << "eq"; break;
  46   case 1: O << "lt"; break;
  47   case 2: O << "le"; break;
  48   case 3: O << "unord"; break;
  49   case 4: O << "neq"; break;
  50   case 5: O << "nlt"; break;
  51   case 6: O << "nle"; break;
  52   case 7: O << "ord"; break;
  53   }
  54 }
  55
  56 /// print_pcrel_imm - This is used to print an immediate value that ends up
  57 /// being encoded as a pc-relative value.
  58 void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
  59                                           raw_ostream &O) {
  60   const MCOperand &Op = MI->getOperand(OpNo);
  61   if (Op.isImm())
  62     O << Op.getImm();
  63   else {
  64     assert(Op.isExpr() && "unknown pcrel immediate operand");
  65     O << *Op.getExpr();
  66   }
  67 }
  68
  69 static void PrintRegName(raw_ostream &O, StringRef RegName) {
  70   for (unsigned i = 0, e = RegName.size(); i != e; ++i)
  71     O << (char)toupper(RegName[i]);
  72 }
  73
  74 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
  75                                        raw_ostream &O) {
  76   const MCOperand &Op = MI->getOperand(OpNo);
  77   if (Op.isReg()) {
  78     PrintRegName(O, getRegisterName(Op.getReg()));
  79   } else if (Op.isImm()) {
  80     O << Op.getImm();
  81   } else {
  82     assert(Op.isExpr() && "unknown operand kind in printOperand");
  83     O << *Op.getExpr();
  84   }
  85 }
  86
  87 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
  88                                             raw_ostream &O) {
  89   const MCOperand &BaseReg  = MI->getOperand(Op);
  90   unsigned ScaleVal         = MI->getOperand(Op+1).getImm();
  91   const MCOperand &IndexReg = MI->getOperand(Op+2);
  92   const MCOperand &DispSpec = MI->getOperand(Op+3);
  93   const MCOperand &SegReg   = MI->getOperand(Op+4);
  94
  95   // If this has a segment register, print it.
  96   if (SegReg.getReg()) {
  97     printOperand(MI, Op+4, O);
  98     O << ':';
  99   }
 100
 101   O << '[';
 102
 103   bool NeedPlus = false;
 104   if (BaseReg.getReg()) {
 105     printOperand(MI, Op, O);
 106     NeedPlus = true;
 107   }
 108
 109   if (IndexReg.getReg()) {
 110     if (NeedPlus) O << " + ";
 111     if (ScaleVal != 1)
 112       O << ScaleVal << '*';
 113     printOperand(MI, Op+2, O);
 114     NeedPlus = true;
 115   }
 116
 117
 118   if (!DispSpec.isImm()) {
 119     if (NeedPlus) O << " + ";
 120     assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
 121     O << *DispSpec.getExpr();
 122   } else {
 123     int64_t DispVal = DispSpec.getImm();
 124     if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
 125       if (NeedPlus) {
 126         if (DispVal > 0)
 127           O << " + ";
 128         else {
 129           O << " - ";
 130           DispVal = -DispVal;
 131         }
 132       }
 133       O << DispVal;
 134     }
 135   }
 136
 137   O << ']';
 138 }