lib/Target/ZPU/ZPUISelLowering.h

   1 //===-- ZPUISelLowering.h - ZPU DAG Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that ZPU uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef ZPUISELLOWERING_H
  16 #define ZPUISELLOWERING_H
  17
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/Target/TargetLowering.h"
  20 #include "ZPU.h"
  21
  22 namespace llvm {
  23   namespace ZPUISD {
  24     enum NodeType {
  25       // Start the numbering from where ISD NodeType finishes.
  26       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  27
  28       // Jump and link (call)
  29       JmpLink,
  30
  31       // Get the Higher 16 bits from a 32-bit immediate
  32       // No relation with ZPU Hi register
  33       Hi,
  34
  35       // Get the Lower 16 bits from a 32-bit immediate
  36       // No relation with ZPU Lo register
  37       Lo,
  38
  39       // Handle gp_rel (small data/bss sections) relocation.
  40       GPRel,
  41
  42       // Conditional Move
  43       CMov,
  44
  45       // Select CC Pseudo Instruction
  46       SelectCC,
  47
  48       // Floating Point Select CC Pseudo Instruction
  49       FPSelectCC,
  50
  51       // Floating Point Branch Conditional
  52       FPBrcond,
  53
  54       // Floating Point Compare
  55       FPCmp,
  56
  57       // Floating Point Rounding
  58       FPRound,
  59
  60       Wrapper,                   // Address wrapper
  61
  62       // Return
  63       Ret
  64     };
  65   }
  66
  67   //===--------------------------------------------------------------------===//
  68   // TargetLowering Implementation
  69   //===--------------------------------------------------------------------===//
  70
  71   class ZPUTargetLowering : public TargetLowering  {
  72   public:
  73     explicit ZPUTargetLowering(ZPUTargetMachine &TM);
  74
  75     /// LowerOperation - Provide custom lowering hooks for some operations.
  76     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  77
  78     /// getTargetNodeName - This method returns the name of a target specific
  79     //  DAG node.
  80     virtual const char *getTargetNodeName(unsigned Opcode) const;
  81
  82     /// getSetCCResultType - get the ISD::SETCC result ValueType
  83     MVT::SimpleValueType getSetCCResultType(EVT VT) const;
  84
  85     /// getFunctionAlignment - Return the Log2 alignment of this function.
  86     virtual unsigned getFunctionAlignment(const Function *F) const;
  87   private:
  88
  89
  90     // Lower Operand helpers
  91     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
  92                             CallingConv::ID CallConv, bool isVarArg,
  93                             const SmallVectorImpl<ISD::InputArg> &Ins,
  94                             DebugLoc dl, SelectionDAG &DAG,
  95                             SmallVectorImpl<SDValue> &InVals) const;
  96
  97 #if 0
  98     // Lower Operand specifics
  99     SDValue LowerANDOR(SDValue Op, SelectionDAG &DAG) const;
 100     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 101     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 102     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 103     SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
 104     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 105     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 106     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 107     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 108     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
 109     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 110 #endif
 111     virtual SDValue
 112       LowerFormalArguments(SDValue Chain,
 113                            CallingConv::ID CallConv, bool isVarArg,
 114                            const SmallVectorImpl<ISD::InputArg> &Ins,
 115                            DebugLoc dl, SelectionDAG &DAG,
 116                            SmallVectorImpl<SDValue> &InVals) const;
 117
 118     virtual SDValue
 119       LowerCall(SDValue Chain, SDValue Callee,
 120                 CallingConv::ID CallConv, bool isVarArg,
 121                 bool &isTailCall,
 122                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 123                 const SmallVectorImpl<SDValue> &OutVals,
 124                 const SmallVectorImpl<ISD::InputArg> &Ins,
 125                 DebugLoc dl, SelectionDAG &DAG,
 126                 SmallVectorImpl<SDValue> &InVals) const;
 127
 128     virtual SDValue
 129       LowerReturn(SDValue Chain,
 130                   CallingConv::ID CallConv, bool isVarArg,
 131                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 132                   const SmallVectorImpl<SDValue> &OutVals,
 133                   DebugLoc dl, SelectionDAG &DAG) const;
 134
 135     virtual MachineBasicBlock *
 136       EmitInstrWithCustomInserter(MachineInstr *MI,
 137                                   MachineBasicBlock *MBB) const;
 138
 139     // Inline asm support
 140     ConstraintType getConstraintType(const std::string &Constraint) const;
 141
 142     /// Examine constraint string and operand type and determine a weight value.
 143     /// The operand object must already have been set up with the operand type.
 144     ConstraintWeight getSingleConstraintMatchWeight(
 145       AsmOperandInfo &info, const char *constraint) const;
 146
 147     std::pair<unsigned, const TargetRegisterClass*>
 148               getRegForInlineAsmConstraint(const std::string &Constraint,
 149               EVT VT) const;
 150
 151     std::vector<unsigned>
 152     getRegClassForInlineAsmConstraint(const std::string &Constraint,
 153               EVT VT) const;
 154
 155     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
 156
 157     /// isFPImmLegal - Returns true if the target can instruction select the
 158     /// specified FP immediate natively. If false, the legalizer will
 159     /// materialize the FP immediate as a load from a constant pool.
 160     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
 161     SDValue LowerGlobalAddress(SDValue Op,
 162                                                        SelectionDAG &DAG)  const;
 163   };
 164 }
 165
 166 #endif // ZPUISELLOWERING_H