lib/CodeGen/DeadMachineInstructionElim.cpp

   1 //===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is an extremely simple MachineInstr-level dead-code-elimination pass.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "codegen-dce"
  15 #include "llvm/CodeGen/Passes.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/CodeGen/MachineFunctionPass.h"
  18 #include "llvm/CodeGen/MachineRegisterInfo.h"
  19 #include "llvm/Support/Debug.h"
  20 #include "llvm/Support/raw_ostream.h"
  21 #include "llvm/Target/TargetInstrInfo.h"
  22 #include "llvm/Target/TargetMachine.h"
  23 #include "llvm/ADT/Statistic.h"
  24 using namespace llvm;
  25
  26 STATISTIC(NumDeletes,          "Number of dead instructions deleted");
  27
  28 namespace {
  29   class DeadMachineInstructionElim : public MachineFunctionPass {
  30     virtual bool runOnMachineFunction(MachineFunction &MF);
  31
  32     const TargetRegisterInfo *TRI;
  33     const MachineRegisterInfo *MRI;
  34     const TargetInstrInfo *TII;
  35     BitVector LivePhysRegs;
  36
  37   public:
  38     static char ID; // Pass identification, replacement for typeid
  39     DeadMachineInstructionElim() : MachineFunctionPass(ID) {
  40      initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry());
  41     }
  42
  43   private:
  44     bool isDead(const MachineInstr *MI) const;
  45   };
  46 }
  47 char DeadMachineInstructionElim::ID = 0;
  48
  49 INITIALIZE_PASS(DeadMachineInstructionElim, "dead-mi-elimination",
  50                 "Remove dead machine instructions", false, false)
  51
  52 FunctionPass *llvm::createDeadMachineInstructionElimPass() {
  53   return new DeadMachineInstructionElim();
  54 }
  55
  56 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
  57   // Don't delete instructions with side effects.
  58   bool SawStore = false;
  59   if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
  60     return false;
  61
  62   // Examine each operand.
  63   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
  64     const MachineOperand &MO = MI->getOperand(i);
  65     if (MO.isReg() && MO.isDef()) {
  66       unsigned Reg = MO.getReg();
  67       if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
  68           LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) {
  69         // This def has a non-debug use. Don't delete the instruction!
  70         return false;
  71       }
  72     }
  73   }
  74
  75   // If there are no defs with uses, the instruction is dead.
  76   return true;
  77 }
  78
  79 bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
  80   bool AnyChanges = false;
  81   MRI = &MF.getRegInfo();
  82   TRI = MF.getTarget().getRegisterInfo();
  83   TII = MF.getTarget().getInstrInfo();
  84
  85   // Treat reserved registers as always live.
  86   BitVector ReservedRegs = TRI->getReservedRegs(MF);
  87
  88   // Loop over all instructions in all blocks, from bottom to top, so that it's
  89   // more likely that chains of dependent but ultimately dead instructions will
  90   // be cleaned up.
  91   for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
  92        I != E; ++I) {
  93     MachineBasicBlock *MBB = &*I;
  94
  95     // Start out assuming that reserved registers are live out of this block.
  96     LivePhysRegs = ReservedRegs;
  97
  98     // Also add any explicit live-out physregs for this block.
  99     if (!MBB->empty() && MBB->back().getDesc().isReturn())
 100       for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
 101            LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
 102         unsigned Reg = *LOI;
 103         if (TargetRegisterInfo::isPhysicalRegister(Reg))
 104           LivePhysRegs.set(Reg);
 105       }
 106
 107     // FIXME: Add live-ins from sucessors to LivePhysRegs. Normally, physregs
 108     // are not live across blocks, but some targets (x86) can have flags live
 109     // out of a block.
 110
 111     // Now scan the instructions and delete dead ones, tracking physreg
 112     // liveness as we go.
 113     for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
 114          MIE = MBB->rend(); MII != MIE; ) {
 115       MachineInstr *MI = &*MII;
 116
 117       // If the instruction is dead, delete it!
 118       if (isDead(MI)) {
 119         DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
 120         // It is possible that some DBG_VALUE instructions refer to this
 121         // instruction.  Examine each def operand for such references;
 122         // if found, mark the DBG_VALUE as undef (but don't delete it).
 123         for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 124           const MachineOperand &MO = MI->getOperand(i);
 125           if (!MO.isReg() || !MO.isDef())
 126             continue;
 127           unsigned Reg = MO.getReg();
 128           if (!TargetRegisterInfo::isVirtualRegister(Reg))
 129             continue;
 130           MachineRegisterInfo::use_iterator nextI;
 131           for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
 132                E = MRI->use_end(); I!=E; I=nextI) {
 133             nextI = llvm::next(I);  // I is invalidated by the setReg
 134             MachineOperand& Use = I.getOperand();
 135             MachineInstr *UseMI = Use.getParent();
 136             if (UseMI==MI)
 137               continue;
 138             assert(Use.isDebug());
 139             UseMI->getOperand(0).setReg(0U);
 140           }
 141         }
 142         AnyChanges = true;
 143         MI->eraseFromParent();
 144         ++NumDeletes;
 145         MIE = MBB->rend();
 146         // MII is now pointing to the next instruction to process,
 147         // so don't increment it.
 148         continue;
 149       }
 150
 151       // Record the physreg defs.
 152       for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 153         const MachineOperand &MO = MI->getOperand(i);
 154         if (MO.isReg() && MO.isDef()) {
 155           unsigned Reg = MO.getReg();
 156           if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
 157             LivePhysRegs.reset(Reg);
 158             // Check the subreg set, not the alias set, because a def
 159             // of a super-register may still be partially live after
 160             // this def.
 161             for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
 162                  *SubRegs; ++SubRegs)
 163               LivePhysRegs.reset(*SubRegs);
 164           }
 165         }
 166       }
 167       // Record the physreg uses, after the defs, in case a physreg is
 168       // both defined and used in the same instruction.
 169       for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 170         const MachineOperand &MO = MI->getOperand(i);
 171         if (MO.isReg() && MO.isUse()) {
 172           unsigned Reg = MO.getReg();
 173           if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
 174             LivePhysRegs.set(Reg);
 175             for (const unsigned *AliasSet = TRI->getAliasSet(Reg);
 176                  *AliasSet; ++AliasSet)
 177               LivePhysRegs.set(*AliasSet);
 178           }
 179         }
 180       }
 181
 182       // We didn't delete the current instruction, so increment MII to
 183       // the next one.
 184       ++MII;
 185     }
 186   }
 187
 188   LivePhysRegs.clear();
 189   return AnyChanges;
 190 }