lib/CodeGen/MachineRegisterInfo.cpp

   1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Implementation of the MachineRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/CodeGen/MachineRegisterInfo.h"
  15 #include "llvm/CodeGen/MachineInstrBuilder.h"
  16 #include "llvm/Target/TargetInstrInfo.h"
  17 #include "llvm/Support/CommandLine.h"
  18 using namespace llvm;
  19
  20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
  21   VRegInfo.reserve(256);
  22   RegAllocHints.reserve(256);
  23   RegClass2VRegMap = new std::vector<unsigned>[TRI.getNumRegClasses()];
  24   UsedPhysRegs.resize(TRI.getNumRegs());
  25
  26   // Create the physreg use/def lists.
  27   PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
  28   memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
  29 }
  30
  31 MachineRegisterInfo::~MachineRegisterInfo() {
  32 #ifndef NDEBUG
  33   for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
  34     assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
  35   for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
  36     assert(!PhysRegUseDefLists[i] &&
  37            "PhysRegUseDefLists has entries after all instructions are deleted");
  38 #endif
  39   delete [] PhysRegUseDefLists;
  40   delete [] RegClass2VRegMap;
  41 }
  42
  43 /// setRegClass - Set the register class of the specified virtual register.
  44 ///
  45 void
  46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
  47   unsigned VR = Reg;
  48   Reg -= TargetRegisterInfo::FirstVirtualRegister;
  49   assert(Reg < VRegInfo.size() && "Invalid vreg!");
  50   const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
  51   VRegInfo[Reg].first = RC;
  52
  53   // Remove from old register class's vregs list. This may be slow but
  54   // fortunately this operation is rarely needed.
  55   std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
  56   std::vector<unsigned>::iterator I = std::find(VRegs.begin(), VRegs.end(), VR);
  57   VRegs.erase(I);
  58
  59   // Add to new register class's vregs list.
  60   RegClass2VRegMap[RC->getID()].push_back(VR);
  61 }
  62
  63 const TargetRegisterClass *
  64 MachineRegisterInfo::constrainRegClass(unsigned Reg,
  65                                        const TargetRegisterClass *RC) {
  66   const TargetRegisterClass *OldRC = getRegClass(Reg);
  67   if (OldRC == RC)
  68     return RC;
  69   const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC);
  70   if (!NewRC)
  71     return 0;
  72   if (NewRC != OldRC)
  73     setRegClass(Reg, NewRC);
  74   return NewRC;
  75 }
  76
  77 /// createVirtualRegister - Create and return a new virtual register in the
  78 /// function with the specified register class.
  79 ///
  80 unsigned
  81 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
  82   assert(RegClass && "Cannot create register without RegClass!");
  83   // Add a reg, but keep track of whether the vector reallocated or not.
  84   void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
  85   VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
  86   RegAllocHints.push_back(std::make_pair(0, 0));
  87
  88   if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
  89     // The vector reallocated, handle this now.
  90     HandleVRegListReallocation();
  91   unsigned VR = getLastVirtReg();
  92   RegClass2VRegMap[RegClass->getID()].push_back(VR);
  93   return VR;
  94 }
  95
  96 /// HandleVRegListReallocation - We just added a virtual register to the
  97 /// VRegInfo info list and it reallocated.  Update the use/def lists info
  98 /// pointers.
  99 void MachineRegisterInfo::HandleVRegListReallocation() {
 100   // The back pointers for the vreg lists point into the previous vector.
 101   // Update them to point to their correct slots.
 102   for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
 103     MachineOperand *List = VRegInfo[i].second;
 104     if (!List) continue;
 105     // Update the back-pointer to be accurate once more.
 106     List->Contents.Reg.Prev = &VRegInfo[i].second;
 107   }
 108 }
 109
 110 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
 111 /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
 112 /// except that it also changes any definitions of the register as well.
 113 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
 114   assert(FromReg != ToReg && "Cannot replace a reg with itself");
 115
 116   // TODO: This could be more efficient by bulk changing the operands.
 117   for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
 118     MachineOperand &O = I.getOperand();
 119     ++I;
 120     O.setReg(ToReg);
 121   }
 122 }
 123
 124
 125 /// getVRegDef - Return the machine instr that defines the specified virtual
 126 /// register or null if none is found.  This assumes that the code is in SSA
 127 /// form, so there should only be one definition.
 128 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
 129   assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
 130          "Invalid vreg!");
 131   // Since we are in SSA form, we can use the first definition.
 132   if (!def_empty(Reg))
 133     return &*def_begin(Reg);
 134   return 0;
 135 }
 136
 137 bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
 138   use_iterator UI = use_begin(RegNo);
 139   if (UI == use_end())
 140     return false;
 141   return ++UI == use_end();
 142 }
 143
 144 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
 145   use_nodbg_iterator UI = use_nodbg_begin(RegNo);
 146   if (UI == use_nodbg_end())
 147     return false;
 148   return ++UI == use_nodbg_end();
 149 }
 150
 151 /// clearKillFlags - Iterate over all the uses of the given register and
 152 /// clear the kill flag from the MachineOperand. This function is used by
 153 /// optimization passes which extend register lifetimes and need only
 154 /// preserve conservative kill flag information.
 155 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
 156   for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
 157     UI.getOperand().setIsKill(false);
 158 }
 159
 160 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
 161   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
 162     if (I->first == Reg || I->second == Reg)
 163       return true;
 164   return false;
 165 }
 166
 167 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
 168   for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
 169     if (*I == Reg)
 170       return true;
 171   return false;
 172 }
 173
 174 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
 175 /// corresponding live-in physical register.
 176 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
 177   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
 178     if (I->second == VReg)
 179       return I->first;
 180   return 0;
 181 }
 182
 183 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
 184 /// corresponding live-in physical register.
 185 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
 186   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
 187     if (I->first == PReg)
 188       return I->second;
 189   return 0;
 190 }
 191
 192 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
 193 /// into the given entry block.
 194 void
 195 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
 196                                       const TargetRegisterInfo &TRI,
 197                                       const TargetInstrInfo &TII) {
 198   // Emit the copies into the top of the block.
 199   for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
 200     if (LiveIns[i].second) {
 201       if (use_empty(LiveIns[i].second)) {
 202         // The livein has no uses. Drop it.
 203         //
 204         // It would be preferable to have isel avoid creating live-in
 205         // records for unused arguments in the first place, but it's
 206         // complicated by the debug info code for arguments.
 207         LiveIns.erase(LiveIns.begin() + i);
 208         --i; --e;
 209       } else {
 210         // Emit a copy.
 211         BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
 212                 TII.get(TargetOpcode::COPY), LiveIns[i].second)
 213           .addReg(LiveIns[i].first);
 214
 215         // Add the register to the entry block live-in set.
 216         EntryMBB->addLiveIn(LiveIns[i].first);
 217       }
 218     } else {
 219       // Add the register to the entry block live-in set.
 220       EntryMBB->addLiveIn(LiveIns[i].first);
 221     }
 222 }
 223
 224 void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
 225   for (int i = UsedPhysRegs.find_first(); i >= 0;
 226        i = UsedPhysRegs.find_next(i))
 227          for (const unsigned *SS = TRI.getSubRegisters(i);
 228               unsigned SubReg = *SS; ++SS)
 229            if (SubReg > unsigned(i))
 230              UsedPhysRegs.set(SubReg);
 231 }
 232
 233 #ifndef NDEBUG
 234 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
 235   for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
 236     I.getOperand().getParent()->dump();
 237 }
 238 #endif