lib/CodeGen/RegAllocBase.h

   1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the RegAllocBase class, which is the skeleton of a basic
  11 // register allocation algorithm and interface for extending it. It provides the
  12 // building blocks on which to construct other experimental allocators and test
  13 // the validity of two principles:
  14 //
  15 // - If virtual and physical register liveness is modeled using intervals, then
  16 // on-the-fly interference checking is cheap. Furthermore, interferences can be
  17 // lazily cached and reused.
  18 //
  19 // - Register allocation complexity, and generated code performance is
  20 // determined by the effectiveness of live range splitting rather than optimal
  21 // coloring.
  22 //
  23 // Following the first principle, interfering checking revolves around the
  24 // LiveIntervalUnion data structure.
  25 //
  26 // To fulfill the second principle, the basic allocator provides a driver for
  27 // incremental splitting. It essentially punts on the problem of register
  28 // coloring, instead driving the assignment of virtual to physical registers by
  29 // the cost of splitting. The basic allocator allows for heuristic reassignment
  30 // of registers, if a more sophisticated allocator chooses to do that.
  31 //
  32 // This framework provides a way to engineer the compile time vs. code
  33 // quality trade-off without relying a particular theoretical solver.
  34 //
  35 //===----------------------------------------------------------------------===//
  36
  37 #ifndef LLVM_CODEGEN_REGALLOCBASE
  38 #define LLVM_CODEGEN_REGALLOCBASE
  39
  40 #include "llvm/ADT/OwningPtr.h"
  41
  42 namespace llvm {
  43
  44 template<typename T> class SmallVectorImpl;
  45 class TargetRegisterInfo;
  46 class VirtRegMap;
  47 class LiveIntervals;
  48
  49 // Heuristic that determines the priority of assigning virtual to physical
  50 // registers. The main impact of the heuristic is expected to be compile time.
  51 // The default is to simply compare spill weights.
  52 struct LessSpillWeightPriority
  53   : public std::binary_function<LiveInterval,LiveInterval, bool> {
  54   bool operator()(const LiveInterval *left, const LiveInterval *right) const {
  55     return left->weight < right->weight;
  56   }
  57 };
  58
  59 // Forward declare a priority queue of live virtual registers. If an
  60 // implementation needs to prioritize by anything other than spill weight, then
  61 // this will become an abstract base class with virtual calls to push/get.
  62 class LiveVirtRegQueue;
  63
  64 /// RegAllocBase provides the register allocation driver and interface that can
  65 /// be extended to add interesting heuristics.
  66 ///
  67 /// More sophisticated allocators must override the selectOrSplit() method to
  68 /// implement live range splitting and must specify a comparator to determine
  69 /// register assignment priority. LessSpillWeightPriority is provided as a
  70 /// standard comparator.
  71 class RegAllocBase {
  72 protected:
  73   // Array of LiveIntervalUnions indexed by physical register.
  74   class LIUArray {
  75     unsigned nRegs_;
  76     OwningArrayPtr<LiveIntervalUnion> array_;
  77   public:
  78     LIUArray(): nRegs_(0) {}
  79
  80     unsigned numRegs() const { return nRegs_; }
  81
  82     void init(unsigned nRegs);
  83
  84     void clear();
  85
  86     LiveIntervalUnion& operator[](unsigned physReg) {
  87       assert(physReg <  nRegs_ && "physReg out of bounds");
  88       return array_[physReg];
  89     }
  90   };
  91
  92   const TargetRegisterInfo *tri_;
  93   VirtRegMap *vrm_;
  94   LiveIntervals *lis_;
  95   LIUArray physReg2liu_;
  96
  97   RegAllocBase(): tri_(0), vrm_(0), lis_(0) {}
  98
  99   virtual ~RegAllocBase() {}
 100
 101   // A RegAlloc pass should call this before allocatePhysRegs.
 102   void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis);
 103
 104   // The top-level driver. The output is a VirtRegMap that us updated with
 105   // physical register assignments.
 106   //
 107   // If an implementation wants to override the LiveInterval comparator, we
 108   // should modify this interface to allow passing in an instance derived from
 109   // LiveVirtRegQueue.
 110   void allocatePhysRegs();
 111
 112   // A RegAlloc pass should override this to provide the allocation heuristics.
 113   // Each call must guarantee forward progess by returning an available PhysReg
 114   // or new set of split live virtual registers. It is up to the splitter to
 115   // converge quickly toward fully spilled live ranges.
 116   virtual unsigned selectOrSplit(LiveInterval &lvr,
 117                                  SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
 118
 119   // A RegAlloc pass should call this when PassManager releases its memory.
 120   virtual void releaseMemory();
 121
 122   // Helper for checking interference between a live virtual register and a
 123   // physical register, including all its register aliases.
 124   bool checkPhysRegInterference(LiveIntervalUnion::Query &query, unsigned preg);
 125
 126 private:
 127   void seedLiveVirtRegs(LiveVirtRegQueue &lvrQ);
 128 };
 129
 130 } // end namespace llvm
 131
 132 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)