lib/CodeGen/SelectionDAG/InstrEmitter.cpp

   1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This implements the Emit routines for the SelectionDAG class, which creates
  11 // MachineInstrs based on the decisions of the SelectionDAG instruction
  12 // selection.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #define DEBUG_TYPE "instr-emitter"
  17 #include "InstrEmitter.h"
  18 #include "SDNodeDbgValue.h"
  19 #include "llvm/CodeGen/MachineConstantPool.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/CodeGen/MachineRegisterInfo.h"
  23 #include "llvm/Target/TargetData.h"
  24 #include "llvm/Target/TargetMachine.h"
  25 #include "llvm/Target/TargetInstrInfo.h"
  26 #include "llvm/Target/TargetLowering.h"
  27 #include "llvm/ADT/Statistic.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 #include "llvm/Support/MathExtras.h"
  31 using namespace llvm;
  32
  33 /// CountResults - The results of target nodes have register or immediate
  34 /// operands first, then an optional chain, and optional flag operands (which do
  35 /// not go into the resulting MachineInstr).
  36 unsigned InstrEmitter::CountResults(SDNode *Node) {
  37   unsigned N = Node->getNumValues();
  38   while (N && Node->getValueType(N - 1) == MVT::Flag)
  39     --N;
  40   if (N && Node->getValueType(N - 1) == MVT::Other)
  41     --N;    // Skip over chain result.
  42   return N;
  43 }
  44
  45 /// CountOperands - The inputs to target nodes have any actual inputs first,
  46 /// followed by an optional chain operand, then an optional flag operand.
  47 /// Compute the number of actual operands that will go into the resulting
  48 /// MachineInstr.
  49 unsigned InstrEmitter::CountOperands(SDNode *Node) {
  50   unsigned N = Node->getNumOperands();
  51   while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
  52     --N;
  53   if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
  54     --N; // Ignore chain if it exists.
  55   return N;
  56 }
  57
  58 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
  59 /// implicit physical register output.
  60 void InstrEmitter::
  61 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
  62                 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
  63   unsigned VRBase = 0;
  64   if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
  65     // Just use the input register directly!
  66     SDValue Op(Node, ResNo);
  67     if (IsClone)
  68       VRBaseMap.erase(Op);
  69     bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
  70     isNew = isNew; // Silence compiler warning.
  71     assert(isNew && "Node emitted out of order - early");
  72     return;
  73   }
  74
  75   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
  76   // the CopyToReg'd destination register instead of creating a new vreg.
  77   bool MatchReg = true;
  78   const TargetRegisterClass *UseRC = NULL;
  79   if (!IsClone && !IsCloned)
  80     for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
  81          UI != E; ++UI) {
  82       SDNode *User = *UI;
  83       bool Match = true;
  84       if (User->getOpcode() == ISD::CopyToReg &&
  85           User->getOperand(2).getNode() == Node &&
  86           User->getOperand(2).getResNo() == ResNo) {
  87         unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
  88         if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
  89           VRBase = DestReg;
  90           Match = false;
  91         } else if (DestReg != SrcReg)
  92           Match = false;
  93       } else {
  94         for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
  95           SDValue Op = User->getOperand(i);
  96           if (Op.getNode() != Node || Op.getResNo() != ResNo)
  97             continue;
  98           EVT VT = Node->getValueType(Op.getResNo());
  99           if (VT == MVT::Other || VT == MVT::Flag)
 100             continue;
 101           Match = false;
 102           if (User->isMachineOpcode()) {
 103             const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
 104             const TargetRegisterClass *RC = 0;
 105             if (i+II.getNumDefs() < II.getNumOperands())
 106               RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
 107             if (!UseRC)
 108               UseRC = RC;
 109             else if (RC) {
 110               const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC);
 111               // If multiple uses expect disjoint register classes, we emit
 112               // copies in AddRegisterOperand.
 113               if (ComRC)
 114                 UseRC = ComRC;
 115             }
 116           }
 117         }
 118       }
 119       MatchReg &= Match;
 120       if (VRBase)
 121         break;
 122     }
 123
 124   EVT VT = Node->getValueType(ResNo);
 125   const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
 126   SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
 127
 128   // Figure out the register class to create for the destreg.
 129   if (VRBase) {
 130     DstRC = MRI->getRegClass(VRBase);
 131   } else if (UseRC) {
 132     assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
 133     DstRC = UseRC;
 134   } else {
 135     DstRC = TLI->getRegClassFor(VT);
 136   }
 137
 138   // If all uses are reading from the src physical register and copying the
 139   // register is either impossible or very expensive, then don't create a copy.
 140   if (MatchReg && SrcRC->getCopyCost() < 0) {
 141     VRBase = SrcReg;
 142   } else {
 143     // Create the reg, emit the copy.
 144     VRBase = MRI->createVirtualRegister(DstRC);
 145     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
 146             VRBase).addReg(SrcReg);
 147   }
 148
 149   SDValue Op(Node, ResNo);
 150   if (IsClone)
 151     VRBaseMap.erase(Op);
 152   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 153   isNew = isNew; // Silence compiler warning.
 154   assert(isNew && "Node emitted out of order - early");
 155 }
 156
 157 /// getDstOfCopyToRegUse - If the only use of the specified result number of
 158 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
 159 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
 160                                                 unsigned ResNo) const {
 161   if (!Node->hasOneUse())
 162     return 0;
 163
 164   SDNode *User = *Node->use_begin();
 165   if (User->getOpcode() == ISD::CopyToReg &&
 166       User->getOperand(2).getNode() == Node &&
 167       User->getOperand(2).getResNo() == ResNo) {
 168     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 169     if (TargetRegisterInfo::isVirtualRegister(Reg))
 170       return Reg;
 171   }
 172   return 0;
 173 }
 174
 175 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
 176                                        const TargetInstrDesc &II,
 177                                        bool IsClone, bool IsCloned,
 178                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
 179   assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
 180          "IMPLICIT_DEF should have been handled as a special case elsewhere!");
 181
 182   for (unsigned i = 0; i < II.getNumDefs(); ++i) {
 183     // If the specific node value is only used by a CopyToReg and the dest reg
 184     // is a vreg in the same register class, use the CopyToReg'd destination
 185     // register instead of creating a new vreg.
 186     unsigned VRBase = 0;
 187     const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
 188     if (II.OpInfo[i].isOptionalDef()) {
 189       // Optional def must be a physical register.
 190       unsigned NumResults = CountResults(Node);
 191       VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
 192       assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
 193       MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 194     }
 195
 196     if (!VRBase && !IsClone && !IsCloned)
 197       for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
 198            UI != E; ++UI) {
 199         SDNode *User = *UI;
 200         if (User->getOpcode() == ISD::CopyToReg &&
 201             User->getOperand(2).getNode() == Node &&
 202             User->getOperand(2).getResNo() == i) {
 203           unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 204           if (TargetRegisterInfo::isVirtualRegister(Reg)) {
 205             const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
 206             if (RegRC == RC) {
 207               VRBase = Reg;
 208               MI->addOperand(MachineOperand::CreateReg(Reg, true));
 209               break;
 210             }
 211           }
 212         }
 213       }
 214
 215     // Create the result registers for this node and add the result regs to
 216     // the machine instruction.
 217     if (VRBase == 0) {
 218       assert(RC && "Isn't a register operand!");
 219       VRBase = MRI->createVirtualRegister(RC);
 220       MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 221     }
 222
 223     SDValue Op(Node, i);
 224     if (IsClone)
 225       VRBaseMap.erase(Op);
 226     bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 227     isNew = isNew; // Silence compiler warning.
 228     assert(isNew && "Node emitted out of order - early");
 229   }
 230 }
 231
 232 /// getVR - Return the virtual register corresponding to the specified result
 233 /// of the specified node.
 234 unsigned InstrEmitter::getVR(SDValue Op,
 235                              DenseMap<SDValue, unsigned> &VRBaseMap) {
 236   if (Op.isMachineOpcode() &&
 237       Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
 238     // Add an IMPLICIT_DEF instruction before every use.
 239     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
 240     // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
 241     // does not include operand register class info.
 242     if (!VReg) {
 243       const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
 244       VReg = MRI->createVirtualRegister(RC);
 245     }
 246     BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
 247             TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
 248     return VReg;
 249   }
 250
 251   DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
 252   assert(I != VRBaseMap.end() && "Node emitted out of order - late");
 253   return I->second;
 254 }
 255
 256
 257 /// AddRegisterOperand - Add the specified register as an operand to the
 258 /// specified machine instr. Insert register copies if the register is
 259 /// not in the required register class.
 260 void
 261 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
 262                                  unsigned IIOpNum,
 263                                  const TargetInstrDesc *II,
 264                                  DenseMap<SDValue, unsigned> &VRBaseMap,
 265                                  bool IsDebug, bool IsClone, bool IsCloned) {
 266   assert(Op.getValueType() != MVT::Other &&
 267          Op.getValueType() != MVT::Flag &&
 268          "Chain and flag operands should occur at end of operand list!");
 269   // Get/emit the operand.
 270   unsigned VReg = getVR(Op, VRBaseMap);
 271   assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
 272
 273   const TargetInstrDesc &TID = MI->getDesc();
 274   bool isOptDef = IIOpNum < TID.getNumOperands() &&
 275     TID.OpInfo[IIOpNum].isOptionalDef();
 276
 277   // If the instruction requires a register in a different class, create
 278   // a new virtual register and copy the value into it.
 279   if (II) {
 280     const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
 281     const TargetRegisterClass *DstRC = 0;
 282     if (IIOpNum < II->getNumOperands())
 283       DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
 284     assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
 285            "Don't have operand info for this instruction!");
 286     if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
 287       unsigned NewVReg = MRI->createVirtualRegister(DstRC);
 288       BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
 289               TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
 290       VReg = NewVReg;
 291     }
 292   }
 293
 294   // If this value has only one use, that use is a kill. This is a
 295   // conservative approximation. InstrEmitter does trivial coalescing
 296   // with CopyFromReg nodes, so don't emit kill flags for them.
 297   // Avoid kill flags on Schedule cloned nodes, since there will be
 298   // multiple uses.
 299   // Tied operands are never killed, so we need to check that. And that
 300   // means we need to determine the index of the operand.
 301   bool isKill = Op.hasOneUse() &&
 302                 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
 303                 !IsDebug &&
 304                 !(IsClone || IsCloned);
 305   if (isKill) {
 306     unsigned Idx = MI->getNumOperands();
 307     while (Idx > 0 &&
 308            MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
 309       --Idx;
 310     bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1;
 311     if (isTied)
 312       isKill = false;
 313   }
 314
 315   MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
 316                                            false/*isImp*/, isKill,
 317                                            false/*isDead*/, false/*isUndef*/,
 318                                            false/*isEarlyClobber*/,
 319                                            0/*SubReg*/, IsDebug));
 320 }
 321
 322 /// AddOperand - Add the specified operand to the specified machine instr.  II
 323 /// specifies the instruction information for the node, and IIOpNum is the
 324 /// operand number (in the II) that we are adding. IIOpNum and II are used for
 325 /// assertions only.
 326 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
 327                               unsigned IIOpNum,
 328                               const TargetInstrDesc *II,
 329                               DenseMap<SDValue, unsigned> &VRBaseMap,
 330                               bool IsDebug, bool IsClone, bool IsCloned) {
 331   if (Op.isMachineOpcode()) {
 332     AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
 333                        IsDebug, IsClone, IsCloned);
 334   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 335     MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
 336   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
 337     const ConstantFP *CFP = F->getConstantFPValue();
 338     MI->addOperand(MachineOperand::CreateFPImm(CFP));
 339   } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
 340     MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
 341   } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
 342     MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
 343                                             TGA->getTargetFlags()));
 344   } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
 345     MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
 346   } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
 347     MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
 348   } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
 349     MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
 350                                              JT->getTargetFlags()));
 351   } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
 352     int Offset = CP->getOffset();
 353     unsigned Align = CP->getAlignment();
 354     const Type *Type = CP->getType();
 355     // MachineConstantPool wants an explicit alignment.
 356     if (Align == 0) {
 357       Align = TM->getTargetData()->getPrefTypeAlignment(Type);
 358       if (Align == 0) {
 359         // Alignment of vector types.  FIXME!
 360         Align = TM->getTargetData()->getTypeAllocSize(Type);
 361       }
 362     }
 363
 364     unsigned Idx;
 365     MachineConstantPool *MCP = MF->getConstantPool();
 366     if (CP->isMachineConstantPoolEntry())
 367       Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
 368     else
 369       Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
 370     MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
 371                                              CP->getTargetFlags()));
 372   } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
 373     MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
 374                                             ES->getTargetFlags()));
 375   } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
 376     MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
 377                                             BA->getTargetFlags()));
 378   } else {
 379     assert(Op.getValueType() != MVT::Other &&
 380            Op.getValueType() != MVT::Flag &&
 381            "Chain and flag operands should occur at end of operand list!");
 382     AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
 383                        IsDebug, IsClone, IsCloned);
 384   }
 385 }
 386
 387 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
 388 /// "SubIdx"'th sub-register class is the specified register class and whose
 389 /// type matches the specified type.
 390 static const TargetRegisterClass*
 391 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
 392                          unsigned SubIdx, EVT VT) {
 393   // Pick the register class of the superegister for this type
 394   for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
 395          E = TRC->superregclasses_end(); I != E; ++I)
 396     if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
 397       return *I;
 398   assert(false && "Couldn't find the register class");
 399   return 0;
 400 }
 401
 402 /// EmitSubregNode - Generate machine code for subreg nodes.
 403 ///
 404 void InstrEmitter::EmitSubregNode(SDNode *Node,
 405                                   DenseMap<SDValue, unsigned> &VRBaseMap,
 406                                   bool IsClone, bool IsCloned) {
 407   unsigned VRBase = 0;
 408   unsigned Opc = Node->getMachineOpcode();
 409
 410   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
 411   // the CopyToReg'd destination register instead of creating a new vreg.
 412   for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
 413        UI != E; ++UI) {
 414     SDNode *User = *UI;
 415     if (User->getOpcode() == ISD::CopyToReg &&
 416         User->getOperand(2).getNode() == Node) {
 417       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 418       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
 419         VRBase = DestReg;
 420         break;
 421       }
 422     }
 423   }
 424
 425   if (Opc == TargetOpcode::EXTRACT_SUBREG) {
 426     // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub
 427     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
 428
 429     // Figure out the register class to create for the destreg.
 430     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
 431     const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
 432     const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
 433     assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
 434
 435     // Figure out the register class to create for the destreg.
 436     // Note that if we're going to directly use an existing register,
 437     // it must be precisely the required class, and not a subclass
 438     // thereof.
 439     if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
 440       // Create the reg
 441       assert(SRC && "Couldn't find source register class");
 442       VRBase = MRI->createVirtualRegister(SRC);
 443     }
 444
 445     // Create the extract_subreg machine instruction.
 446     MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
 447                                TII->get(TargetOpcode::COPY), VRBase);
 448
 449     // Add source, and subreg index
 450     AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false,
 451                IsClone, IsCloned);
 452     assert(TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg()) &&
 453            "Cannot yet extract from physregs");
 454     MI->getOperand(1).setSubReg(SubIdx);
 455     MBB->insert(InsertPos, MI);
 456   } else if (Opc == TargetOpcode::INSERT_SUBREG ||
 457              Opc == TargetOpcode::SUBREG_TO_REG) {
 458     SDValue N0 = Node->getOperand(0);
 459     SDValue N1 = Node->getOperand(1);
 460     SDValue N2 = Node->getOperand(2);
 461     unsigned SubReg = getVR(N1, VRBaseMap);
 462     unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
 463     const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
 464     const TargetRegisterClass *SRC =
 465       getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0));
 466
 467     // Figure out the register class to create for the destreg.
 468     // Note that if we're going to directly use an existing register,
 469     // it must be precisely the required class, and not a subclass
 470     // thereof.
 471     if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
 472       // Create the reg
 473       assert(SRC && "Couldn't find source register class");
 474       VRBase = MRI->createVirtualRegister(SRC);
 475     }
 476
 477     // Create the insert_subreg or subreg_to_reg machine instruction.
 478     MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
 479     MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 480
 481     // If creating a subreg_to_reg, then the first input operand
 482     // is an implicit value immediate, otherwise it's a register
 483     if (Opc == TargetOpcode::SUBREG_TO_REG) {
 484       const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
 485       MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
 486     } else
 487       AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
 488                  IsClone, IsCloned);
 489     // Add the subregster being inserted
 490     AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
 491                IsClone, IsCloned);
 492     MI->addOperand(MachineOperand::CreateImm(SubIdx));
 493     MBB->insert(InsertPos, MI);
 494   } else
 495     llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
 496
 497   SDValue Op(Node, 0);
 498   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 499   isNew = isNew; // Silence compiler warning.
 500   assert(isNew && "Node emitted out of order - early");
 501 }
 502
 503 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
 504 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
 505 /// register is constrained to be in a particular register class.
 506 ///
 507 void
 508 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
 509                                      DenseMap<SDValue, unsigned> &VRBaseMap) {
 510   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
 511
 512   // Create the new VReg in the destination class and emit a copy.
 513   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
 514   const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
 515   unsigned NewVReg = MRI->createVirtualRegister(DstRC);
 516   BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
 517     NewVReg).addReg(VReg);
 518
 519   SDValue Op(Node, 0);
 520   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
 521   isNew = isNew; // Silence compiler warning.
 522   assert(isNew && "Node emitted out of order - early");
 523 }
 524
 525 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
 526 ///
 527 void InstrEmitter::EmitRegSequence(SDNode *Node,
 528                                   DenseMap<SDValue, unsigned> &VRBaseMap,
 529                                   bool IsClone, bool IsCloned) {
 530   const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0));
 531   unsigned NewVReg = MRI->createVirtualRegister(RC);
 532   MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
 533                              TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
 534   unsigned NumOps = Node->getNumOperands();
 535   assert((NumOps & 1) == 0 &&
 536          "REG_SEQUENCE must have an even number of operands!");
 537   const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
 538   for (unsigned i = 0; i != NumOps; ++i) {
 539     SDValue Op = Node->getOperand(i);
 540     if (i & 1) {
 541       unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
 542       unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
 543       const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
 544       const TargetRegisterClass *SRC =
 545         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
 546       if (!SRC)
 547         llvm_unreachable("Invalid subregister index in REG_SEQUENCE");
 548       if (SRC != RC) {
 549         MRI->setRegClass(NewVReg, SRC);
 550         RC = SRC;
 551       }
 552     }
 553     AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
 554                IsClone, IsCloned);
 555   }
 556
 557   MBB->insert(InsertPos, MI);
 558   SDValue Op(Node, 0);
 559   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
 560   isNew = isNew; // Silence compiler warning.
 561   assert(isNew && "Node emitted out of order - early");
 562 }
 563
 564 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
 565 ///
 566 MachineInstr *
 567 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
 568                            DenseMap<SDValue, unsigned> &VRBaseMap) {
 569   uint64_t Offset = SD->getOffset();
 570   MDNode* MDPtr = SD->getMDPtr();
 571   DebugLoc DL = SD->getDebugLoc();
 572
 573   if (SD->getKind() == SDDbgValue::FRAMEIX) {
 574     // Stack address; this needs to be lowered in target-dependent fashion.
 575     // EmitTargetCodeForFrameDebugValue is responsible for allocation.
 576     unsigned FrameIx = SD->getFrameIx();
 577     return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
 578   }
 579   // Otherwise, we're going to create an instruction here.
 580   const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
 581   MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
 582   if (SD->getKind() == SDDbgValue::SDNODE) {
 583     SDNode *Node = SD->getSDNode();
 584     SDValue Op = SDValue(Node, SD->getResNo());
 585     // It's possible we replaced this SDNode with other(s) and therefore
 586     // didn't generate code for it.  It's better to catch these cases where
 587     // they happen and transfer the debug info, but trying to guarantee that
 588     // in all cases would be very fragile; this is a safeguard for any
 589     // that were missed.
 590     DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
 591     if (I==VRBaseMap.end())
 592       MIB.addReg(0U);       // undef
 593     else
 594       AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
 595                  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
 596   } else if (SD->getKind() == SDDbgValue::CONST) {
 597     const Value *V = SD->getConst();
 598     if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
 599       // FIXME: SDDbgValue constants aren't updated with legalization, so it's
 600       // possible to have i128 constants in them at this point. Dwarf writer
 601       // does not handle i128 constants at the moment so, as a crude workaround,
 602       // just drop the debug info if this happens.
 603       if (!CI->getValue().isSignedIntN(64))
 604         MIB.addReg(0U);
 605       else
 606         MIB.addImm(CI->getSExtValue());
 607     } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
 608       MIB.addFPImm(CF);
 609     } else {
 610       // Could be an Undef.  In any case insert an Undef so we can see what we
 611       // dropped.
 612       MIB.addReg(0U);
 613     }
 614   } else {
 615     // Insert an Undef so we can see what we dropped.
 616     MIB.addReg(0U);
 617   }
 618
 619   MIB.addImm(Offset).addMetadata(MDPtr);
 620   return &*MIB;
 621 }
 622
 623 /// EmitMachineNode - Generate machine code for a target-specific node and
 624 /// needed dependencies.
 625 ///
 626 void InstrEmitter::
 627 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
 628                 DenseMap<SDValue, unsigned> &VRBaseMap) {
 629   unsigned Opc = Node->getMachineOpcode();
 630
 631   // Handle subreg insert/extract specially
 632   if (Opc == TargetOpcode::EXTRACT_SUBREG ||
 633       Opc == TargetOpcode::INSERT_SUBREG ||
 634       Opc == TargetOpcode::SUBREG_TO_REG) {
 635     EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
 636     return;
 637   }
 638
 639   // Handle COPY_TO_REGCLASS specially.
 640   if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
 641     EmitCopyToRegClassNode(Node, VRBaseMap);
 642     return;
 643   }
 644
 645   // Handle REG_SEQUENCE specially.
 646   if (Opc == TargetOpcode::REG_SEQUENCE) {
 647     EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
 648     return;
 649   }
 650
 651   if (Opc == TargetOpcode::IMPLICIT_DEF)
 652     // We want a unique VR for each IMPLICIT_DEF use.
 653     return;
 654
 655   const TargetInstrDesc &II = TII->get(Opc);
 656   unsigned NumResults = CountResults(Node);
 657   unsigned NodeOperands = CountOperands(Node);
 658   bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
 659 #ifndef NDEBUG
 660   unsigned NumMIOperands = NodeOperands + NumResults;
 661   if (II.isVariadic())
 662     assert(NumMIOperands >= II.getNumOperands() &&
 663            "Too few operands for a variadic node!");
 664   else
 665     assert(NumMIOperands >= II.getNumOperands() &&
 666            NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() &&
 667            "#operands for dag node doesn't match .td file!");
 668 #endif
 669
 670   // Create the new machine instruction.
 671   MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
 672
 673   // The MachineInstr constructor adds implicit-def operands. Scan through
 674   // these to determine which are dead.
 675   if (MI->getNumOperands() != 0 &&
 676       Node->getValueType(Node->getNumValues()-1) == MVT::Flag) {
 677     // First, collect all used registers.
 678     SmallVector<unsigned, 8> UsedRegs;
 679     for (SDNode *F = Node->getFlaggedUser(); F; F = F->getFlaggedUser())
 680       if (F->getOpcode() == ISD::CopyFromReg)
 681         UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
 682       else {
 683         // Collect declared implicit uses.
 684         const TargetInstrDesc &TID = TII->get(F->getMachineOpcode());
 685         UsedRegs.append(TID.getImplicitUses(),
 686                         TID.getImplicitUses() + TID.getNumImplicitUses());
 687         // In addition to declared implicit uses, we must also check for
 688         // direct RegisterSDNode operands.
 689         for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
 690           if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
 691             unsigned Reg = R->getReg();
 692             if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg))
 693               UsedRegs.push_back(Reg);
 694           }
 695       }
 696     // Then mark unused registers as dead.
 697     MI->setPhysRegsDeadExcept(UsedRegs, *TRI);
 698   }
 699
 700   // Add result register values for things that are defined by this
 701   // instruction.
 702   if (NumResults)
 703     CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
 704
 705   // Emit all of the actual operands of this instruction, adding them to the
 706   // instruction as appropriate.
 707   bool HasOptPRefs = II.getNumDefs() > NumResults;
 708   assert((!HasOptPRefs || !HasPhysRegOuts) &&
 709          "Unable to cope with optional defs and phys regs defs!");
 710   unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
 711   for (unsigned i = NumSkip; i != NodeOperands; ++i)
 712     AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
 713                VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
 714
 715   // Transfer all of the memory reference descriptions of this instruction.
 716   MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
 717                  cast<MachineSDNode>(Node)->memoperands_end());
 718
 719   // Insert the instruction into position in the block. This needs to
 720   // happen before any custom inserter hook is called so that the
 721   // hook knows where in the block to insert the replacement code.
 722   MBB->insert(InsertPos, MI);
 723
 724   if (II.usesCustomInsertionHook()) {
 725     // Insert this instruction into the basic block using a target
 726     // specific inserter which may returns a new basic block.
 727     bool AtEnd = InsertPos == MBB->end();
 728     MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
 729     if (NewMBB != MBB) {
 730       if (AtEnd)
 731         InsertPos = NewMBB->end();
 732       MBB = NewMBB;
 733     }
 734     return;
 735   }
 736
 737   // Additional results must be an physical register def.
 738   if (HasPhysRegOuts) {
 739     for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
 740       unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
 741       if (Node->hasAnyUseOfValue(i))
 742         EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
 743       // If there are no uses, mark the register as dead now, so that
 744       // MachineLICM/Sink can see that it's dead. Don't do this if the
 745       // node has a Flag value, for the benefit of targets still using
 746       // Flag for values in physregs.
 747       else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
 748         MI->addRegisterDead(Reg, TRI);
 749     }
 750   }
 751
 752   // If the instruction has implicit defs and the node doesn't, mark the
 753   // implicit def as dead.  If the node has any flag outputs, we don't do this
 754   // because we don't know what implicit defs are being used by flagged nodes.
 755   if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
 756     if (const unsigned *IDList = II.getImplicitDefs()) {
 757       for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs();
 758            i != e; ++i)
 759         MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI);
 760     }
 761 }
 762
 763 /// EmitSpecialNode - Generate machine code for a target-independent node and
 764 /// needed dependencies.
 765 void InstrEmitter::
 766 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
 767                 DenseMap<SDValue, unsigned> &VRBaseMap) {
 768   switch (Node->getOpcode()) {
 769   default:
 770 #ifndef NDEBUG
 771     Node->dump();
 772 #endif
 773     llvm_unreachable("This target-independent node should have been selected!");
 774     break;
 775   case ISD::EntryToken:
 776     llvm_unreachable("EntryToken should have been excluded from the schedule!");
 777     break;
 778   case ISD::MERGE_VALUES:
 779   case ISD::TokenFactor: // fall thru
 780     break;
 781   case ISD::CopyToReg: {
 782     unsigned SrcReg;
 783     SDValue SrcVal = Node->getOperand(2);
 784     if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
 785       SrcReg = R->getReg();
 786     else
 787       SrcReg = getVR(SrcVal, VRBaseMap);
 788
 789     unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
 790     if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
 791       break;
 792
 793     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
 794             DestReg).addReg(SrcReg);
 795     break;
 796   }
 797   case ISD::CopyFromReg: {
 798     unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
 799     EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
 800     break;
 801   }
 802   case ISD::EH_LABEL: {
 803     MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
 804     BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
 805             TII->get(TargetOpcode::EH_LABEL)).addSym(S);
 806     break;
 807   }
 808
 809   case ISD::INLINEASM: {
 810     unsigned NumOps = Node->getNumOperands();
 811     if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
 812       --NumOps;  // Ignore the flag operand.
 813
 814     // Create the inline asm machine instruction.
 815     MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
 816                                TII->get(TargetOpcode::INLINEASM));
 817
 818     // Add the asm string as an external symbol operand.
 819     SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
 820     const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
 821     MI->addOperand(MachineOperand::CreateES(AsmStr));
 822
 823     // Add the isAlignStack bit.
 824     int64_t isAlignStack =
 825       cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_IsAlignStack))->
 826                           getZExtValue();
 827     MI->addOperand(MachineOperand::CreateImm(isAlignStack));
 828
 829     // Add all of the operand registers to the instruction.
 830     for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
 831       unsigned Flags =
 832         cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
 833       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
 834
 835       MI->addOperand(MachineOperand::CreateImm(Flags));
 836       ++i;  // Skip the ID value.
 837
 838       switch (InlineAsm::getKind(Flags)) {
 839       default: llvm_unreachable("Bad flags!");
 840         case InlineAsm::Kind_RegDef:
 841         for (; NumVals; --NumVals, ++i) {
 842           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
 843           // FIXME: Add dead flags for physical and virtual registers defined.
 844           // For now, mark physical register defs as implicit to help fast
 845           // regalloc. This makes inline asm look a lot like calls.
 846           MI->addOperand(MachineOperand::CreateReg(Reg, true,
 847                        /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg)));
 848         }
 849         break;
 850       case InlineAsm::Kind_RegDefEarlyClobber:
 851         for (; NumVals; --NumVals, ++i) {
 852           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
 853           MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true,
 854                          /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg),
 855                                                    /*isKill=*/ false,
 856                                                    /*isDead=*/ false,
 857                                                    /*isUndef=*/false,
 858                                                    /*isEarlyClobber=*/ true));
 859         }
 860         break;
 861       case InlineAsm::Kind_RegUse:  // Use of register.
 862       case InlineAsm::Kind_Imm:  // Immediate.
 863       case InlineAsm::Kind_Mem:  // Addressing mode.
 864         // The addressing mode has been selected, just add all of the
 865         // operands to the machine instruction.
 866         for (; NumVals; --NumVals, ++i)
 867           AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
 868                      /*IsDebug=*/false, IsClone, IsCloned);
 869         break;
 870       }
 871     }
 872
 873     // Get the mdnode from the asm if it exists and add it to the instruction.
 874     SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
 875     const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
 876     if (MD)
 877       MI->addOperand(MachineOperand::CreateMetadata(MD));
 878
 879     MBB->insert(InsertPos, MI);
 880     break;
 881   }
 882   }
 883 }
 884
 885 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
 886 /// at the given position in the given block.
 887 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
 888                            MachineBasicBlock::iterator insertpos)
 889   : MF(mbb->getParent()),
 890     MRI(&MF->getRegInfo()),
 891     TM(&MF->getTarget()),
 892     TII(TM->getInstrInfo()),
 893     TRI(TM->getRegisterInfo()),
 894     TLI(TM->getTargetLowering()),
 895     MBB(mbb), InsertPos(insertpos) {
 896 }