Fixed some bugs.
[llvm/zpu.git] / lib / CodeGen / SelectionDAG / InstrEmitter.h
blob02c044c3f8f1ef8da9823d0042593b6277ba08f1
1 //===---- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This declares the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
12 // selection.
14 //===----------------------------------------------------------------------===//
16 #ifndef INSTREMITTER_H
17 #define INSTREMITTER_H
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/ADT/DenseMap.h"
23 namespace llvm {
25 class TargetInstrDesc;
26 class SDDbgValue;
28 class InstrEmitter {
29 MachineFunction *MF;
30 MachineRegisterInfo *MRI;
31 const TargetMachine *TM;
32 const TargetInstrInfo *TII;
33 const TargetRegisterInfo *TRI;
34 const TargetLowering *TLI;
36 MachineBasicBlock *MBB;
37 MachineBasicBlock::iterator InsertPos;
39 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
40 /// implicit physical register output.
41 void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
42 bool IsClone, bool IsCloned,
43 unsigned SrcReg,
44 DenseMap<SDValue, unsigned> &VRBaseMap);
46 /// getDstOfCopyToRegUse - If the only use of the specified result number of
47 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
48 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node,
49 unsigned ResNo) const;
51 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
52 const TargetInstrDesc &II,
53 bool IsClone, bool IsCloned,
54 DenseMap<SDValue, unsigned> &VRBaseMap);
56 /// getVR - Return the virtual register corresponding to the specified result
57 /// of the specified node.
58 unsigned getVR(SDValue Op,
59 DenseMap<SDValue, unsigned> &VRBaseMap);
61 /// AddRegisterOperand - Add the specified register as an operand to the
62 /// specified machine instr. Insert register copies if the register is
63 /// not in the required register class.
64 void AddRegisterOperand(MachineInstr *MI, SDValue Op,
65 unsigned IIOpNum,
66 const TargetInstrDesc *II,
67 DenseMap<SDValue, unsigned> &VRBaseMap,
68 bool IsDebug, bool IsClone, bool IsCloned);
70 /// AddOperand - Add the specified operand to the specified machine instr. II
71 /// specifies the instruction information for the node, and IIOpNum is the
72 /// operand number (in the II) that we are adding. IIOpNum and II are used for
73 /// assertions only.
74 void AddOperand(MachineInstr *MI, SDValue Op,
75 unsigned IIOpNum,
76 const TargetInstrDesc *II,
77 DenseMap<SDValue, unsigned> &VRBaseMap,
78 bool IsDebug, bool IsClone, bool IsCloned);
80 /// EmitSubregNode - Generate machine code for subreg nodes.
81 ///
82 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap,
83 bool IsClone, bool IsCloned);
85 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
86 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
87 /// register is constrained to be in a particular register class.
88 ///
89 void EmitCopyToRegClassNode(SDNode *Node,
90 DenseMap<SDValue, unsigned> &VRBaseMap);
92 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
93 ///
94 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap,
95 bool IsClone, bool IsCloned);
96 public:
97 /// CountResults - The results of target nodes have register or immediate
98 /// operands first, then an optional chain, and optional flag operands
99 /// (which do not go into the machine instrs.)
100 static unsigned CountResults(SDNode *Node);
102 /// CountOperands - The inputs to target nodes have any actual inputs first,
103 /// followed by an optional chain operand, then flag operands. Compute
104 /// the number of actual operands that will go into the resulting
105 /// MachineInstr.
106 static unsigned CountOperands(SDNode *Node);
108 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
110 MachineInstr *EmitDbgValue(SDDbgValue *SD,
111 DenseMap<SDValue, unsigned> &VRBaseMap);
113 /// EmitNode - Generate machine code for a node and needed dependencies.
115 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
116 DenseMap<SDValue, unsigned> &VRBaseMap) {
117 if (Node->isMachineOpcode())
118 EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap);
119 else
120 EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap);
123 /// getBlock - Return the current basic block.
124 MachineBasicBlock *getBlock() { return MBB; }
126 /// getInsertPos - Return the current insertion position.
127 MachineBasicBlock::iterator getInsertPos() { return InsertPos; }
129 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
130 /// at the given position in the given block.
131 InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos);
133 private:
134 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
135 DenseMap<SDValue, unsigned> &VRBaseMap);
136 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
137 DenseMap<SDValue, unsigned> &VRBaseMap);
142 #endif