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Fixed some bugs.
[llvm/zpu.git] / lib / CodeGen / SelectionDAG / LegalizeIntegerTypes.cpp
blobe67ceffc2b0d2a850ffc8bb3a7e682e6706665d3
1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
17 // targets).
18 //
19 //===----------------------------------------------------------------------===//
20
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 using namespace llvm;
26
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
30
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
38
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
41 return;
42
43 switch (N->getOpcode()) {
44 default:
45 #ifndef NDEBUG
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
48 #endif
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
52 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
56 case ISD::CONVERT_RNDSAT:
57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
61 case ISD::EXTRACT_VECTOR_ELT:
62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
68 case ISD::SIGN_EXTEND_INREG:
69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
75
76 case ISD::SIGN_EXTEND:
77 case ISD::ZERO_EXTEND:
78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
79
80 case ISD::FP_TO_SINT:
81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
82
83 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
84
85 case ISD::AND:
86 case ISD::OR:
87 case ISD::XOR:
88 case ISD::ADD:
89 case ISD::SUB:
90 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
91
92 case ISD::SDIV:
93 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
94
95 case ISD::UDIV:
96 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
97
98 case ISD::SADDO:
99 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
100 case ISD::UADDO:
101 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
102 case ISD::SMULO:
103 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
104
105 case ISD::ATOMIC_LOAD_ADD:
106 case ISD::ATOMIC_LOAD_SUB:
107 case ISD::ATOMIC_LOAD_AND:
108 case ISD::ATOMIC_LOAD_OR:
109 case ISD::ATOMIC_LOAD_XOR:
110 case ISD::ATOMIC_LOAD_NAND:
111 case ISD::ATOMIC_LOAD_MIN:
112 case ISD::ATOMIC_LOAD_MAX:
113 case ISD::ATOMIC_LOAD_UMIN:
114 case ISD::ATOMIC_LOAD_UMAX:
115 case ISD::ATOMIC_SWAP:
116 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
117
118 case ISD::ATOMIC_CMP_SWAP:
119 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
120 }
121
122 // If the result is null then the sub-method took care of registering it.
123 if (Res.getNode())
124 SetPromotedInteger(SDValue(N, ResNo), Res);
125 }
126
127 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
128 // Sign-extend the new bits, and continue the assertion.
129 SDValue Op = SExtPromotedInteger(N->getOperand(0));
130 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
131 Op.getValueType(), Op, N->getOperand(1));
132 }
133
134 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
135 // Zero the new bits, and continue the assertion.
136 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
137 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
138 Op.getValueType(), Op, N->getOperand(1));
139 }
140
141 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
142 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
143 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
144 N->getMemoryVT(),
145 N->getChain(), N->getBasePtr(),
146 Op2, N->getMemOperand());
147 // Legalized the chain result - switch anything that used the old chain to
148 // use the new one.
149 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
150 return Res;
151 }
152
153 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
154 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
155 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
156 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
157 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
158 Op2, Op3, N->getMemOperand());
159 // Legalized the chain result - switch anything that used the old chain to
160 // use the new one.
161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
162 return Res;
163 }
164
165 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
166 SDValue InOp = N->getOperand(0);
167 EVT InVT = InOp.getValueType();
168 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
169 EVT OutVT = N->getValueType(0);
170 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
171 DebugLoc dl = N->getDebugLoc();
172
173 switch (getTypeAction(InVT)) {
174 default:
175 assert(false && "Unknown type action!");
176 break;
177 case Legal:
178 break;
179 case PromoteInteger:
180 if (NOutVT.bitsEq(NInVT))
181 // The input promotes to the same size. Convert the promoted value.
182 return DAG.getNode(ISD::BIT_CONVERT, dl,
183 NOutVT, GetPromotedInteger(InOp));
184 break;
185 case SoftenFloat:
186 // Promote the integer operand by hand.
187 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
188 case ExpandInteger:
189 case ExpandFloat:
190 break;
191 case ScalarizeVector:
192 // Convert the element to an integer and promote it by hand.
193 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
194 BitConvertToInteger(GetScalarizedVector(InOp)));
195 case SplitVector: {
196 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
197 // pieces of the input into integers and reassemble in the final type.
198 SDValue Lo, Hi;
199 GetSplitVector(N->getOperand(0), Lo, Hi);
200 Lo = BitConvertToInteger(Lo);
201 Hi = BitConvertToInteger(Hi);
202
203 if (TLI.isBigEndian())
204 std::swap(Lo, Hi);
205
206 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
207 EVT::getIntegerVT(*DAG.getContext(),
208 NOutVT.getSizeInBits()),
209 JoinIntegers(Lo, Hi));
210 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
211 }
212 case WidenVector:
213 if (OutVT.bitsEq(NInVT))
214 // The input is widened to the same size. Convert to the widened value.
215 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
216 }
217
218 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
219 CreateStackStoreLoad(InOp, OutVT));
220 }
221
222 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
223 SDValue Op = GetPromotedInteger(N->getOperand(0));
224 EVT OVT = N->getValueType(0);
225 EVT NVT = Op.getValueType();
226 DebugLoc dl = N->getDebugLoc();
227
228 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
229 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
230 DAG.getConstant(DiffBits, TLI.getPointerTy()));
231 }
232
233 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
234 // The pair element type may be legal, or may not promote to the same type as
235 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
236 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
237 TLI.getTypeToTransformTo(*DAG.getContext(),
238 N->getValueType(0)), JoinIntegers(N->getOperand(0),
239 N->getOperand(1)));
240 }
241
242 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
243 EVT VT = N->getValueType(0);
244 // FIXME there is no actual debug info here
245 DebugLoc dl = N->getDebugLoc();
246 // Zero extend things like i1, sign extend everything else. It shouldn't
247 // matter in theory which one we pick, but this tends to give better code?
248 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
249 SDValue Result = DAG.getNode(Opc, dl,
250 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
251 SDValue(N, 0));
252 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
253 return Result;
254 }
255
256 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
257 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
258 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
259 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
260 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
261 "can only promote integers");
262 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
263 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
264 N->getOperand(1), N->getOperand(2),
265 N->getOperand(3), N->getOperand(4), CvtCode);
266 }
267
268 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
269 // Zero extend to the promoted type and do the count there.
270 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
271 DebugLoc dl = N->getDebugLoc();
272 EVT OVT = N->getValueType(0);
273 EVT NVT = Op.getValueType();
274 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
275 // Subtract off the extra leading bits in the bigger type.
276 return DAG.getNode(ISD::SUB, dl, NVT, Op,
277 DAG.getConstant(NVT.getSizeInBits() -
278 OVT.getSizeInBits(), NVT));
279 }
280
281 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
282 // Zero extend to the promoted type and do the count there.
283 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
284 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
285 }
286
287 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
288 SDValue Op = GetPromotedInteger(N->getOperand(0));
289 EVT OVT = N->getValueType(0);
290 EVT NVT = Op.getValueType();
291 DebugLoc dl = N->getDebugLoc();
292 // The count is the same in the promoted type except if the original
293 // value was zero. This can be handled by setting the bit just off
294 // the top of the original type.
295 APInt TopBit(NVT.getSizeInBits(), 0);
296 TopBit.set(OVT.getSizeInBits());
297 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
298 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
299 }
300
301 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
302 DebugLoc dl = N->getDebugLoc();
303 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
304 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
305 N->getOperand(1));
306 }
307
308 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
309 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
310 unsigned NewOpc = N->getOpcode();
311 DebugLoc dl = N->getDebugLoc();
312
313 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
314 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
315 // and SINT conversions are Custom, there is no way to tell which is
316 // preferable. We choose SINT because that's the right thing on PPC.)
317 if (N->getOpcode() == ISD::FP_TO_UINT &&
318 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
319 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
320 NewOpc = ISD::FP_TO_SINT;
321
322 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
323
324 // Assert that the converted value fits in the original type. If it doesn't
325 // (eg: because the value being converted is too big), then the result of the
326 // original operation was undefined anyway, so the assert is still correct.
327 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
328 ISD::AssertZext : ISD::AssertSext, dl,
329 NVT, Res, DAG.getValueType(N->getValueType(0)));
330 }
331
332 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
333 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
334 DebugLoc dl = N->getDebugLoc();
335
336 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
337
338 return DAG.getNode(ISD::AssertZext, dl,
339 NVT, Res, DAG.getValueType(N->getValueType(0)));
340 }
341
342 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
343 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
344 DebugLoc dl = N->getDebugLoc();
345
346 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
347 SDValue Res = GetPromotedInteger(N->getOperand(0));
348 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
349
350 // If the result and operand types are the same after promotion, simplify
351 // to an in-register extension.
352 if (NVT == Res.getValueType()) {
353 // The high bits are not guaranteed to be anything. Insert an extend.
354 if (N->getOpcode() == ISD::SIGN_EXTEND)
355 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
356 DAG.getValueType(N->getOperand(0).getValueType()));
357 if (N->getOpcode() == ISD::ZERO_EXTEND)
358 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
359 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
360 return Res;
361 }
362 }
363
364 // Otherwise, just extend the original operand all the way to the larger type.
365 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
366 }
367
368 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
369 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
370 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
371 ISD::LoadExtType ExtType =
372 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
373 DebugLoc dl = N->getDebugLoc();
374 SDValue Res = DAG.getExtLoad(ExtType, NVT, dl, N->getChain(), N->getBasePtr(),
375 N->getPointerInfo(),
376 N->getMemoryVT(), N->isVolatile(),
377 N->isNonTemporal(), N->getAlignment());
378
379 // Legalized the chain result - switch anything that used the old chain to
380 // use the new one.
381 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
382 return Res;
383 }
384
385 /// Promote the overflow flag of an overflowing arithmetic node.
386 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
387 // Simply change the return type of the boolean result.
388 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
389 EVT ValueVTs[] = { N->getValueType(0), NVT };
390 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
391 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
392 DAG.getVTList(ValueVTs, 2), Ops, 2);
393
394 // Modified the sum result - switch anything that used the old sum to use
395 // the new one.
396 ReplaceValueWith(SDValue(N, 0), Res);
397
398 return SDValue(Res.getNode(), 1);
399 }
400
401 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
402 if (ResNo == 1)
403 return PromoteIntRes_Overflow(N);
404
405 // The operation overflowed iff the result in the larger type is not the
406 // sign extension of its truncation to the original type.
407 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
408 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
409 EVT OVT = N->getOperand(0).getValueType();
410 EVT NVT = LHS.getValueType();
411 DebugLoc dl = N->getDebugLoc();
412
413 // Do the arithmetic in the larger type.
414 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
415 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
416
417 // Calculate the overflow flag: sign extend the arithmetic result from
418 // the original type.
419 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
420 DAG.getValueType(OVT));
421 // Overflowed if and only if this is not equal to Res.
422 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
423
424 // Use the calculated overflow everywhere.
425 ReplaceValueWith(SDValue(N, 1), Ofl);
426
427 return Res;
428 }
429
430 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
431 // Sign extend the input.
432 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
433 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
434 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
435 LHS.getValueType(), LHS, RHS);
436 }
437
438 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
439 SDValue LHS = GetPromotedInteger(N->getOperand(1));
440 SDValue RHS = GetPromotedInteger(N->getOperand(2));
441 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
442 LHS.getValueType(), N->getOperand(0),LHS,RHS);
443 }
444
445 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
446 SDValue LHS = GetPromotedInteger(N->getOperand(2));
447 SDValue RHS = GetPromotedInteger(N->getOperand(3));
448 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
449 LHS.getValueType(), N->getOperand(0),
450 N->getOperand(1), LHS, RHS, N->getOperand(4));
451 }
452
453 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
454 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
455 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
456 DebugLoc dl = N->getDebugLoc();
457
458 // Get the SETCC result using the canonical SETCC type.
459 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
460 N->getOperand(1), N->getOperand(2));
461
462 // Convert to the expected type.
463 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
464 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
465 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
466 }
467
468 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
469 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
470 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
471 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
472 }
473
474 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
475 SDValue Op = GetPromotedInteger(N->getOperand(0));
476 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
477 Op.getValueType(), Op, N->getOperand(1));
478 }
479
480 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
481 // The input may have strange things in the top bits of the registers, but
482 // these operations don't care. They may have weird bits going out, but
483 // that too is okay if they are integer operations.
484 SDValue LHS = GetPromotedInteger(N->getOperand(0));
485 SDValue RHS = GetPromotedInteger(N->getOperand(1));
486 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
487 LHS.getValueType(), LHS, RHS);
488 }
489
490 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
491 // The input value must be properly sign extended.
492 SDValue Res = SExtPromotedInteger(N->getOperand(0));
493 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
494 Res.getValueType(), Res, N->getOperand(1));
495 }
496
497 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
498 // The input value must be properly zero extended.
499 EVT VT = N->getValueType(0);
500 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
501 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
502 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
503 }
504
505 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
506 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
507 SDValue Res;
508
509 switch (getTypeAction(N->getOperand(0).getValueType())) {
510 default: llvm_unreachable("Unknown type action!");
511 case Legal:
512 case ExpandInteger:
513 Res = N->getOperand(0);
514 break;
515 case PromoteInteger:
516 Res = GetPromotedInteger(N->getOperand(0));
517 break;
518 }
519
520 // Truncate to NVT instead of VT
521 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
522 }
523
524 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
525 if (ResNo == 1)
526 return PromoteIntRes_Overflow(N);
527
528 // The operation overflowed iff the result in the larger type is not the
529 // zero extension of its truncation to the original type.
530 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
531 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
532 EVT OVT = N->getOperand(0).getValueType();
533 EVT NVT = LHS.getValueType();
534 DebugLoc dl = N->getDebugLoc();
535
536 // Do the arithmetic in the larger type.
537 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
538 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
539
540 // Calculate the overflow flag: zero extend the arithmetic result from
541 // the original type.
542 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
543 // Overflowed if and only if this is not equal to Res.
544 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
545
546 // Use the calculated overflow everywhere.
547 ReplaceValueWith(SDValue(N, 1), Ofl);
548
549 return Res;
550 }
551
552 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
553 // Zero extend the input.
554 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
555 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
556 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
557 LHS.getValueType(), LHS, RHS);
558 }
559
560 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
561 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
562 N->getValueType(0)));
563 }
564
565 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
566 SDValue Chain = N->getOperand(0); // Get the chain.
567 SDValue Ptr = N->getOperand(1); // Get the pointer.
568 EVT VT = N->getValueType(0);
569 DebugLoc dl = N->getDebugLoc();
570
571 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
572 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
573 // The argument is passed as NumRegs registers of type RegVT.
574
575 SmallVector<SDValue, 8> Parts(NumRegs);
576 for (unsigned i = 0; i < NumRegs; ++i) {
577 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
578 N->getConstantOperandVal(3));
579 Chain = Parts[i].getValue(1);
580 }
581
582 // Handle endianness of the load.
583 if (TLI.isBigEndian())
584 std::reverse(Parts.begin(), Parts.end());
585
586 // Assemble the parts in the promoted type.
587 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
588 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
589 for (unsigned i = 1; i < NumRegs; ++i) {
590 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
591 // Shift it to the right position and "or" it in.
592 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
593 DAG.getConstant(i * RegVT.getSizeInBits(),
594 TLI.getPointerTy()));
595 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
596 }
597
598 // Modified the chain result - switch anything that used the old chain to
599 // use the new one.
600 ReplaceValueWith(SDValue(N, 1), Chain);
601
602 return Res;
603 }
604
605 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
606 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
607 return PromoteIntRes_Overflow(N);
608 }
609
610 //===----------------------------------------------------------------------===//
611 // Integer Operand Promotion
612 //===----------------------------------------------------------------------===//
613
614 /// PromoteIntegerOperand - This method is called when the specified operand of
615 /// the specified node is found to need promotion. At this point, all of the
616 /// result types of the node are known to be legal, but other operands of the
617 /// node may need promotion or expansion as well as the specified one.
618 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
619 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
620 SDValue Res = SDValue();
621
622 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
623 return false;
624
625 switch (N->getOpcode()) {
626 default:
627 #ifndef NDEBUG
628 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
629 N->dump(&DAG); dbgs() << "\n";
630 #endif
631 llvm_unreachable("Do not know how to promote this operator's operand!");
632
633 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
634 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
635 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
636 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
637 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
638 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
639 case ISD::CONVERT_RNDSAT:
640 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
641 case ISD::INSERT_VECTOR_ELT:
642 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
643 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
644 case ISD::SCALAR_TO_VECTOR:
645 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
646 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
647 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
648 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
649 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
650 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
651 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
652 OpNo); break;
653 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
654 case ISD::FP16_TO_FP32:
655 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
656 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
657
658 case ISD::SHL:
659 case ISD::SRA:
660 case ISD::SRL:
661 case ISD::ROTL:
662 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
663 }
664
665 // If the result is null, the sub-method took care of registering results etc.
666 if (!Res.getNode()) return false;
667
668 // If the result is N, the sub-method updated N in place. Tell the legalizer
669 // core about this.
670 if (Res.getNode() == N)
671 return true;
672
673 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
674 "Invalid operand expansion");
675
676 ReplaceValueWith(SDValue(N, 0), Res);
677 return false;
678 }
679
680 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
681 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
682 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
683 ISD::CondCode CCCode) {
684 // We have to insert explicit sign or zero extends. Note that we could
685 // insert sign extends for ALL conditions, but zero extend is cheaper on
686 // many machines (an AND instead of two shifts), so prefer it.
687 switch (CCCode) {
688 default: llvm_unreachable("Unknown integer comparison!");
689 case ISD::SETEQ:
690 case ISD::SETNE:
691 case ISD::SETUGE:
692 case ISD::SETUGT:
693 case ISD::SETULE:
694 case ISD::SETULT:
695 // ALL of these operations will work if we either sign or zero extend
696 // the operands (including the unsigned comparisons!). Zero extend is
697 // usually a simpler/cheaper operation, so prefer it.
698 NewLHS = ZExtPromotedInteger(NewLHS);
699 NewRHS = ZExtPromotedInteger(NewRHS);
700 break;
701 case ISD::SETGE:
702 case ISD::SETGT:
703 case ISD::SETLT:
704 case ISD::SETLE:
705 NewLHS = SExtPromotedInteger(NewLHS);
706 NewRHS = SExtPromotedInteger(NewRHS);
707 break;
708 }
709 }
710
711 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
712 SDValue Op = GetPromotedInteger(N->getOperand(0));
713 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
714 }
715
716 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
717 // This should only occur in unusual situations like bitcasting to an
718 // x86_fp80, so just turn it into a store+load
719 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
720 }
721
722 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
723 assert(OpNo == 2 && "Don't know how to promote this operand!");
724
725 SDValue LHS = N->getOperand(2);
726 SDValue RHS = N->getOperand(3);
727 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
728
729 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
730 // legal types.
731 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
732 N->getOperand(1), LHS, RHS, N->getOperand(4)),
733 0);
734 }
735
736 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
737 assert(OpNo == 1 && "only know how to promote condition");
738
739 // Promote all the way up to the canonical SetCC type.
740 EVT SVT = TLI.getSetCCResultType(MVT::Other);
741 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
742
743 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
744 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
745 N->getOperand(2)), 0);
746 }
747
748 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
749 // Since the result type is legal, the operands must promote to it.
750 EVT OVT = N->getOperand(0).getValueType();
751 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
752 SDValue Hi = GetPromotedInteger(N->getOperand(1));
753 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
754 DebugLoc dl = N->getDebugLoc();
755
756 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
757 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
758 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
759 }
760
761 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
762 // The vector type is legal but the element type is not. This implies
763 // that the vector is a power-of-two in length and that the element
764 // type does not have a strange size (eg: it is not i1).
765 EVT VecVT = N->getValueType(0);
766 unsigned NumElts = VecVT.getVectorNumElements();
767 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
768
769 // Promote the inserted value. The type does not need to match the
770 // vector element type. Check that any extra bits introduced will be
771 // truncated away.
772 assert(N->getOperand(0).getValueType().getSizeInBits() >=
773 N->getValueType(0).getVectorElementType().getSizeInBits() &&
774 "Type of inserted value narrower than vector element type!");
775
776 SmallVector<SDValue, 16> NewOps;
777 for (unsigned i = 0; i < NumElts; ++i)
778 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
779
780 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
781 }
782
783 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
784 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
785 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
786 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
787 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
788 "can only promote integer arguments");
789 SDValue InOp = GetPromotedInteger(N->getOperand(0));
790 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
791 N->getOperand(1), N->getOperand(2),
792 N->getOperand(3), N->getOperand(4), CvtCode);
793 }
794
795 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
796 unsigned OpNo) {
797 if (OpNo == 1) {
798 // Promote the inserted value. This is valid because the type does not
799 // have to match the vector element type.
800
801 // Check that any extra bits introduced will be truncated away.
802 assert(N->getOperand(1).getValueType().getSizeInBits() >=
803 N->getValueType(0).getVectorElementType().getSizeInBits() &&
804 "Type of inserted value narrower than vector element type!");
805 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
806 GetPromotedInteger(N->getOperand(1)),
807 N->getOperand(2)),
808 0);
809 }
810
811 assert(OpNo == 2 && "Different operand and result vector types?");
812
813 // Promote the index.
814 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
815 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
816 N->getOperand(1), Idx), 0);
817 }
818
819 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
820 SDValue NewOps[6];
821 DebugLoc dl = N->getDebugLoc();
822 NewOps[0] = N->getOperand(0);
823 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
824 SDValue Flag = GetPromotedInteger(N->getOperand(i));
825 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
826 }
827 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
828 }
829
830 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
831 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
832 // the operand in place.
833 return SDValue(DAG.UpdateNodeOperands(N,
834 GetPromotedInteger(N->getOperand(0))), 0);
835 }
836
837 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
838 assert(OpNo == 0 && "Only know how to promote condition");
839
840 // Promote all the way up to the canonical SetCC type.
841 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
842 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
843
844 return SDValue(DAG.UpdateNodeOperands(N, Cond,
845 N->getOperand(1), N->getOperand(2)), 0);
846 }
847
848 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
849 assert(OpNo == 0 && "Don't know how to promote this operand!");
850
851 SDValue LHS = N->getOperand(0);
852 SDValue RHS = N->getOperand(1);
853 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
854
855 // The CC (#4) and the possible return values (#2 and #3) have legal types.
856 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
857 N->getOperand(3), N->getOperand(4)), 0);
858 }
859
860 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
861 assert(OpNo == 0 && "Don't know how to promote this operand!");
862
863 SDValue LHS = N->getOperand(0);
864 SDValue RHS = N->getOperand(1);
865 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
866
867 // The CC (#2) is always legal.
868 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
869 }
870
871 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
872 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
873 ZExtPromotedInteger(N->getOperand(1))), 0);
874 }
875
876 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
877 SDValue Op = GetPromotedInteger(N->getOperand(0));
878 DebugLoc dl = N->getDebugLoc();
879 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
880 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
881 Op, DAG.getValueType(N->getOperand(0).getValueType()));
882 }
883
884 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
885 return SDValue(DAG.UpdateNodeOperands(N,
886 SExtPromotedInteger(N->getOperand(0))), 0);
887 }
888
889 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
890 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
891 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
892 unsigned Alignment = N->getAlignment();
893 bool isVolatile = N->isVolatile();
894 bool isNonTemporal = N->isNonTemporal();
895 DebugLoc dl = N->getDebugLoc();
896
897 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
898
899 // Truncate the value and store the result.
900 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
901 N->getMemoryVT(),
902 isVolatile, isNonTemporal, Alignment);
903 }
904
905 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
906 SDValue Op = GetPromotedInteger(N->getOperand(0));
907 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
908 }
909
910 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
911 return SDValue(DAG.UpdateNodeOperands(N,
912 ZExtPromotedInteger(N->getOperand(0))), 0);
913 }
914
915 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
916 DebugLoc dl = N->getDebugLoc();
917 SDValue Op = GetPromotedInteger(N->getOperand(0));
918 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
919 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
920 }
921
922
923 //===----------------------------------------------------------------------===//
924 // Integer Result Expansion
925 //===----------------------------------------------------------------------===//
926
927 /// ExpandIntegerResult - This method is called when the specified result of the
928 /// specified node is found to need expansion. At this point, the node may also
929 /// have invalid operands or may have other results that need promotion, we just
930 /// know that (at least) one result needs expansion.
931 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
932 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
933 SDValue Lo, Hi;
934 Lo = Hi = SDValue();
935
936 // See if the target wants to custom expand this node.
937 if (CustomLowerNode(N, N->getValueType(ResNo), true))
938 return;
939
940 switch (N->getOpcode()) {
941 default:
942 #ifndef NDEBUG
943 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
944 N->dump(&DAG); dbgs() << "\n";
945 #endif
946 llvm_unreachable("Do not know how to expand the result of this operator!");
947
948 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
949 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
950 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
951 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
952
953 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
954 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
955 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
956 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
957 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
958
959 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
960 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
961 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
962 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
963 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
964 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
965 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
966 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
967 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
968 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
969 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
970 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
971 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
972 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
973 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
974 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
975 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
976 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
977 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
978 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
979
980 case ISD::AND:
981 case ISD::OR:
982 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
983
984 case ISD::ADD:
985 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
986
987 case ISD::ADDC:
988 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
989
990 case ISD::ADDE:
991 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
992
993 case ISD::SHL:
994 case ISD::SRA:
995 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
996
997 case ISD::SADDO:
998 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
999 case ISD::UADDO:
1000 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1001 }
1002
1003 // If Lo/Hi is null, the sub-method took care of registering results etc.
1004 if (Lo.getNode())
1005 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1006 }
1007
1008 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1009 /// and the shift amount is a constant 'Amt'. Expand the operation.
1010 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1011 SDValue &Lo, SDValue &Hi) {
1012 DebugLoc dl = N->getDebugLoc();
1013 // Expand the incoming operand to be shifted, so that we have its parts
1014 SDValue InL, InH;
1015 GetExpandedInteger(N->getOperand(0), InL, InH);
1016
1017 EVT NVT = InL.getValueType();
1018 unsigned VTBits = N->getValueType(0).getSizeInBits();
1019 unsigned NVTBits = NVT.getSizeInBits();
1020 EVT ShTy = N->getOperand(1).getValueType();
1021
1022 if (N->getOpcode() == ISD::SHL) {
1023 if (Amt > VTBits) {
1024 Lo = Hi = DAG.getConstant(0, NVT);
1025 } else if (Amt > NVTBits) {
1026 Lo = DAG.getConstant(0, NVT);
1027 Hi = DAG.getNode(ISD::SHL, dl,
1028 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1029 } else if (Amt == NVTBits) {
1030 Lo = DAG.getConstant(0, NVT);
1031 Hi = InL;
1032 } else if (Amt == 1 &&
1033 TLI.isOperationLegalOrCustom(ISD::ADDC,
1034 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1035 // Emit this X << 1 as X+X.
1036 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1037 SDValue LoOps[2] = { InL, InL };
1038 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1039 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1040 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1041 } else {
1042 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1043 Hi = DAG.getNode(ISD::OR, dl, NVT,
1044 DAG.getNode(ISD::SHL, dl, NVT, InH,
1045 DAG.getConstant(Amt, ShTy)),
1046 DAG.getNode(ISD::SRL, dl, NVT, InL,
1047 DAG.getConstant(NVTBits-Amt, ShTy)));
1048 }
1049 return;
1050 }
1051
1052 if (N->getOpcode() == ISD::SRL) {
1053 if (Amt > VTBits) {
1054 Lo = DAG.getConstant(0, NVT);
1055 Hi = DAG.getConstant(0, NVT);
1056 } else if (Amt > NVTBits) {
1057 Lo = DAG.getNode(ISD::SRL, dl,
1058 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1059 Hi = DAG.getConstant(0, NVT);
1060 } else if (Amt == NVTBits) {
1061 Lo = InH;
1062 Hi = DAG.getConstant(0, NVT);
1063 } else {
1064 Lo = DAG.getNode(ISD::OR, dl, NVT,
1065 DAG.getNode(ISD::SRL, dl, NVT, InL,
1066 DAG.getConstant(Amt, ShTy)),
1067 DAG.getNode(ISD::SHL, dl, NVT, InH,
1068 DAG.getConstant(NVTBits-Amt, ShTy)));
1069 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1070 }
1071 return;
1072 }
1073
1074 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1075 if (Amt > VTBits) {
1076 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1077 DAG.getConstant(NVTBits-1, ShTy));
1078 } else if (Amt > NVTBits) {
1079 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1080 DAG.getConstant(Amt-NVTBits, ShTy));
1081 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1082 DAG.getConstant(NVTBits-1, ShTy));
1083 } else if (Amt == NVTBits) {
1084 Lo = InH;
1085 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1086 DAG.getConstant(NVTBits-1, ShTy));
1087 } else {
1088 Lo = DAG.getNode(ISD::OR, dl, NVT,
1089 DAG.getNode(ISD::SRL, dl, NVT, InL,
1090 DAG.getConstant(Amt, ShTy)),
1091 DAG.getNode(ISD::SHL, dl, NVT, InH,
1092 DAG.getConstant(NVTBits-Amt, ShTy)));
1093 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1094 }
1095 }
1096
1097 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1098 /// this shift based on knowledge of the high bit of the shift amount. If we
1099 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1100 /// shift amount.
1101 bool DAGTypeLegalizer::
1102 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1103 SDValue Amt = N->getOperand(1);
1104 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1105 EVT ShTy = Amt.getValueType();
1106 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1107 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1108 assert(isPowerOf2_32(NVTBits) &&
1109 "Expanded integer type size not a power of two!");
1110 DebugLoc dl = N->getDebugLoc();
1111
1112 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1113 APInt KnownZero, KnownOne;
1114 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1115
1116 // If we don't know anything about the high bits, exit.
1117 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1118 return false;
1119
1120 // Get the incoming operand to be shifted.
1121 SDValue InL, InH;
1122 GetExpandedInteger(N->getOperand(0), InL, InH);
1123
1124 // If we know that any of the high bits of the shift amount are one, then we
1125 // can do this as a couple of simple shifts.
1126 if (KnownOne.intersects(HighBitMask)) {
1127 // Mask out the high bit, which we know is set.
1128 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1129 DAG.getConstant(~HighBitMask, ShTy));
1130
1131 switch (N->getOpcode()) {
1132 default: llvm_unreachable("Unknown shift");
1133 case ISD::SHL:
1134 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1135 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1136 return true;
1137 case ISD::SRL:
1138 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1139 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1140 return true;
1141 case ISD::SRA:
1142 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1143 DAG.getConstant(NVTBits-1, ShTy));
1144 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1145 return true;
1146 }
1147 }
1148
1149 #if 0
1150 // FIXME: This code is broken for shifts with a zero amount!
1151 // If we know that all of the high bits of the shift amount are zero, then we
1152 // can do this as a couple of simple shifts.
1153 if ((KnownZero & HighBitMask) == HighBitMask) {
1154 // Compute 32-amt.
1155 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1156 DAG.getConstant(NVTBits, ShTy),
1157 Amt);
1158 unsigned Op1, Op2;
1159 switch (N->getOpcode()) {
1160 default: llvm_unreachable("Unknown shift");
1161 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1162 case ISD::SRL:
1163 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1164 }
1165
1166 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1167 Hi = DAG.getNode(ISD::OR, NVT,
1168 DAG.getNode(Op1, NVT, InH, Amt),
1169 DAG.getNode(Op2, NVT, InL, Amt2));
1170 return true;
1171 }
1172 #endif
1173
1174 return false;
1175 }
1176
1177 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1178 /// of any size.
1179 bool DAGTypeLegalizer::
1180 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1181 SDValue Amt = N->getOperand(1);
1182 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1183 EVT ShTy = Amt.getValueType();
1184 unsigned NVTBits = NVT.getSizeInBits();
1185 assert(isPowerOf2_32(NVTBits) &&
1186 "Expanded integer type size not a power of two!");
1187 DebugLoc dl = N->getDebugLoc();
1188
1189 // Get the incoming operand to be shifted.
1190 SDValue InL, InH;
1191 GetExpandedInteger(N->getOperand(0), InL, InH);
1192
1193 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1194 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1195 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1196 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1197 Amt, NVBitsNode, ISD::SETULT);
1198
1199 SDValue LoS, HiS, LoL, HiL;
1200 switch (N->getOpcode()) {
1201 default: llvm_unreachable("Unknown shift");
1202 case ISD::SHL:
1203 // Short: ShAmt < NVTBits
1204 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1205 HiS = DAG.getNode(ISD::OR, dl, NVT,
1206 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1207 // FIXME: If Amt is zero, the following shift generates an undefined result
1208 // on some architectures.
1209 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1210
1211 // Long: ShAmt >= NVTBits
1212 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1213 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1214
1215 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1216 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1217 return true;
1218 case ISD::SRL:
1219 // Short: ShAmt < NVTBits
1220 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1221 LoS = DAG.getNode(ISD::OR, dl, NVT,
1222 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1223 // FIXME: If Amt is zero, the following shift generates an undefined result
1224 // on some architectures.
1225 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1226
1227 // Long: ShAmt >= NVTBits
1228 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1229 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1230
1231 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1232 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1233 return true;
1234 case ISD::SRA:
1235 // Short: ShAmt < NVTBits
1236 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1237 LoS = DAG.getNode(ISD::OR, dl, NVT,
1238 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1239 // FIXME: If Amt is zero, the following shift generates an undefined result
1240 // on some architectures.
1241 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1242
1243 // Long: ShAmt >= NVTBits
1244 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1245 DAG.getConstant(NVTBits-1, ShTy));
1246 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1247
1248 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1249 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1250 return true;
1251 }
1252
1253 return false;
1254 }
1255
1256 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1257 SDValue &Lo, SDValue &Hi) {
1258 DebugLoc dl = N->getDebugLoc();
1259 // Expand the subcomponents.
1260 SDValue LHSL, LHSH, RHSL, RHSH;
1261 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1262 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1263
1264 EVT NVT = LHSL.getValueType();
1265 SDValue LoOps[2] = { LHSL, RHSL };
1266 SDValue HiOps[3] = { LHSH, RHSH };
1267
1268 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1269 // them. TODO: Teach operation legalization how to expand unsupported
1270 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1271 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1272 // generate a value of this type in the expanded code sequence.
1273 bool hasCarry =
1274 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1275 ISD::ADDC : ISD::SUBC,
1276 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1277
1278 if (hasCarry) {
1279 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1280 if (N->getOpcode() == ISD::ADD) {
1281 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1282 HiOps[2] = Lo.getValue(1);
1283 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1284 } else {
1285 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1286 HiOps[2] = Lo.getValue(1);
1287 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1288 }
1289 } else {
1290 if (N->getOpcode() == ISD::ADD) {
1291 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1292 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1293 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1294 ISD::SETULT);
1295 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1296 DAG.getConstant(1, NVT),
1297 DAG.getConstant(0, NVT));
1298 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1299 ISD::SETULT);
1300 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1301 DAG.getConstant(1, NVT), Carry1);
1302 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1303 } else {
1304 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1305 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1306 SDValue Cmp =
1307 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1308 LoOps[0], LoOps[1], ISD::SETULT);
1309 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1310 DAG.getConstant(1, NVT),
1311 DAG.getConstant(0, NVT));
1312 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1313 }
1314 }
1315 }
1316
1317 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1318 SDValue &Lo, SDValue &Hi) {
1319 // Expand the subcomponents.
1320 SDValue LHSL, LHSH, RHSL, RHSH;
1321 DebugLoc dl = N->getDebugLoc();
1322 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1323 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1324 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1325 SDValue LoOps[2] = { LHSL, RHSL };
1326 SDValue HiOps[3] = { LHSH, RHSH };
1327
1328 if (N->getOpcode() == ISD::ADDC) {
1329 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1330 HiOps[2] = Lo.getValue(1);
1331 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1332 } else {
1333 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1334 HiOps[2] = Lo.getValue(1);
1335 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1336 }
1337
1338 // Legalized the flag result - switch anything that used the old flag to
1339 // use the new one.
1340 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1341 }
1342
1343 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1344 SDValue &Lo, SDValue &Hi) {
1345 // Expand the subcomponents.
1346 SDValue LHSL, LHSH, RHSL, RHSH;
1347 DebugLoc dl = N->getDebugLoc();
1348 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1349 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1350 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1351 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1352 SDValue HiOps[3] = { LHSH, RHSH };
1353
1354 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1355 HiOps[2] = Lo.getValue(1);
1356 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1357
1358 // Legalized the flag result - switch anything that used the old flag to
1359 // use the new one.
1360 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1361 }
1362
1363 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1364 SDValue &Lo, SDValue &Hi) {
1365 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1366 DebugLoc dl = N->getDebugLoc();
1367 SDValue Op = N->getOperand(0);
1368 if (Op.getValueType().bitsLE(NVT)) {
1369 // The low part is any extension of the input (which degenerates to a copy).
1370 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1371 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1372 } else {
1373 // For example, extension of an i48 to an i64. The operand type necessarily
1374 // promotes to the result type, so will end up being expanded too.
1375 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1376 "Only know how to promote this result!");
1377 SDValue Res = GetPromotedInteger(Op);
1378 assert(Res.getValueType() == N->getValueType(0) &&
1379 "Operand over promoted?");
1380 // Split the promoted operand. This will simplify when it is expanded.
1381 SplitInteger(Res, Lo, Hi);
1382 }
1383 }
1384
1385 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1386 SDValue &Lo, SDValue &Hi) {
1387 DebugLoc dl = N->getDebugLoc();
1388 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1389 EVT NVT = Lo.getValueType();
1390 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1391 unsigned NVTBits = NVT.getSizeInBits();
1392 unsigned EVTBits = EVT.getSizeInBits();
1393
1394 if (NVTBits < EVTBits) {
1395 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1396 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1397 EVTBits - NVTBits)));
1398 } else {
1399 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1400 // The high part replicates the sign bit of Lo, make it explicit.
1401 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1402 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1403 }
1404 }
1405
1406 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1407 SDValue &Lo, SDValue &Hi) {
1408 DebugLoc dl = N->getDebugLoc();
1409 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1410 EVT NVT = Lo.getValueType();
1411 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1412 unsigned NVTBits = NVT.getSizeInBits();
1413 unsigned EVTBits = EVT.getSizeInBits();
1414
1415 if (NVTBits < EVTBits) {
1416 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1417 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1418 EVTBits - NVTBits)));
1419 } else {
1420 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1421 // The high part must be zero, make it explicit.
1422 Hi = DAG.getConstant(0, NVT);
1423 }
1424 }
1425
1426 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1427 SDValue &Lo, SDValue &Hi) {
1428 DebugLoc dl = N->getDebugLoc();
1429 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1430 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1431 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1432 }
1433
1434 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1435 SDValue &Lo, SDValue &Hi) {
1436 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1437 unsigned NBitWidth = NVT.getSizeInBits();
1438 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1439 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1440 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1441 }
1442
1443 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1444 SDValue &Lo, SDValue &Hi) {
1445 DebugLoc dl = N->getDebugLoc();
1446 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1447 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1448 EVT NVT = Lo.getValueType();
1449
1450 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1451 DAG.getConstant(0, NVT), ISD::SETNE);
1452
1453 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1454 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1455
1456 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1457 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1458 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1459 Hi = DAG.getConstant(0, NVT);
1460 }
1461
1462 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1463 SDValue &Lo, SDValue &Hi) {
1464 DebugLoc dl = N->getDebugLoc();
1465 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1466 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1467 EVT NVT = Lo.getValueType();
1468 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1469 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1470 Hi = DAG.getConstant(0, NVT);
1471 }
1472
1473 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1474 SDValue &Lo, SDValue &Hi) {
1475 DebugLoc dl = N->getDebugLoc();
1476 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1477 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1478 EVT NVT = Lo.getValueType();
1479
1480 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1481 DAG.getConstant(0, NVT), ISD::SETNE);
1482
1483 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1484 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1485
1486 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1487 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1488 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1489 Hi = DAG.getConstant(0, NVT);
1490 }
1491
1492 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1493 SDValue &Hi) {
1494 DebugLoc dl = N->getDebugLoc();
1495 EVT VT = N->getValueType(0);
1496 SDValue Op = N->getOperand(0);
1497 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1498 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1499 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1500 }
1501
1502 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1503 SDValue &Hi) {
1504 DebugLoc dl = N->getDebugLoc();
1505 EVT VT = N->getValueType(0);
1506 SDValue Op = N->getOperand(0);
1507 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1508 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1509 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1510 }
1511
1512 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1513 SDValue &Lo, SDValue &Hi) {
1514 if (ISD::isNormalLoad(N)) {
1515 ExpandRes_NormalLoad(N, Lo, Hi);
1516 return;
1517 }
1518
1519 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1520
1521 EVT VT = N->getValueType(0);
1522 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1523 SDValue Ch = N->getChain();
1524 SDValue Ptr = N->getBasePtr();
1525 ISD::LoadExtType ExtType = N->getExtensionType();
1526 unsigned Alignment = N->getAlignment();
1527 bool isVolatile = N->isVolatile();
1528 bool isNonTemporal = N->isNonTemporal();
1529 DebugLoc dl = N->getDebugLoc();
1530
1531 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1532
1533 if (N->getMemoryVT().bitsLE(NVT)) {
1534 EVT MemVT = N->getMemoryVT();
1535
1536 Lo = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(),
1537 MemVT, isVolatile, isNonTemporal, Alignment);
1538
1539 // Remember the chain.
1540 Ch = Lo.getValue(1);
1541
1542 if (ExtType == ISD::SEXTLOAD) {
1543 // The high part is obtained by SRA'ing all but one of the bits of the
1544 // lo part.
1545 unsigned LoSize = Lo.getValueType().getSizeInBits();
1546 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1547 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1548 } else if (ExtType == ISD::ZEXTLOAD) {
1549 // The high part is just a zero.
1550 Hi = DAG.getConstant(0, NVT);
1551 } else {
1552 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1553 // The high part is undefined.
1554 Hi = DAG.getUNDEF(NVT);
1555 }
1556 } else if (TLI.isLittleEndian()) {
1557 // Little-endian - low bits are at low addresses.
1558 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1559 isVolatile, isNonTemporal, Alignment);
1560
1561 unsigned ExcessBits =
1562 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1563 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1564
1565 // Increment the pointer to the other half.
1566 unsigned IncrementSize = NVT.getSizeInBits()/8;
1567 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1568 DAG.getIntPtrConstant(IncrementSize));
1569 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr,
1570 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1571 isVolatile, isNonTemporal,
1572 MinAlign(Alignment, IncrementSize));
1573
1574 // Build a factor node to remember that this load is independent of the
1575 // other one.
1576 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1577 Hi.getValue(1));
1578 } else {
1579 // Big-endian - high bits are at low addresses. Favor aligned loads at
1580 // the cost of some bit-fiddling.
1581 EVT MemVT = N->getMemoryVT();
1582 unsigned EBytes = MemVT.getStoreSize();
1583 unsigned IncrementSize = NVT.getSizeInBits()/8;
1584 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1585
1586 // Load both the high bits and maybe some of the low bits.
1587 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(),
1588 EVT::getIntegerVT(*DAG.getContext(),
1589 MemVT.getSizeInBits() - ExcessBits),
1590 isVolatile, isNonTemporal, Alignment);
1591
1592 // Increment the pointer to the other half.
1593 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1594 DAG.getIntPtrConstant(IncrementSize));
1595 // Load the rest of the low bits.
1596 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, dl, Ch, Ptr,
1597 N->getPointerInfo().getWithOffset(IncrementSize),
1598 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1599 isVolatile, isNonTemporal,
1600 MinAlign(Alignment, IncrementSize));
1601
1602 // Build a factor node to remember that this load is independent of the
1603 // other one.
1604 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1605 Hi.getValue(1));
1606
1607 if (ExcessBits < NVT.getSizeInBits()) {
1608 // Transfer low bits from the bottom of Hi to the top of Lo.
1609 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1610 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1611 DAG.getConstant(ExcessBits,
1612 TLI.getPointerTy())));
1613 // Move high bits to the right position in Hi.
1614 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1615 NVT, Hi,
1616 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1617 TLI.getPointerTy()));
1618 }
1619 }
1620
1621 // Legalized the chain result - switch anything that used the old chain to
1622 // use the new one.
1623 ReplaceValueWith(SDValue(N, 1), Ch);
1624 }
1625
1626 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1627 SDValue &Lo, SDValue &Hi) {
1628 DebugLoc dl = N->getDebugLoc();
1629 SDValue LL, LH, RL, RH;
1630 GetExpandedInteger(N->getOperand(0), LL, LH);
1631 GetExpandedInteger(N->getOperand(1), RL, RH);
1632 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1633 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1634 }
1635
1636 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1637 SDValue &Lo, SDValue &Hi) {
1638 EVT VT = N->getValueType(0);
1639 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1640 DebugLoc dl = N->getDebugLoc();
1641
1642 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1643 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1644 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1645 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1646 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1647 SDValue LL, LH, RL, RH;
1648 GetExpandedInteger(N->getOperand(0), LL, LH);
1649 GetExpandedInteger(N->getOperand(1), RL, RH);
1650 unsigned OuterBitSize = VT.getSizeInBits();
1651 unsigned InnerBitSize = NVT.getSizeInBits();
1652 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1653 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1654
1655 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1656 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1657 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1658 // The inputs are both zero-extended.
1659 if (HasUMUL_LOHI) {
1660 // We can emit a umul_lohi.
1661 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1662 Hi = SDValue(Lo.getNode(), 1);
1663 return;
1664 }
1665 if (HasMULHU) {
1666 // We can emit a mulhu+mul.
1667 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1668 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1669 return;
1670 }
1671 }
1672 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1673 // The input values are both sign-extended.
1674 if (HasSMUL_LOHI) {
1675 // We can emit a smul_lohi.
1676 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1677 Hi = SDValue(Lo.getNode(), 1);
1678 return;
1679 }
1680 if (HasMULHS) {
1681 // We can emit a mulhs+mul.
1682 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1683 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1684 return;
1685 }
1686 }
1687 if (HasUMUL_LOHI) {
1688 // Lo,Hi = umul LHS, RHS.
1689 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1690 DAG.getVTList(NVT, NVT), LL, RL);
1691 Lo = UMulLOHI;
1692 Hi = UMulLOHI.getValue(1);
1693 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1694 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1695 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1696 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1697 return;
1698 }
1699 if (HasMULHU) {
1700 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1701 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1702 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1703 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1704 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1705 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1706 return;
1707 }
1708 }
1709
1710 // If nothing else, we can make a libcall.
1711 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1712 if (VT == MVT::i16)
1713 LC = RTLIB::MUL_I16;
1714 else if (VT == MVT::i32)
1715 LC = RTLIB::MUL_I32;
1716 else if (VT == MVT::i64)
1717 LC = RTLIB::MUL_I64;
1718 else if (VT == MVT::i128)
1719 LC = RTLIB::MUL_I128;
1720 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1721
1722 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1723 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1724 }
1725
1726 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1727 SDValue &Lo, SDValue &Hi) {
1728 SDValue LHS = Node->getOperand(0);
1729 SDValue RHS = Node->getOperand(1);
1730 DebugLoc dl = Node->getDebugLoc();
1731
1732 // Expand the result by simply replacing it with the equivalent
1733 // non-overflow-checking operation.
1734 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1735 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1736 LHS, RHS);
1737 SplitInteger(Sum, Lo, Hi);
1738
1739 // Compute the overflow.
1740 //
1741 // LHSSign -> LHS >= 0
1742 // RHSSign -> RHS >= 0
1743 // SumSign -> Sum >= 0
1744 //
1745 // Add:
1746 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
1747 // Sub:
1748 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
1749 //
1750 EVT OType = Node->getValueType(1);
1751 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
1752
1753 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
1754 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
1755 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
1756 Node->getOpcode() == ISD::SADDO ?
1757 ISD::SETEQ : ISD::SETNE);
1758
1759 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
1760 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
1761
1762 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
1763
1764 // Use the calculated overflow everywhere.
1765 ReplaceValueWith(SDValue(Node, 1), Cmp);
1766 }
1767
1768 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1769 SDValue &Lo, SDValue &Hi) {
1770 EVT VT = N->getValueType(0);
1771 DebugLoc dl = N->getDebugLoc();
1772
1773 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1774 if (VT == MVT::i16)
1775 LC = RTLIB::SDIV_I16;
1776 else if (VT == MVT::i32)
1777 LC = RTLIB::SDIV_I32;
1778 else if (VT == MVT::i64)
1779 LC = RTLIB::SDIV_I64;
1780 else if (VT == MVT::i128)
1781 LC = RTLIB::SDIV_I128;
1782 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1783
1784 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1785 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1786 }
1787
1788 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1789 SDValue &Lo, SDValue &Hi) {
1790 EVT VT = N->getValueType(0);
1791 DebugLoc dl = N->getDebugLoc();
1792
1793 // If we can emit an efficient shift operation, do so now. Check to see if
1794 // the RHS is a constant.
1795 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1796 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1797
1798 // If we can determine that the high bit of the shift is zero or one, even if
1799 // the low bits are variable, emit this shift in an optimized form.
1800 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1801 return;
1802
1803 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1804 unsigned PartsOpc;
1805 if (N->getOpcode() == ISD::SHL) {
1806 PartsOpc = ISD::SHL_PARTS;
1807 } else if (N->getOpcode() == ISD::SRL) {
1808 PartsOpc = ISD::SRL_PARTS;
1809 } else {
1810 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1811 PartsOpc = ISD::SRA_PARTS;
1812 }
1813
1814 // Next check to see if the target supports this SHL_PARTS operation or if it
1815 // will custom expand it.
1816 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1817 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1818 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1819 Action == TargetLowering::Custom) {
1820 // Expand the subcomponents.
1821 SDValue LHSL, LHSH;
1822 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1823
1824 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1825 EVT VT = LHSL.getValueType();
1826 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1827 Hi = Lo.getValue(1);
1828 return;
1829 }
1830
1831 // Otherwise, emit a libcall.
1832 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1833 bool isSigned;
1834 if (N->getOpcode() == ISD::SHL) {
1835 isSigned = false; /*sign irrelevant*/
1836 if (VT == MVT::i16)
1837 LC = RTLIB::SHL_I16;
1838 else if (VT == MVT::i32)
1839 LC = RTLIB::SHL_I32;
1840 else if (VT == MVT::i64)
1841 LC = RTLIB::SHL_I64;
1842 else if (VT == MVT::i128)
1843 LC = RTLIB::SHL_I128;
1844 } else if (N->getOpcode() == ISD::SRL) {
1845 isSigned = false;
1846 if (VT == MVT::i16)
1847 LC = RTLIB::SRL_I16;
1848 else if (VT == MVT::i32)
1849 LC = RTLIB::SRL_I32;
1850 else if (VT == MVT::i64)
1851 LC = RTLIB::SRL_I64;
1852 else if (VT == MVT::i128)
1853 LC = RTLIB::SRL_I128;
1854 } else {
1855 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1856 isSigned = true;
1857 if (VT == MVT::i16)
1858 LC = RTLIB::SRA_I16;
1859 else if (VT == MVT::i32)
1860 LC = RTLIB::SRA_I32;
1861 else if (VT == MVT::i64)
1862 LC = RTLIB::SRA_I64;
1863 else if (VT == MVT::i128)
1864 LC = RTLIB::SRA_I128;
1865 }
1866
1867 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1868 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1869 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1870 return;
1871 }
1872
1873 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1874 llvm_unreachable("Unsupported shift!");
1875 }
1876
1877 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1878 SDValue &Lo, SDValue &Hi) {
1879 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1880 DebugLoc dl = N->getDebugLoc();
1881 SDValue Op = N->getOperand(0);
1882 if (Op.getValueType().bitsLE(NVT)) {
1883 // The low part is sign extension of the input (degenerates to a copy).
1884 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1885 // The high part is obtained by SRA'ing all but one of the bits of low part.
1886 unsigned LoSize = NVT.getSizeInBits();
1887 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1888 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1889 } else {
1890 // For example, extension of an i48 to an i64. The operand type necessarily
1891 // promotes to the result type, so will end up being expanded too.
1892 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1893 "Only know how to promote this result!");
1894 SDValue Res = GetPromotedInteger(Op);
1895 assert(Res.getValueType() == N->getValueType(0) &&
1896 "Operand over promoted?");
1897 // Split the promoted operand. This will simplify when it is expanded.
1898 SplitInteger(Res, Lo, Hi);
1899 unsigned ExcessBits =
1900 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1901 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1902 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1903 ExcessBits)));
1904 }
1905 }
1906
1907 void DAGTypeLegalizer::
1908 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1909 DebugLoc dl = N->getDebugLoc();
1910 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1911 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1912
1913 if (EVT.bitsLE(Lo.getValueType())) {
1914 // sext_inreg the low part if needed.
1915 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1916 N->getOperand(1));
1917
1918 // The high part gets the sign extension from the lo-part. This handles
1919 // things like sextinreg V:i64 from i8.
1920 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1921 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1922 TLI.getPointerTy()));
1923 } else {
1924 // For example, extension of an i48 to an i64. Leave the low part alone,
1925 // sext_inreg the high part.
1926 unsigned ExcessBits =
1927 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1928 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1929 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1930 ExcessBits)));
1931 }
1932 }
1933
1934 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1935 SDValue &Lo, SDValue &Hi) {
1936 EVT VT = N->getValueType(0);
1937 DebugLoc dl = N->getDebugLoc();
1938
1939 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1940 if (VT == MVT::i16)
1941 LC = RTLIB::SREM_I16;
1942 else if (VT == MVT::i32)
1943 LC = RTLIB::SREM_I32;
1944 else if (VT == MVT::i64)
1945 LC = RTLIB::SREM_I64;
1946 else if (VT == MVT::i128)
1947 LC = RTLIB::SREM_I128;
1948 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1949
1950 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1951 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1952 }
1953
1954 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1955 SDValue &Lo, SDValue &Hi) {
1956 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1957 DebugLoc dl = N->getDebugLoc();
1958 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1959 Hi = DAG.getNode(ISD::SRL, dl,
1960 N->getOperand(0).getValueType(), N->getOperand(0),
1961 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1962 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1963 }
1964
1965 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
1966 SDValue &Lo, SDValue &Hi) {
1967 SDValue LHS = N->getOperand(0);
1968 SDValue RHS = N->getOperand(1);
1969 DebugLoc dl = N->getDebugLoc();
1970
1971 // Expand the result by simply replacing it with the equivalent
1972 // non-overflow-checking operation.
1973 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
1974 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1975 LHS, RHS);
1976 SplitInteger(Sum, Lo, Hi);
1977
1978 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
1979 // overflows iff a - b > a.
1980 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
1981 N->getOpcode () == ISD::UADDO ?
1982 ISD::SETULT : ISD::SETUGT);
1983
1984 // Use the calculated overflow everywhere.
1985 ReplaceValueWith(SDValue(N, 1), Ofl);
1986 }
1987
1988 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1989 SDValue &Lo, SDValue &Hi) {
1990 EVT VT = N->getValueType(0);
1991 DebugLoc dl = N->getDebugLoc();
1992
1993 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1994 if (VT == MVT::i16)
1995 LC = RTLIB::UDIV_I16;
1996 else if (VT == MVT::i32)
1997 LC = RTLIB::UDIV_I32;
1998 else if (VT == MVT::i64)
1999 LC = RTLIB::UDIV_I64;
2000 else if (VT == MVT::i128)
2001 LC = RTLIB::UDIV_I128;
2002 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2003
2004 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2005 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2006 }
2007
2008 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2009 SDValue &Lo, SDValue &Hi) {
2010 EVT VT = N->getValueType(0);
2011 DebugLoc dl = N->getDebugLoc();
2012
2013 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2014 if (VT == MVT::i16)
2015 LC = RTLIB::UREM_I16;
2016 else if (VT == MVT::i32)
2017 LC = RTLIB::UREM_I32;
2018 else if (VT == MVT::i64)
2019 LC = RTLIB::UREM_I64;
2020 else if (VT == MVT::i128)
2021 LC = RTLIB::UREM_I128;
2022 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2023
2024 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2025 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2026 }
2027
2028 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2029 SDValue &Lo, SDValue &Hi) {
2030 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2031 DebugLoc dl = N->getDebugLoc();
2032 SDValue Op = N->getOperand(0);
2033 if (Op.getValueType().bitsLE(NVT)) {
2034 // The low part is zero extension of the input (degenerates to a copy).
2035 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2036 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2037 } else {
2038 // For example, extension of an i48 to an i64. The operand type necessarily
2039 // promotes to the result type, so will end up being expanded too.
2040 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
2041 "Only know how to promote this result!");
2042 SDValue Res = GetPromotedInteger(Op);
2043 assert(Res.getValueType() == N->getValueType(0) &&
2044 "Operand over promoted?");
2045 // Split the promoted operand. This will simplify when it is expanded.
2046 SplitInteger(Res, Lo, Hi);
2047 unsigned ExcessBits =
2048 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2049 Hi = DAG.getZeroExtendInReg(Hi, dl,
2050 EVT::getIntegerVT(*DAG.getContext(),
2051 ExcessBits));
2052 }
2053 }
2054
2055
2056 //===----------------------------------------------------------------------===//
2057 // Integer Operand Expansion
2058 //===----------------------------------------------------------------------===//
2059
2060 /// ExpandIntegerOperand - This method is called when the specified operand of
2061 /// the specified node is found to need expansion. At this point, all of the
2062 /// result types of the node are known to be legal, but other operands of the
2063 /// node may need promotion or expansion as well as the specified one.
2064 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2065 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2066 SDValue Res = SDValue();
2067
2068 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2069 return false;
2070
2071 switch (N->getOpcode()) {
2072 default:
2073 #ifndef NDEBUG
2074 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2075 N->dump(&DAG); dbgs() << "\n";
2076 #endif
2077 llvm_unreachable("Do not know how to expand this operator's operand!");
2078
2079 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
2080 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2081 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2082 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2083 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2084 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2085 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2086 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2087 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2088 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2089 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2090 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2091
2092 case ISD::SHL:
2093 case ISD::SRA:
2094 case ISD::SRL:
2095 case ISD::ROTL:
2096 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2097 case ISD::RETURNADDR:
2098 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2099 }
2100
2101 // If the result is null, the sub-method took care of registering results etc.
2102 if (!Res.getNode()) return false;
2103
2104 // If the result is N, the sub-method updated N in place. Tell the legalizer
2105 // core about this.
2106 if (Res.getNode() == N)
2107 return true;
2108
2109 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2110 "Invalid operand expansion");
2111
2112 ReplaceValueWith(SDValue(N, 0), Res);
2113 return false;
2114 }
2115
2116 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2117 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2118 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2119 SDValue &NewRHS,
2120 ISD::CondCode &CCCode,
2121 DebugLoc dl) {
2122 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2123 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2124 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2125
2126 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2127 if (RHSLo == RHSHi) {
2128 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2129 if (RHSCST->isAllOnesValue()) {
2130 // Equality comparison to -1.
2131 NewLHS = DAG.getNode(ISD::AND, dl,
2132 LHSLo.getValueType(), LHSLo, LHSHi);
2133 NewRHS = RHSLo;
2134 return;
2135 }
2136 }
2137 }
2138
2139 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2140 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2141 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2142 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2143 return;
2144 }
2145
2146 // If this is a comparison of the sign bit, just look at the top part.
2147 // X > -1, x < 0
2148 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2149 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2150 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2151 NewLHS = LHSHi;
2152 NewRHS = RHSHi;
2153 return;
2154 }
2155
2156 // FIXME: This generated code sucks.
2157 ISD::CondCode LowCC;
2158 switch (CCCode) {
2159 default: llvm_unreachable("Unknown integer setcc!");
2160 case ISD::SETLT:
2161 case ISD::SETULT: LowCC = ISD::SETULT; break;
2162 case ISD::SETGT:
2163 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2164 case ISD::SETLE:
2165 case ISD::SETULE: LowCC = ISD::SETULE; break;
2166 case ISD::SETGE:
2167 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2168 }
2169
2170 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2171 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2172 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2173
2174 // NOTE: on targets without efficient SELECT of bools, we can always use
2175 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2176 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2177 SDValue Tmp1, Tmp2;
2178 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2179 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2180 if (!Tmp1.getNode())
2181 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2182 LHSLo, RHSLo, LowCC);
2183 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2184 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2185 if (!Tmp2.getNode())
2186 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2187 TLI.getSetCCResultType(LHSHi.getValueType()),
2188 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2189
2190 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2191 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2192 if ((Tmp1C && Tmp1C->isNullValue()) ||
2193 (Tmp2C && Tmp2C->isNullValue() &&
2194 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2195 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2196 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2197 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2198 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2199 // low part is known false, returns high part.
2200 // For LE / GE, if high part is known false, ignore the low part.
2201 // For LT / GT, if high part is known true, ignore the low part.
2202 NewLHS = Tmp2;
2203 NewRHS = SDValue();
2204 return;
2205 }
2206
2207 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2208 LHSHi, RHSHi, ISD::SETEQ, false,
2209 DagCombineInfo, dl);
2210 if (!NewLHS.getNode())
2211 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2212 LHSHi, RHSHi, ISD::SETEQ);
2213 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2214 NewLHS, Tmp1, Tmp2);
2215 NewRHS = SDValue();
2216 }
2217
2218 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2219 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2220 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2221 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2222
2223 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2224 // against zero to select between true and false values.
2225 if (NewRHS.getNode() == 0) {
2226 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2227 CCCode = ISD::SETNE;
2228 }
2229
2230 // Update N to have the operands specified.
2231 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2232 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2233 N->getOperand(4)), 0);
2234 }
2235
2236 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2237 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2238 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2239 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2240
2241 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2242 // against zero to select between true and false values.
2243 if (NewRHS.getNode() == 0) {
2244 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2245 CCCode = ISD::SETNE;
2246 }
2247
2248 // Update N to have the operands specified.
2249 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2250 N->getOperand(2), N->getOperand(3),
2251 DAG.getCondCode(CCCode)), 0);
2252 }
2253
2254 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2255 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2256 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2257 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2258
2259 // If ExpandSetCCOperands returned a scalar, use it.
2260 if (NewRHS.getNode() == 0) {
2261 assert(NewLHS.getValueType() == N->getValueType(0) &&
2262 "Unexpected setcc expansion!");
2263 return NewLHS;
2264 }
2265
2266 // Otherwise, update N to have the operands specified.
2267 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2268 DAG.getCondCode(CCCode)), 0);
2269 }
2270
2271 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2272 // The value being shifted is legal, but the shift amount is too big.
2273 // It follows that either the result of the shift is undefined, or the
2274 // upper half of the shift amount is zero. Just use the lower half.
2275 SDValue Lo, Hi;
2276 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2277 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2278 }
2279
2280 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2281 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2282 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2283 // constant to valid type.
2284 SDValue Lo, Hi;
2285 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2286 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2287 }
2288
2289 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2290 SDValue Op = N->getOperand(0);
2291 EVT DstVT = N->getValueType(0);
2292 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2293 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2294 "Don't know how to expand this SINT_TO_FP!");
2295 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2296 }
2297
2298 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2299 if (ISD::isNormalStore(N))
2300 return ExpandOp_NormalStore(N, OpNo);
2301
2302 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2303 assert(OpNo == 1 && "Can only expand the stored value so far");
2304
2305 EVT VT = N->getOperand(1).getValueType();
2306 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2307 SDValue Ch = N->getChain();
2308 SDValue Ptr = N->getBasePtr();
2309 unsigned Alignment = N->getAlignment();
2310 bool isVolatile = N->isVolatile();
2311 bool isNonTemporal = N->isNonTemporal();
2312 DebugLoc dl = N->getDebugLoc();
2313 SDValue Lo, Hi;
2314
2315 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2316
2317 if (N->getMemoryVT().bitsLE(NVT)) {
2318 GetExpandedInteger(N->getValue(), Lo, Hi);
2319 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2320 N->getMemoryVT(), isVolatile, isNonTemporal,
2321 Alignment);
2322 }
2323
2324 if (TLI.isLittleEndian()) {
2325 // Little-endian - low bits are at low addresses.
2326 GetExpandedInteger(N->getValue(), Lo, Hi);
2327
2328 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2329 isVolatile, isNonTemporal, Alignment);
2330
2331 unsigned ExcessBits =
2332 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2333 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2334
2335 // Increment the pointer to the other half.
2336 unsigned IncrementSize = NVT.getSizeInBits()/8;
2337 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2338 DAG.getIntPtrConstant(IncrementSize));
2339 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2340 N->getPointerInfo().getWithOffset(IncrementSize),
2341 NEVT, isVolatile, isNonTemporal,
2342 MinAlign(Alignment, IncrementSize));
2343 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2344 }
2345
2346 // Big-endian - high bits are at low addresses. Favor aligned stores at
2347 // the cost of some bit-fiddling.
2348 GetExpandedInteger(N->getValue(), Lo, Hi);
2349
2350 EVT ExtVT = N->getMemoryVT();
2351 unsigned EBytes = ExtVT.getStoreSize();
2352 unsigned IncrementSize = NVT.getSizeInBits()/8;
2353 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2354 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2355 ExtVT.getSizeInBits() - ExcessBits);
2356
2357 if (ExcessBits < NVT.getSizeInBits()) {
2358 // Transfer high bits from the top of Lo to the bottom of Hi.
2359 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2360 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2361 TLI.getPointerTy()));
2362 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2363 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2364 DAG.getConstant(ExcessBits,
2365 TLI.getPointerTy())));
2366 }
2367
2368 // Store both the high bits and maybe some of the low bits.
2369 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2370 HiVT, isVolatile, isNonTemporal, Alignment);
2371
2372 // Increment the pointer to the other half.
2373 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2374 DAG.getIntPtrConstant(IncrementSize));
2375 // Store the lowest ExcessBits bits in the second half.
2376 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2377 N->getPointerInfo().getWithOffset(IncrementSize),
2378 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2379 isVolatile, isNonTemporal,
2380 MinAlign(Alignment, IncrementSize));
2381 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2382 }
2383
2384 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2385 SDValue InL, InH;
2386 GetExpandedInteger(N->getOperand(0), InL, InH);
2387 // Just truncate the low part of the source.
2388 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2389 }
2390
2391 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2392 switch (VT.getSimpleVT().SimpleTy) {
2393 default: llvm_unreachable("Unknown FP format");
2394 case MVT::f32: return &APFloat::IEEEsingle;
2395 case MVT::f64: return &APFloat::IEEEdouble;
2396 case MVT::f80: return &APFloat::x87DoubleExtended;
2397 case MVT::f128: return &APFloat::IEEEquad;
2398 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2399 }
2400 }
2401
2402 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2403 SDValue Op = N->getOperand(0);
2404 EVT SrcVT = Op.getValueType();
2405 EVT DstVT = N->getValueType(0);
2406 DebugLoc dl = N->getDebugLoc();
2407
2408 // The following optimization is valid only if every value in SrcVT (when
2409 // treated as signed) is representable in DstVT. Check that the mantissa
2410 // size of DstVT is >= than the number of bits in SrcVT -1.
2411 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2412 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2413 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2414 // Do a signed conversion then adjust the result.
2415 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2416 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2417
2418 // The result of the signed conversion needs adjusting if the 'sign bit' of
2419 // the incoming integer was set. To handle this, we dynamically test to see
2420 // if it is set, and, if so, add a fudge factor.
2421
2422 const uint64_t F32TwoE32 = 0x4F800000ULL;
2423 const uint64_t F32TwoE64 = 0x5F800000ULL;
2424 const uint64_t F32TwoE128 = 0x7F800000ULL;
2425
2426 APInt FF(32, 0);
2427 if (SrcVT == MVT::i32)
2428 FF = APInt(32, F32TwoE32);
2429 else if (SrcVT == MVT::i64)
2430 FF = APInt(32, F32TwoE64);
2431 else if (SrcVT == MVT::i128)
2432 FF = APInt(32, F32TwoE128);
2433 else
2434 assert(false && "Unsupported UINT_TO_FP!");
2435
2436 // Check whether the sign bit is set.
2437 SDValue Lo, Hi;
2438 GetExpandedInteger(Op, Lo, Hi);
2439 SDValue SignSet = DAG.getSetCC(dl,
2440 TLI.getSetCCResultType(Hi.getValueType()),
2441 Hi, DAG.getConstant(0, Hi.getValueType()),
2442 ISD::SETLT);
2443
2444 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2445 SDValue FudgePtr = DAG.getConstantPool(
2446 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2447 TLI.getPointerTy());
2448
2449 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2450 SDValue Zero = DAG.getIntPtrConstant(0);
2451 SDValue Four = DAG.getIntPtrConstant(4);
2452 if (TLI.isBigEndian()) std::swap(Zero, Four);
2453 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2454 Zero, Four);
2455 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2456 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2457 Alignment = std::min(Alignment, 4u);
2458
2459 // Load the value out, extending it from f32 to the destination float type.
2460 // FIXME: Avoid the extend by constructing the right constant pool?
2461 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, dl, DAG.getEntryNode(),
2462 FudgePtr,
2463 MachinePointerInfo::getConstantPool(),
2464 MVT::f32,
2465 false, false, Alignment);
2466 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2467 }
2468
2469 // Otherwise, use a libcall.
2470 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2471 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2472 "Don't know how to expand this UINT_TO_FP!");
2473 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);
2474 }
ZPU llvm backend wip