Fixed some bugs.
[llvm/zpu.git] / lib / MC / MCDisassembler / EDInfo.h
blob627c06641dbc1357e0c04204eda860cef647dbb3
1 //===-- EDInfo.h - LLVM Enhanced Disassembler -------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_EDINFO_H
11 #define LLVM_EDINFO_H
13 enum {
14 EDIS_MAX_OPERANDS = 13,
15 EDIS_MAX_SYNTAXES = 2
18 enum OperandTypes {
19 kOperandTypeNone,
20 kOperandTypeImmediate,
21 kOperandTypeRegister,
22 kOperandTypeX86Memory,
23 kOperandTypeX86EffectiveAddress,
24 kOperandTypeX86PCRelative,
25 kOperandTypeARMBranchTarget,
26 kOperandTypeARMSoReg,
27 kOperandTypeARMSoImm,
28 kOperandTypeARMSoImm2Part,
29 kOperandTypeARMPredicate,
30 kOperandTypeARMAddrMode2,
31 kOperandTypeARMAddrMode2Offset,
32 kOperandTypeARMAddrMode3,
33 kOperandTypeARMAddrMode3Offset,
34 kOperandTypeARMAddrMode4,
35 kOperandTypeARMAddrMode5,
36 kOperandTypeARMAddrMode6,
37 kOperandTypeARMAddrMode6Offset,
38 kOperandTypeARMAddrModePC,
39 kOperandTypeARMRegisterList,
40 kOperandTypeARMTBAddrMode,
41 kOperandTypeThumbITMask,
42 kOperandTypeThumbAddrModeS1,
43 kOperandTypeThumbAddrModeS2,
44 kOperandTypeThumbAddrModeS4,
45 kOperandTypeThumbAddrModeRR,
46 kOperandTypeThumbAddrModeSP,
47 kOperandTypeThumb2SoReg,
48 kOperandTypeThumb2SoImm,
49 kOperandTypeThumb2AddrModeImm8,
50 kOperandTypeThumb2AddrModeImm8Offset,
51 kOperandTypeThumb2AddrModeImm12,
52 kOperandTypeThumb2AddrModeSoReg,
53 kOperandTypeThumb2AddrModeImm8s4,
54 kOperandTypeThumb2AddrModeImm8s4Offset
57 enum OperandFlags {
58 kOperandFlagSource = 0x1,
59 kOperandFlagTarget = 0x2
62 enum InstructionTypes {
63 kInstructionTypeNone,
64 kInstructionTypeMove,
65 kInstructionTypeBranch,
66 kInstructionTypePush,
67 kInstructionTypePop,
68 kInstructionTypeCall,
69 kInstructionTypeReturn
73 #endif