lib/Target/ARM/ARMBaseInstrInfo.h

   1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMBASEINSTRUCTIONINFO_H
  15 #define ARMBASEINSTRUCTIONINFO_H
  16
  17 #include "ARM.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/Target/TargetInstrInfo.h"
  20
  21 namespace llvm {
  22   class ARMSubtarget;
  23   class ARMBaseRegisterInfo;
  24
  25 /// ARMII - This namespace holds all of the target specific flags that
  26 /// instruction info tracks.
  27 ///
  28 namespace ARMII {
  29   enum {
  30     //===------------------------------------------------------------------===//
  31     // Instruction Flags.
  32
  33     //===------------------------------------------------------------------===//
  34     // This four-bit field describes the addressing mode used.
  35
  36     AddrModeMask  = 0x1f,
  37     AddrModeNone    = 0,
  38     AddrMode1       = 1,
  39     AddrMode2       = 2,
  40     AddrMode3       = 3,
  41     AddrMode4       = 4,
  42     AddrMode5       = 5,
  43     AddrMode6       = 6,
  44     AddrModeT1_1    = 7,
  45     AddrModeT1_2    = 8,
  46     AddrModeT1_4    = 9,
  47     AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
  48     AddrModeT2_i12  = 11,
  49     AddrModeT2_i8   = 12,
  50     AddrModeT2_so   = 13,
  51     AddrModeT2_pc   = 14, // +/- i12 for pc relative data
  52     AddrModeT2_i8s4 = 15, // i8 * 4
  53     AddrMode_i12    = 16,
  54
  55     // Size* - Flags to keep track of the size of an instruction.
  56     SizeShift     = 5,
  57     SizeMask      = 7 << SizeShift,
  58     SizeSpecial   = 1,   // 0 byte pseudo or special case.
  59     Size8Bytes    = 2,
  60     Size4Bytes    = 3,
  61     Size2Bytes    = 4,
  62
  63     // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
  64     // and store ops only.  Generic "updating" flag is used for ld/st multiple.
  65     IndexModeShift = 8,
  66     IndexModeMask  = 3 << IndexModeShift,
  67     IndexModePre   = 1,
  68     IndexModePost  = 2,
  69     IndexModeUpd   = 3,
  70
  71     //===------------------------------------------------------------------===//
  72     // Instruction encoding formats.
  73     //
  74     FormShift     = 10,
  75     FormMask      = 0x3f << FormShift,
  76
  77     // Pseudo instructions
  78     Pseudo        = 0  << FormShift,
  79
  80     // Multiply instructions
  81     MulFrm        = 1  << FormShift,
  82
  83     // Branch instructions
  84     BrFrm         = 2  << FormShift,
  85     BrMiscFrm     = 3  << FormShift,
  86
  87     // Data Processing instructions
  88     DPFrm         = 4  << FormShift,
  89     DPSoRegFrm    = 5  << FormShift,
  90
  91     // Load and Store
  92     LdFrm         = 6  << FormShift,
  93     StFrm         = 7  << FormShift,
  94     LdMiscFrm     = 8  << FormShift,
  95     StMiscFrm     = 9  << FormShift,
  96     LdStMulFrm    = 10 << FormShift,
  97
  98     LdStExFrm     = 11 << FormShift,
  99
 100     // Miscellaneous arithmetic instructions
 101     ArithMiscFrm  = 12 << FormShift,
 102     SatFrm        = 13 << FormShift,
 103
 104     // Extend instructions
 105     ExtFrm        = 14 << FormShift,
 106
 107     // VFP formats
 108     VFPUnaryFrm   = 15 << FormShift,
 109     VFPBinaryFrm  = 16 << FormShift,
 110     VFPConv1Frm   = 17 << FormShift,
 111     VFPConv2Frm   = 18 << FormShift,
 112     VFPConv3Frm   = 19 << FormShift,
 113     VFPConv4Frm   = 20 << FormShift,
 114     VFPConv5Frm   = 21 << FormShift,
 115     VFPLdStFrm    = 22 << FormShift,
 116     VFPLdStMulFrm = 23 << FormShift,
 117     VFPMiscFrm    = 24 << FormShift,
 118
 119     // Thumb format
 120     ThumbFrm      = 25 << FormShift,
 121
 122     // Miscelleaneous format
 123     MiscFrm       = 26 << FormShift,
 124
 125     // NEON formats
 126     NGetLnFrm     = 27 << FormShift,
 127     NSetLnFrm     = 28 << FormShift,
 128     NDupFrm       = 29 << FormShift,
 129     NLdStFrm      = 30 << FormShift,
 130     N1RegModImmFrm= 31 << FormShift,
 131     N2RegFrm      = 32 << FormShift,
 132     NVCVTFrm      = 33 << FormShift,
 133     NVDupLnFrm    = 34 << FormShift,
 134     N2RegVShLFrm  = 35 << FormShift,
 135     N2RegVShRFrm  = 36 << FormShift,
 136     N3RegFrm      = 37 << FormShift,
 137     N3RegVShFrm   = 38 << FormShift,
 138     NVExtFrm      = 39 << FormShift,
 139     NVMulSLFrm    = 40 << FormShift,
 140     NVTBLFrm      = 41 << FormShift,
 141
 142     //===------------------------------------------------------------------===//
 143     // Misc flags.
 144
 145     // UnaryDP - Indicates this is a unary data processing instruction, i.e.
 146     // it doesn't have a Rn operand.
 147     UnaryDP       = 1 << 16,
 148
 149     // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
 150     // a 16-bit Thumb instruction if certain conditions are met.
 151     Xform16Bit    = 1 << 17,
 152
 153     //===------------------------------------------------------------------===//
 154     // Code domain.
 155     DomainShift   = 18,
 156     DomainMask    = 3 << DomainShift,
 157     DomainGeneral = 0 << DomainShift,
 158     DomainVFP     = 1 << DomainShift,
 159     DomainNEON    = 2 << DomainShift,
 160
 161     //===------------------------------------------------------------------===//
 162     // Field shifts - such shifts are used to set field while generating
 163     // machine instructions.
 164     //
 165     // FIXME: This list will need adjusting/fixing as the MC code emitter
 166     // takes shape and the ARMCodeEmitter.cpp bits go away.
 167     ShiftTypeShift = 4,
 168
 169     M_BitShift     = 5,
 170     ShiftImmShift  = 5,
 171     ShiftShift     = 7,
 172     N_BitShift     = 7,
 173     ImmHiShift     = 8,
 174     SoRotImmShift  = 8,
 175     RegRsShift     = 8,
 176     ExtRotImmShift = 10,
 177     RegRdLoShift   = 12,
 178     RegRdShift     = 12,
 179     RegRdHiShift   = 16,
 180     RegRnShift     = 16,
 181     S_BitShift     = 20,
 182     W_BitShift     = 21,
 183     AM3_I_BitShift = 22,
 184     D_BitShift     = 22,
 185     U_BitShift     = 23,
 186     P_BitShift     = 24,
 187     I_BitShift     = 25,
 188     CondShift      = 28
 189   };
 190 }
 191
 192 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
 193   const ARMSubtarget &Subtarget;
 194 protected:
 195   // Can be only subclassed.
 196   explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
 197 public:
 198   // Return the non-pre/post incrementing version of 'Opc'. Return 0
 199   // if there is not such an opcode.
 200   virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
 201
 202   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
 203                                               MachineBasicBlock::iterator &MBBI,
 204                                               LiveVariables *LV) const;
 205
 206   virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
 207   const ARMSubtarget &getSubtarget() const { return Subtarget; }
 208
 209   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
 210                                  MachineBasicBlock::iterator MI,
 211                                  const std::vector<CalleeSavedInfo> &CSI,
 212                                  const TargetRegisterInfo *TRI) const;
 213
 214   // Branch analysis.
 215   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 216                              MachineBasicBlock *&FBB,
 217                              SmallVectorImpl<MachineOperand> &Cond,
 218                              bool AllowModify = false) const;
 219   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
 220   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 221                                 MachineBasicBlock *FBB,
 222                                 const SmallVectorImpl<MachineOperand> &Cond,
 223                                 DebugLoc DL) const;
 224
 225   virtual
 226   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 227
 228   // Predication support.
 229   bool isPredicated(const MachineInstr *MI) const {
 230     int PIdx = MI->findFirstPredOperandIdx();
 231     return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
 232   }
 233
 234   ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
 235     int PIdx = MI->findFirstPredOperandIdx();
 236     return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
 237                       : ARMCC::AL;
 238   }
 239
 240   virtual
 241   bool PredicateInstruction(MachineInstr *MI,
 242                             const SmallVectorImpl<MachineOperand> &Pred) const;
 243
 244   virtual
 245   bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
 246                          const SmallVectorImpl<MachineOperand> &Pred2) const;
 247
 248   virtual bool DefinesPredicate(MachineInstr *MI,
 249                                 std::vector<MachineOperand> &Pred) const;
 250
 251   virtual bool isPredicable(MachineInstr *MI) const;
 252
 253   /// GetInstSize - Returns the size of the specified MachineInstr.
 254   ///
 255   virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
 256
 257   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
 258                                        int &FrameIndex) const;
 259   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
 260                                       int &FrameIndex) const;
 261
 262   virtual void copyPhysReg(MachineBasicBlock &MBB,
 263                            MachineBasicBlock::iterator I, DebugLoc DL,
 264                            unsigned DestReg, unsigned SrcReg,
 265                            bool KillSrc) const;
 266
 267   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
 268                                    MachineBasicBlock::iterator MBBI,
 269                                    unsigned SrcReg, bool isKill, int FrameIndex,
 270                                    const TargetRegisterClass *RC,
 271                                    const TargetRegisterInfo *TRI) const;
 272
 273   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
 274                                     MachineBasicBlock::iterator MBBI,
 275                                     unsigned DestReg, int FrameIndex,
 276                                     const TargetRegisterClass *RC,
 277                                     const TargetRegisterInfo *TRI) const;
 278
 279   virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
 280                                                  int FrameIx,
 281                                                  uint64_t Offset,
 282                                                  const MDNode *MDPtr,
 283                                                  DebugLoc DL) const;
 284
 285   virtual void reMaterialize(MachineBasicBlock &MBB,
 286                              MachineBasicBlock::iterator MI,
 287                              unsigned DestReg, unsigned SubIdx,
 288                              const MachineInstr *Orig,
 289                              const TargetRegisterInfo &TRI) const;
 290
 291   MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
 292
 293   virtual bool produceSameValue(const MachineInstr *MI0,
 294                                 const MachineInstr *MI1) const;
 295
 296   /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
 297   /// determine if two loads are loading from the same base address. It should
 298   /// only return true if the base pointers are the same and the only
 299   /// differences between the two addresses is the offset. It also returns the
 300   /// offsets by reference.
 301   virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
 302                                        int64_t &Offset1, int64_t &Offset2)const;
 303
 304   /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
 305   /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
 306   /// be scheduled togther. On some targets if two loads are loading from
 307   /// addresses in the same cache line, it's better if they are scheduled
 308   /// together. This function takes two integers that represent the load offsets
 309   /// from the common base address. It returns true if it decides it's desirable
 310   /// to schedule the two loads together. "NumLoads" is the number of loads that
 311   /// have already been scheduled after Load1.
 312   virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
 313                                        int64_t Offset1, int64_t Offset2,
 314                                        unsigned NumLoads) const;
 315
 316   virtual bool isSchedulingBoundary(const MachineInstr *MI,
 317                                     const MachineBasicBlock *MBB,
 318                                     const MachineFunction &MF) const;
 319
 320   virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
 321                                    unsigned NumCyles, unsigned ExtraPredCycles,
 322                                    float Prob, float Confidence) const;
 323
 324   virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
 325                                    unsigned NumT, unsigned ExtraT,
 326                                    MachineBasicBlock &FMBB,
 327                                    unsigned NumF, unsigned ExtraF,
 328                                    float Probability, float Confidence) const;
 329
 330   virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
 331                                          unsigned NumCyles,
 332                                          float Probability,
 333                                          float Confidence) const {
 334     return NumCyles == 1;
 335   }
 336
 337   /// AnalyzeCompare - For a comparison instruction, return the source register
 338   /// in SrcReg and the value it compares against in CmpValue. Return true if
 339   /// the comparison instruction can be analyzed.
 340   virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
 341                               int &CmpMask, int &CmpValue) const;
 342
 343   /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
 344   /// that we can remove a "comparison with zero".
 345   virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
 346                                     int CmpMask, int CmpValue,
 347                                     const MachineRegisterInfo *MRI,
 348                                     MachineBasicBlock::iterator &MII) const;
 349
 350   virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
 351                                   const MachineInstr *MI) const;
 352
 353   virtual
 354   int getOperandLatency(const InstrItineraryData *ItinData,
 355                         const MachineInstr *DefMI, unsigned DefIdx,
 356                         const MachineInstr *UseMI, unsigned UseIdx) const;
 357   virtual
 358   int getOperandLatency(const InstrItineraryData *ItinData,
 359                         SDNode *DefNode, unsigned DefIdx,
 360                         SDNode *UseNode, unsigned UseIdx) const;
 361 private:
 362   int getVLDMDefCycle(const InstrItineraryData *ItinData,
 363                       const TargetInstrDesc &DefTID,
 364                       unsigned DefClass,
 365                       unsigned DefIdx, unsigned DefAlign) const;
 366   int getLDMDefCycle(const InstrItineraryData *ItinData,
 367                      const TargetInstrDesc &DefTID,
 368                      unsigned DefClass,
 369                      unsigned DefIdx, unsigned DefAlign) const;
 370   int getVSTMUseCycle(const InstrItineraryData *ItinData,
 371                       const TargetInstrDesc &UseTID,
 372                       unsigned UseClass,
 373                       unsigned UseIdx, unsigned UseAlign) const;
 374   int getSTMUseCycle(const InstrItineraryData *ItinData,
 375                      const TargetInstrDesc &UseTID,
 376                      unsigned UseClass,
 377                      unsigned UseIdx, unsigned UseAlign) const;
 378   int getOperandLatency(const InstrItineraryData *ItinData,
 379                         const TargetInstrDesc &DefTID,
 380                         unsigned DefIdx, unsigned DefAlign,
 381                         const TargetInstrDesc &UseTID,
 382                         unsigned UseIdx, unsigned UseAlign) const;
 383
 384   int getInstrLatency(const InstrItineraryData *ItinData,
 385                       const MachineInstr *MI, unsigned *PredCost = 0) const;
 386
 387   int getInstrLatency(const InstrItineraryData *ItinData,
 388                       SDNode *Node) const;
 389
 390   bool hasHighOperandLatency(const InstrItineraryData *ItinData,
 391                              const MachineRegisterInfo *MRI,
 392                              const MachineInstr *DefMI, unsigned DefIdx,
 393                              const MachineInstr *UseMI, unsigned UseIdx) const;
 394   bool hasLowDefLatency(const InstrItineraryData *ItinData,
 395                         const MachineInstr *DefMI, unsigned DefIdx) const;
 396 };
 397
 398 static inline
 399 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
 400   return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
 401 }
 402
 403 static inline
 404 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
 405   return MIB.addReg(0);
 406 }
 407
 408 static inline
 409 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
 410                                           bool isDead = false) {
 411   return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
 412 }
 413
 414 static inline
 415 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
 416   return MIB.addReg(0);
 417 }
 418
 419 static inline
 420 bool isUncondBranchOpcode(int Opc) {
 421   return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
 422 }
 423
 424 static inline
 425 bool isCondBranchOpcode(int Opc) {
 426   return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
 427 }
 428
 429 static inline
 430 bool isJumpTableBranchOpcode(int Opc) {
 431   return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
 432     Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
 433 }
 434
 435 static inline
 436 bool isIndirectBranchOpcode(int Opc) {
 437   return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
 438 }
 439
 440 /// getInstrPredicate - If instruction is predicated, returns its predicate
 441 /// condition, otherwise returns AL. It also returns the condition code
 442 /// register by reference.
 443 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
 444
 445 int getMatchingCondBranchOpcode(int Opc);
 446
 447 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
 448 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
 449 /// code.
 450 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
 451                              MachineBasicBlock::iterator &MBBI, DebugLoc dl,
 452                              unsigned DestReg, unsigned BaseReg, int NumBytes,
 453                              ARMCC::CondCodes Pred, unsigned PredReg,
 454                              const ARMBaseInstrInfo &TII);
 455
 456 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
 457                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
 458                             unsigned DestReg, unsigned BaseReg, int NumBytes,
 459                             ARMCC::CondCodes Pred, unsigned PredReg,
 460                             const ARMBaseInstrInfo &TII);
 461 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
 462                                MachineBasicBlock::iterator &MBBI,
 463                                unsigned DestReg, unsigned BaseReg,
 464                                int NumBytes, const TargetInstrInfo &TII,
 465                                const ARMBaseRegisterInfo& MRI,
 466                                DebugLoc dl);
 467
 468
 469 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
 470 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
 471 /// offset could not be handled directly in MI, and return the left-over
 472 /// portion by reference.
 473 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
 474                           unsigned FrameReg, int &Offset,
 475                           const ARMBaseInstrInfo &TII);
 476
 477 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
 478                          unsigned FrameReg, int &Offset,
 479                          const ARMBaseInstrInfo &TII);
 480
 481 } // End llvm namespace
 482
 483 #endif