lib/Target/ARM/ARMBaseRegisterInfo.h

   1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the base ARM implementation of TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMBASEREGISTERINFO_H
  15 #define ARMBASEREGISTERINFO_H
  16
  17 #include "ARM.h"
  18 #include "llvm/Target/TargetRegisterInfo.h"
  19 #include "ARMGenRegisterInfo.h.inc"
  20
  21 namespace llvm {
  22   class ARMSubtarget;
  23   class ARMBaseInstrInfo;
  24   class Type;
  25
  26 /// Register allocation hints.
  27 namespace ARMRI {
  28   enum {
  29     RegPairOdd  = 1,
  30     RegPairEven = 2
  31   };
  32 }
  33
  34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
  35 ///
  36 static inline bool isARMLowRegister(unsigned Reg) {
  37   using namespace ARM;
  38   switch (Reg) {
  39   case R0:  case R1:  case R2:  case R3:
  40   case R4:  case R5:  case R6:  case R7:
  41     return true;
  42   default:
  43     return false;
  44   }
  45 }
  46
  47 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
  48 protected:
  49   const ARMBaseInstrInfo &TII;
  50   const ARMSubtarget &STI;
  51
  52   /// FramePtr - ARM physical register used as frame ptr.
  53   unsigned FramePtr;
  54
  55   /// BasePtr - ARM physical register used as a base ptr in complex stack
  56   /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
  57   /// variable size stack objects.
  58   unsigned BasePtr;
  59
  60   // Can be only subclassed.
  61   explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
  62                                const ARMSubtarget &STI);
  63
  64   // Return the opcode that implements 'Op', or 0 if no opcode
  65   unsigned getOpcode(int Op) const;
  66
  67 public:
  68   /// Code Generation virtual methods...
  69   const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
  70
  71   BitVector getReservedRegs(const MachineFunction &MF) const;
  72
  73   /// getMatchingSuperRegClass - Return a subclass of the specified register
  74   /// class A so that each register in it has a sub-register of the
  75   /// specified sub-register index which is in the specified register class B.
  76   virtual const TargetRegisterClass *
  77   getMatchingSuperRegClass(const TargetRegisterClass *A,
  78                            const TargetRegisterClass *B, unsigned Idx) const;
  79
  80   /// canCombineSubRegIndices - Given a register class and a list of
  81   /// subregister indices, return true if it's possible to combine the
  82   /// subregister indices into one that corresponds to a larger
  83   /// subregister. Return the new subregister index by reference. Note the
  84   /// new index may be zero if the given subregisters can be combined to
  85   /// form the whole register.
  86   virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
  87                                        SmallVectorImpl<unsigned> &SubIndices,
  88                                        unsigned &NewSubIdx) const;
  89
  90   const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
  91
  92   std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
  93   getAllocationOrder(const TargetRegisterClass *RC,
  94                      unsigned HintType, unsigned HintReg,
  95                      const MachineFunction &MF) const;
  96
  97   unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
  98                                const MachineFunction &MF) const;
  99
 100   void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
 101                           MachineFunction &MF) const;
 102
 103   bool hasFP(const MachineFunction &MF) const;
 104   bool hasBasePointer(const MachineFunction &MF) const;
 105
 106   bool canRealignStack(const MachineFunction &MF) const;
 107   bool needsStackRealignment(const MachineFunction &MF) const;
 108   int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
 109   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
 110   void materializeFrameBaseRegister(MachineBasicBlock::iterator I,
 111                                     unsigned BaseReg, int FrameIdx,
 112                                     int64_t Offset) const;
 113   void resolveFrameIndex(MachineBasicBlock::iterator I,
 114                          unsigned BaseReg, int64_t Offset) const;
 115   bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
 116
 117   bool cannotEliminateFrame(const MachineFunction &MF) const;
 118
 119   void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
 120                                             RegScavenger *RS = NULL) const;
 121
 122   // Debug information queries.
 123   unsigned getRARegister() const;
 124   unsigned getFrameRegister(const MachineFunction &MF) const;
 125   int getFrameIndexReference(const MachineFunction &MF, int FI,
 126                              unsigned &FrameReg) const;
 127   int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
 128                                  unsigned &FrameReg, int SPAdj) const;
 129   int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
 130
 131   // Exception handling queries.
 132   unsigned getEHExceptionRegister() const;
 133   unsigned getEHHandlerRegister() const;
 134
 135   int getDwarfRegNum(unsigned RegNum, bool isEH) const;
 136
 137   bool isLowRegister(unsigned Reg) const;
 138
 139
 140   /// emitLoadConstPool - Emits a load from constpool to materialize the
 141   /// specified immediate.
 142   virtual void emitLoadConstPool(MachineBasicBlock &MBB,
 143                                  MachineBasicBlock::iterator &MBBI,
 144                                  DebugLoc dl,
 145                                  unsigned DestReg, unsigned SubIdx,
 146                                  int Val,
 147                                  ARMCC::CondCodes Pred = ARMCC::AL,
 148                                  unsigned PredReg = 0) const;
 149
 150   /// Code Generation virtual methods...
 151   virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
 152
 153   virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
 154
 155   virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
 156
 157   virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
 158
 159   virtual bool hasReservedCallFrame(const MachineFunction &MF) const;
 160   virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
 161
 162   virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
 163                                            MachineBasicBlock &MBB,
 164                                            MachineBasicBlock::iterator I) const;
 165
 166   virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
 167                                    int SPAdj, RegScavenger *RS = NULL) const;
 168
 169   virtual void emitPrologue(MachineFunction &MF) const;
 170   virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 171
 172 private:
 173   unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
 174
 175   unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
 176
 177   unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
 178 };
 179
 180 } // end namespace llvm
 181
 182 #endif