lib/Target/ARM/ARMCodeEmitter.cpp

   1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the pass that transforms the ARM machine instructions into
  11 // relocatable machine code.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "jit"
  16 #include "ARM.h"
  17 #include "ARMAddressingModes.h"
  18 #include "ARMConstantPoolValue.h"
  19 #include "ARMInstrInfo.h"
  20 #include "ARMRelocations.h"
  21 #include "ARMSubtarget.h"
  22 #include "ARMTargetMachine.h"
  23 #include "llvm/Constants.h"
  24 #include "llvm/DerivedTypes.h"
  25 #include "llvm/Function.h"
  26 #include "llvm/PassManager.h"
  27 #include "llvm/CodeGen/JITCodeEmitter.h"
  28 #include "llvm/CodeGen/MachineConstantPool.h"
  29 #include "llvm/CodeGen/MachineFunctionPass.h"
  30 #include "llvm/CodeGen/MachineInstr.h"
  31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
  32 #include "llvm/CodeGen/MachineModuleInfo.h"
  33 #include "llvm/CodeGen/Passes.h"
  34 #include "llvm/ADT/Statistic.h"
  35 #include "llvm/Support/Debug.h"
  36 #include "llvm/Support/ErrorHandling.h"
  37 #include "llvm/Support/raw_ostream.h"
  38 #ifndef NDEBUG
  39 #include <iomanip>
  40 #endif
  41 using namespace llvm;
  42
  43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
  44
  45 namespace {
  46
  47   class ARMCodeEmitter : public MachineFunctionPass {
  48     ARMJITInfo                *JTI;
  49     const ARMInstrInfo        *II;
  50     const TargetData          *TD;
  51     const ARMSubtarget        *Subtarget;
  52     TargetMachine             &TM;
  53     JITCodeEmitter            &MCE;
  54     MachineModuleInfo *MMI;
  55     const std::vector<MachineConstantPoolEntry> *MCPEs;
  56     const std::vector<MachineJumpTableEntry> *MJTEs;
  57     bool IsPIC;
  58     bool IsThumb;
  59
  60     void getAnalysisUsage(AnalysisUsage &AU) const {
  61       AU.addRequired<MachineModuleInfo>();
  62       MachineFunctionPass::getAnalysisUsage(AU);
  63     }
  64
  65     static char ID;
  66   public:
  67     ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
  68       : MachineFunctionPass(ID), JTI(0),
  69         II((const ARMInstrInfo *)tm.getInstrInfo()),
  70         TD(tm.getTargetData()), TM(tm),
  71         MCE(mce), MCPEs(0), MJTEs(0),
  72         IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
  73
  74     /// getBinaryCodeForInstr - This function, generated by the
  75     /// CodeEmitterGenerator using TableGen, produces the binary encoding for
  76     /// machine instructions.
  77     unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
  78
  79     bool runOnMachineFunction(MachineFunction &MF);
  80
  81     virtual const char *getPassName() const {
  82       return "ARM Machine Code Emitter";
  83     }
  84
  85     void emitInstruction(const MachineInstr &MI);
  86
  87   private:
  88
  89     void emitWordLE(unsigned Binary);
  90     void emitDWordLE(uint64_t Binary);
  91     void emitConstPoolInstruction(const MachineInstr &MI);
  92     void emitMOVi32immInstruction(const MachineInstr &MI);
  93     void emitMOVi2piecesInstruction(const MachineInstr &MI);
  94     void emitLEApcrelJTInstruction(const MachineInstr &MI);
  95     void emitPseudoMoveInstruction(const MachineInstr &MI);
  96     void addPCLabel(unsigned LabelID);
  97     void emitPseudoInstruction(const MachineInstr &MI);
  98     unsigned getMachineSoRegOpValue(const MachineInstr &MI,
  99                                     const TargetInstrDesc &TID,
 100                                     const MachineOperand &MO,
 101                                     unsigned OpIdx);
 102
 103     unsigned getMachineSoImmOpValue(unsigned SoImm);
 104     unsigned getAddrModeSBit(const MachineInstr &MI,
 105                              const TargetInstrDesc &TID) const;
 106
 107     void emitDataProcessingInstruction(const MachineInstr &MI,
 108                                        unsigned ImplicitRd = 0,
 109                                        unsigned ImplicitRn = 0);
 110
 111     void emitLoadStoreInstruction(const MachineInstr &MI,
 112                                   unsigned ImplicitRd = 0,
 113                                   unsigned ImplicitRn = 0);
 114
 115     void emitMiscLoadStoreInstruction(const MachineInstr &MI,
 116                                       unsigned ImplicitRn = 0);
 117
 118     void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
 119
 120     void emitMulFrmInstruction(const MachineInstr &MI);
 121
 122     void emitExtendInstruction(const MachineInstr &MI);
 123
 124     void emitMiscArithInstruction(const MachineInstr &MI);
 125
 126     void emitSaturateInstruction(const MachineInstr &MI);
 127
 128     void emitBranchInstruction(const MachineInstr &MI);
 129
 130     void emitInlineJumpTable(unsigned JTIndex);
 131
 132     void emitMiscBranchInstruction(const MachineInstr &MI);
 133
 134     void emitVFPArithInstruction(const MachineInstr &MI);
 135
 136     void emitVFPConversionInstruction(const MachineInstr &MI);
 137
 138     void emitVFPLoadStoreInstruction(const MachineInstr &MI);
 139
 140     void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
 141
 142     void emitNEONLaneInstruction(const MachineInstr &MI);
 143     void emitNEONDupInstruction(const MachineInstr &MI);
 144     void emitNEON1RegModImmInstruction(const MachineInstr &MI);
 145     void emitNEON2RegInstruction(const MachineInstr &MI);
 146     void emitNEON3RegInstruction(const MachineInstr &MI);
 147
 148     /// getMachineOpValue - Return binary encoding of operand. If the machine
 149     /// operand requires relocation, record the relocation and return zero.
 150     unsigned getMachineOpValue(const MachineInstr &MI,
 151                                const MachineOperand &MO) const;
 152     unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
 153       return getMachineOpValue(MI, MI.getOperand(OpIdx));
 154     }
 155
 156     // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
 157     //  TableGen'erated getBinaryCodeForInstr() function to encode any
 158     //  operand values, instead querying getMachineOpValue() directly for
 159     //  each operand it needs to encode. Thus, any of the new encoder
 160     //  helper functions can simply return 0 as the values the return
 161     //  are already handled elsewhere. They are placeholders to allow this
 162     //  encoder to continue to function until the MC encoder is sufficiently
 163     //  far along that this one can be eliminated entirely.
 164     unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
 165       const { return 0; }
 166     unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
 167       const { return 0; }
 168     unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
 169       const { return 0; }
 170     unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
 171       const { return 0; }
 172     unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
 173       const { return 0; }
 174     unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
 175       const { return 0; }
 176     unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
 177       const { return 0; }
 178     unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
 179                                             unsigned Op) const { return 0; }
 180
 181     unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
 182       const {
 183       // {17-13} = reg
 184       // {12}    = (U)nsigned (add == '1', sub == '0')
 185       // {11-0}  = imm12
 186       const MachineOperand &MO  = MI.getOperand(Op);
 187       const MachineOperand &MO1 = MI.getOperand(Op + 1);
 188       if (!MO.isReg()) {
 189         emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
 190         return 0;
 191       }
 192       unsigned Reg = getARMRegisterNumbering(MO.getReg());
 193       int32_t Imm12 = MO1.getImm();
 194       uint32_t Binary;
 195       Binary = Imm12 & 0xfff;
 196       if (Imm12 >= 0)
 197         Binary |= (1 << 12);
 198       Binary |= (Reg << 13);
 199       return Binary;
 200     }
 201     uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
 202       // {12-9}  = reg
 203       // {8}     = (U)nsigned (add == '1', sub == '0')
 204       // {7-0}   = imm12
 205       const MachineOperand &MO  = MI.getOperand(Op);
 206       const MachineOperand &MO1 = MI.getOperand(Op + 1);
 207       if (!MO.isReg()) {
 208         emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
 209         return 0;
 210       }
 211       unsigned Reg = getARMRegisterNumbering(MO.getReg());
 212       int32_t Imm8 = MO1.getImm();
 213       uint32_t Binary;
 214       Binary = Imm8 & 0xff;
 215       if (Imm8 >= 0)
 216         Binary |= (1 << 8);
 217       Binary |= (Reg << 9);
 218       return Binary;
 219     }
 220     unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
 221       const { return 0; }
 222
 223     unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
 224       const { return 0; }
 225
 226     /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
 227     /// machine operand requires relocation, record the relocation and return
 228     /// zero.
 229     unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
 230                             unsigned Reloc);
 231
 232     /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
 233     ///
 234     unsigned getShiftOp(unsigned Imm) const ;
 235
 236     /// Routines that handle operands which add machine relocations which are
 237     /// fixed up by the relocation stage.
 238     void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
 239                            bool MayNeedFarStub,  bool Indirect,
 240                            intptr_t ACPV = 0) const;
 241     void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
 242     void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
 243     void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
 244     void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
 245                                intptr_t JTBase = 0) const;
 246   };
 247 }
 248
 249 char ARMCodeEmitter::ID = 0;
 250
 251 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
 252 /// code to the specified MCE object.
 253 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
 254                                                 JITCodeEmitter &JCE) {
 255   return new ARMCodeEmitter(TM, JCE);
 256 }
 257
 258 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
 259   assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
 260           MF.getTarget().getRelocationModel() != Reloc::Static) &&
 261          "JIT relocation model must be set to static or default!");
 262   JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
 263   II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
 264   TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
 265   Subtarget = &TM.getSubtarget<ARMSubtarget>();
 266   MCPEs = &MF.getConstantPool()->getConstants();
 267   MJTEs = 0;
 268   if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
 269   IsPIC = TM.getRelocationModel() == Reloc::PIC_;
 270   IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
 271   JTI->Initialize(MF, IsPIC);
 272   MMI = &getAnalysis<MachineModuleInfo>();
 273   MCE.setModuleInfo(MMI);
 274
 275   do {
 276     DEBUG(errs() << "JITTing function '"
 277           << MF.getFunction()->getName() << "'\n");
 278     MCE.startFunction(MF);
 279     for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
 280          MBB != E; ++MBB) {
 281       MCE.StartMachineBasicBlock(MBB);
 282       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
 283            I != E; ++I)
 284         emitInstruction(*I);
 285     }
 286   } while (MCE.finishFunction(MF));
 287
 288   return false;
 289 }
 290
 291 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
 292 ///
 293 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
 294   switch (ARM_AM::getAM2ShiftOpc(Imm)) {
 295   default: llvm_unreachable("Unknown shift opc!");
 296   case ARM_AM::asr: return 2;
 297   case ARM_AM::lsl: return 0;
 298   case ARM_AM::lsr: return 1;
 299   case ARM_AM::ror:
 300   case ARM_AM::rrx: return 3;
 301   }
 302   return 0;
 303 }
 304
 305 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
 306 /// machine operand requires relocation, record the relocation and return zero.
 307 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
 308                                         const MachineOperand &MO,
 309                                         unsigned Reloc) {
 310   assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
 311       && "Relocation to this function should be for movt or movw");
 312
 313   if (MO.isImm())
 314     return static_cast<unsigned>(MO.getImm());
 315   else if (MO.isGlobal())
 316     emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
 317   else if (MO.isSymbol())
 318     emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
 319   else if (MO.isMBB())
 320     emitMachineBasicBlock(MO.getMBB(), Reloc);
 321   else {
 322 #ifndef NDEBUG
 323     errs() << MO;
 324 #endif
 325     llvm_unreachable("Unsupported operand type for movw/movt");
 326   }
 327   return 0;
 328 }
 329
 330 /// getMachineOpValue - Return binary encoding of operand. If the machine
 331 /// operand requires relocation, record the relocation and return zero.
 332 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
 333                                            const MachineOperand &MO) const {
 334   if (MO.isReg())
 335     return getARMRegisterNumbering(MO.getReg());
 336   else if (MO.isImm())
 337     return static_cast<unsigned>(MO.getImm());
 338   else if (MO.isGlobal())
 339     emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
 340   else if (MO.isSymbol())
 341     emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
 342   else if (MO.isCPI()) {
 343     const TargetInstrDesc &TID = MI.getDesc();
 344     // For VFP load, the immediate offset is multiplied by 4.
 345     unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
 346       ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
 347     emitConstPoolAddress(MO.getIndex(), Reloc);
 348   } else if (MO.isJTI())
 349     emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
 350   else if (MO.isMBB())
 351     emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
 352   else {
 353 #ifndef NDEBUG
 354     errs() << MO;
 355 #endif
 356     llvm_unreachable(0);
 357   }
 358   return 0;
 359 }
 360
 361 /// emitGlobalAddress - Emit the specified address to the code stream.
 362 ///
 363 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
 364                                        bool MayNeedFarStub, bool Indirect,
 365                                        intptr_t ACPV) const {
 366   MachineRelocation MR = Indirect
 367     ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
 368                                            const_cast<GlobalValue *>(GV),
 369                                            ACPV, MayNeedFarStub)
 370     : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
 371                                const_cast<GlobalValue *>(GV), ACPV,
 372                                MayNeedFarStub);
 373   MCE.addRelocation(MR);
 374 }
 375
 376 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
 377 /// be emitted to the current location in the function, and allow it to be PC
 378 /// relative.
 379 void ARMCodeEmitter::
 380 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
 381   MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
 382                                                  Reloc, ES));
 383 }
 384
 385 /// emitConstPoolAddress - Arrange for the address of an constant pool
 386 /// to be emitted to the current location in the function, and allow it to be PC
 387 /// relative.
 388 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
 389   // Tell JIT emitter we'll resolve the address.
 390   MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
 391                                                     Reloc, CPI, 0, true));
 392 }
 393
 394 /// emitJumpTableAddress - Arrange for the address of a jump table to
 395 /// be emitted to the current location in the function, and allow it to be PC
 396 /// relative.
 397 void ARMCodeEmitter::
 398 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
 399   MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
 400                                                     Reloc, JTIndex, 0, true));
 401 }
 402
 403 /// emitMachineBasicBlock - Emit the specified address basic block.
 404 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
 405                                            unsigned Reloc,
 406                                            intptr_t JTBase) const {
 407   MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
 408                                              Reloc, BB, JTBase));
 409 }
 410
 411 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
 412   DEBUG(errs() << "  0x";
 413         errs().write_hex(Binary) << "\n");
 414   MCE.emitWordLE(Binary);
 415 }
 416
 417 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
 418   DEBUG(errs() << "  0x";
 419         errs().write_hex(Binary) << "\n");
 420   MCE.emitDWordLE(Binary);
 421 }
 422
 423 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
 424   DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
 425
 426   MCE.processDebugLoc(MI.getDebugLoc(), true);
 427
 428   ++NumEmitted;  // Keep track of the # of mi's emitted
 429   switch (MI.getDesc().TSFlags & ARMII::FormMask) {
 430   default: {
 431     llvm_unreachable("Unhandled instruction encoding format!");
 432     break;
 433   }
 434   case ARMII::Pseudo:
 435     emitPseudoInstruction(MI);
 436     break;
 437   case ARMII::DPFrm:
 438   case ARMII::DPSoRegFrm:
 439     emitDataProcessingInstruction(MI);
 440     break;
 441   case ARMII::LdFrm:
 442   case ARMII::StFrm:
 443     emitLoadStoreInstruction(MI);
 444     break;
 445   case ARMII::LdMiscFrm:
 446   case ARMII::StMiscFrm:
 447     emitMiscLoadStoreInstruction(MI);
 448     break;
 449   case ARMII::LdStMulFrm:
 450     emitLoadStoreMultipleInstruction(MI);
 451     break;
 452   case ARMII::MulFrm:
 453     emitMulFrmInstruction(MI);
 454     break;
 455   case ARMII::ExtFrm:
 456     emitExtendInstruction(MI);
 457     break;
 458   case ARMII::ArithMiscFrm:
 459     emitMiscArithInstruction(MI);
 460     break;
 461   case ARMII::SatFrm:
 462     emitSaturateInstruction(MI);
 463     break;
 464   case ARMII::BrFrm:
 465     emitBranchInstruction(MI);
 466     break;
 467   case ARMII::BrMiscFrm:
 468     emitMiscBranchInstruction(MI);
 469     break;
 470   // VFP instructions.
 471   case ARMII::VFPUnaryFrm:
 472   case ARMII::VFPBinaryFrm:
 473     emitVFPArithInstruction(MI);
 474     break;
 475   case ARMII::VFPConv1Frm:
 476   case ARMII::VFPConv2Frm:
 477   case ARMII::VFPConv3Frm:
 478   case ARMII::VFPConv4Frm:
 479   case ARMII::VFPConv5Frm:
 480     emitVFPConversionInstruction(MI);
 481     break;
 482   case ARMII::VFPLdStFrm:
 483     emitVFPLoadStoreInstruction(MI);
 484     break;
 485   case ARMII::VFPLdStMulFrm:
 486     emitVFPLoadStoreMultipleInstruction(MI);
 487     break;
 488
 489   // NEON instructions.
 490   case ARMII::NGetLnFrm:
 491   case ARMII::NSetLnFrm:
 492     emitNEONLaneInstruction(MI);
 493     break;
 494   case ARMII::NDupFrm:
 495     emitNEONDupInstruction(MI);
 496     break;
 497   case ARMII::N1RegModImmFrm:
 498     emitNEON1RegModImmInstruction(MI);
 499     break;
 500   case ARMII::N2RegFrm:
 501     emitNEON2RegInstruction(MI);
 502     break;
 503   case ARMII::N3RegFrm:
 504     emitNEON3RegInstruction(MI);
 505     break;
 506   }
 507   MCE.processDebugLoc(MI.getDebugLoc(), false);
 508 }
 509
 510 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
 511   unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
 512   unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
 513   const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
 514
 515   // Remember the CONSTPOOL_ENTRY address for later relocation.
 516   JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
 517
 518   // Emit constpool island entry. In most cases, the actual values will be
 519   // resolved and relocated after code emission.
 520   if (MCPE.isMachineConstantPoolEntry()) {
 521     ARMConstantPoolValue *ACPV =
 522       static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
 523
 524     DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
 525           << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
 526
 527     assert(ACPV->isGlobalValue() && "unsupported constant pool value");
 528     const GlobalValue *GV = ACPV->getGV();
 529     if (GV) {
 530       Reloc::Model RelocM = TM.getRelocationModel();
 531       emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
 532                         isa<Function>(GV),
 533                         Subtarget->GVIsIndirectSymbol(GV, RelocM),
 534                         (intptr_t)ACPV);
 535      } else  {
 536       emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
 537     }
 538     emitWordLE(0);
 539   } else {
 540     const Constant *CV = MCPE.Val.ConstVal;
 541
 542     DEBUG({
 543         errs() << "  ** Constant pool #" << CPI << " @ "
 544                << (void*)MCE.getCurrentPCValue() << " ";
 545         if (const Function *F = dyn_cast<Function>(CV))
 546           errs() << F->getName();
 547         else
 548           errs() << *CV;
 549         errs() << '\n';
 550       });
 551
 552     if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
 553       emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
 554       emitWordLE(0);
 555     } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
 556       uint32_t Val = uint32_t(*CI->getValue().getRawData());
 557       emitWordLE(Val);
 558     } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
 559       if (CFP->getType()->isFloatTy())
 560         emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
 561       else if (CFP->getType()->isDoubleTy())
 562         emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
 563       else {
 564         llvm_unreachable("Unable to handle this constantpool entry!");
 565       }
 566     } else {
 567       llvm_unreachable("Unable to handle this constantpool entry!");
 568     }
 569   }
 570 }
 571
 572 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
 573   const MachineOperand &MO0 = MI.getOperand(0);
 574   const MachineOperand &MO1 = MI.getOperand(1);
 575
 576   // Emit the 'movw' instruction.
 577   unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
 578
 579   unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
 580
 581   // Set the conditional execution predicate.
 582   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 583
 584   // Encode Rd.
 585   Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
 586
 587   // Encode imm16 as imm4:imm12
 588   Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
 589   Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
 590   emitWordLE(Binary);
 591
 592   unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
 593   // Emit the 'movt' instruction.
 594   Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
 595
 596   // Set the conditional execution predicate.
 597   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 598
 599   // Encode Rd.
 600   Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
 601
 602   // Encode imm16 as imm4:imm1, same as movw above.
 603   Binary |= Hi16 & 0xFFF;
 604   Binary |= ((Hi16 >> 12) & 0xF) << 16;
 605   emitWordLE(Binary);
 606 }
 607
 608 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
 609   const MachineOperand &MO0 = MI.getOperand(0);
 610   const MachineOperand &MO1 = MI.getOperand(1);
 611   assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
 612                                                   "Not a valid so_imm value!");
 613   unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
 614   unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
 615
 616   // Emit the 'mov' instruction.
 617   unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
 618
 619   // Set the conditional execution predicate.
 620   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 621
 622   // Encode Rd.
 623   Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
 624
 625   // Encode so_imm.
 626   // Set bit I(25) to identify this is the immediate form of <shifter_op>
 627   Binary |= 1 << ARMII::I_BitShift;
 628   Binary |= getMachineSoImmOpValue(V1);
 629   emitWordLE(Binary);
 630
 631   // Now the 'orr' instruction.
 632   Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
 633
 634   // Set the conditional execution predicate.
 635   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 636
 637   // Encode Rd.
 638   Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
 639
 640   // Encode Rn.
 641   Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
 642
 643   // Encode so_imm.
 644   // Set bit I(25) to identify this is the immediate form of <shifter_op>
 645   Binary |= 1 << ARMII::I_BitShift;
 646   Binary |= getMachineSoImmOpValue(V2);
 647   emitWordLE(Binary);
 648 }
 649
 650 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
 651   // It's basically add r, pc, (LJTI - $+8)
 652
 653   const TargetInstrDesc &TID = MI.getDesc();
 654
 655   // Emit the 'add' instruction.
 656   unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
 657
 658   // Set the conditional execution predicate
 659   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 660
 661   // Encode S bit if MI modifies CPSR.
 662   Binary |= getAddrModeSBit(MI, TID);
 663
 664   // Encode Rd.
 665   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
 666
 667   // Encode Rn which is PC.
 668   Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
 669
 670   // Encode the displacement.
 671   Binary |= 1 << ARMII::I_BitShift;
 672   emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
 673
 674   emitWordLE(Binary);
 675 }
 676
 677 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
 678   unsigned Opcode = MI.getDesc().Opcode;
 679
 680   // Part of binary is determined by TableGn.
 681   unsigned Binary = getBinaryCodeForInstr(MI);
 682
 683   // Set the conditional execution predicate
 684   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 685
 686   // Encode S bit if MI modifies CPSR.
 687   if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
 688     Binary |= 1 << ARMII::S_BitShift;
 689
 690   // Encode register def if there is one.
 691   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
 692
 693   // Encode the shift operation.
 694   switch (Opcode) {
 695   default: break;
 696   case ARM::RRX:
 697     // rrx
 698     Binary |= 0x6 << 4;
 699     break;
 700   case ARM::MOVsrl_flag:
 701     // lsr #1
 702     Binary |= (0x2 << 4) | (1 << 7);
 703     break;
 704   case ARM::MOVsra_flag:
 705     // asr #1
 706     Binary |= (0x4 << 4) | (1 << 7);
 707     break;
 708   }
 709
 710   // Encode register Rm.
 711   Binary |= getMachineOpValue(MI, 1);
 712
 713   emitWordLE(Binary);
 714 }
 715
 716 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
 717   DEBUG(errs() << "  ** LPC" << LabelID << " @ "
 718         << (void*)MCE.getCurrentPCValue() << '\n');
 719   JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
 720 }
 721
 722 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
 723   unsigned Opcode = MI.getDesc().Opcode;
 724   switch (Opcode) {
 725   default:
 726     llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
 727   case ARM::BX:
 728   case ARM::BMOVPCRX:
 729   case ARM::BXr9:
 730   case ARM::BMOVPCRXr9: {
 731     // First emit mov lr, pc
 732     unsigned Binary = 0x01a0e00f;
 733     Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 734     emitWordLE(Binary);
 735
 736     // and then emit the branch.
 737     emitMiscBranchInstruction(MI);
 738     break;
 739   }
 740   case TargetOpcode::INLINEASM: {
 741     // We allow inline assembler nodes with empty bodies - they can
 742     // implicitly define registers, which is ok for JIT.
 743     if (MI.getOperand(0).getSymbolName()[0]) {
 744       report_fatal_error("JIT does not support inline asm!");
 745     }
 746     break;
 747   }
 748   case TargetOpcode::PROLOG_LABEL:
 749   case TargetOpcode::EH_LABEL:
 750     MCE.emitLabel(MI.getOperand(0).getMCSymbol());
 751     break;
 752   case TargetOpcode::IMPLICIT_DEF:
 753   case TargetOpcode::KILL:
 754     // Do nothing.
 755     break;
 756   case ARM::CONSTPOOL_ENTRY:
 757     emitConstPoolInstruction(MI);
 758     break;
 759   case ARM::PICADD: {
 760     // Remember of the address of the PC label for relocation later.
 761     addPCLabel(MI.getOperand(2).getImm());
 762     // PICADD is just an add instruction that implicitly read pc.
 763     emitDataProcessingInstruction(MI, 0, ARM::PC);
 764     break;
 765   }
 766   case ARM::PICLDR:
 767   case ARM::PICLDRB:
 768   case ARM::PICSTR:
 769   case ARM::PICSTRB: {
 770     // Remember of the address of the PC label for relocation later.
 771     addPCLabel(MI.getOperand(2).getImm());
 772     // These are just load / store instructions that implicitly read pc.
 773     emitLoadStoreInstruction(MI, 0, ARM::PC);
 774     break;
 775   }
 776   case ARM::PICLDRH:
 777   case ARM::PICLDRSH:
 778   case ARM::PICLDRSB:
 779   case ARM::PICSTRH: {
 780     // Remember of the address of the PC label for relocation later.
 781     addPCLabel(MI.getOperand(2).getImm());
 782     // These are just load / store instructions that implicitly read pc.
 783     emitMiscLoadStoreInstruction(MI, ARM::PC);
 784     break;
 785   }
 786
 787   case ARM::MOVi32imm:
 788     emitMOVi32immInstruction(MI);
 789     break;
 790
 791   case ARM::MOVi2pieces:
 792     // Two instructions to materialize a constant.
 793     emitMOVi2piecesInstruction(MI);
 794     break;
 795   case ARM::LEApcrelJT:
 796     // Materialize jumptable address.
 797     emitLEApcrelJTInstruction(MI);
 798     break;
 799   case ARM::RRX:
 800   case ARM::MOVsrl_flag:
 801   case ARM::MOVsra_flag:
 802     emitPseudoMoveInstruction(MI);
 803     break;
 804   }
 805 }
 806
 807 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
 808                                                 const TargetInstrDesc &TID,
 809                                                 const MachineOperand &MO,
 810                                                 unsigned OpIdx) {
 811   unsigned Binary = getMachineOpValue(MI, MO);
 812
 813   const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
 814   const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
 815   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
 816
 817   // Encode the shift opcode.
 818   unsigned SBits = 0;
 819   unsigned Rs = MO1.getReg();
 820   if (Rs) {
 821     // Set shift operand (bit[7:4]).
 822     // LSL - 0001
 823     // LSR - 0011
 824     // ASR - 0101
 825     // ROR - 0111
 826     // RRX - 0110 and bit[11:8] clear.
 827     switch (SOpc) {
 828     default: llvm_unreachable("Unknown shift opc!");
 829     case ARM_AM::lsl: SBits = 0x1; break;
 830     case ARM_AM::lsr: SBits = 0x3; break;
 831     case ARM_AM::asr: SBits = 0x5; break;
 832     case ARM_AM::ror: SBits = 0x7; break;
 833     case ARM_AM::rrx: SBits = 0x6; break;
 834     }
 835   } else {
 836     // Set shift operand (bit[6:4]).
 837     // LSL - 000
 838     // LSR - 010
 839     // ASR - 100
 840     // ROR - 110
 841     switch (SOpc) {
 842     default: llvm_unreachable("Unknown shift opc!");
 843     case ARM_AM::lsl: SBits = 0x0; break;
 844     case ARM_AM::lsr: SBits = 0x2; break;
 845     case ARM_AM::asr: SBits = 0x4; break;
 846     case ARM_AM::ror: SBits = 0x6; break;
 847     }
 848   }
 849   Binary |= SBits << 4;
 850   if (SOpc == ARM_AM::rrx)
 851     return Binary;
 852
 853   // Encode the shift operation Rs or shift_imm (except rrx).
 854   if (Rs) {
 855     // Encode Rs bit[11:8].
 856     assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
 857     return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
 858   }
 859
 860   // Encode shift_imm bit[11:7].
 861   return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
 862 }
 863
 864 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
 865   int SoImmVal = ARM_AM::getSOImmVal(SoImm);
 866   assert(SoImmVal != -1 && "Not a valid so_imm value!");
 867
 868   // Encode rotate_imm.
 869   unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
 870     << ARMII::SoRotImmShift;
 871
 872   // Encode immed_8.
 873   Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
 874   return Binary;
 875 }
 876
 877 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
 878                                          const TargetInstrDesc &TID) const {
 879   for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
 880     const MachineOperand &MO = MI.getOperand(i-1);
 881     if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
 882       return 1 << ARMII::S_BitShift;
 883   }
 884   return 0;
 885 }
 886
 887 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
 888                                                    unsigned ImplicitRd,
 889                                                    unsigned ImplicitRn) {
 890   const TargetInstrDesc &TID = MI.getDesc();
 891
 892   // Part of binary is determined by TableGn.
 893   unsigned Binary = getBinaryCodeForInstr(MI);
 894
 895   // Set the conditional execution predicate
 896   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 897
 898   // Encode S bit if MI modifies CPSR.
 899   Binary |= getAddrModeSBit(MI, TID);
 900
 901   // Encode register def if there is one.
 902   unsigned NumDefs = TID.getNumDefs();
 903   unsigned OpIdx = 0;
 904   if (NumDefs)
 905     Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
 906   else if (ImplicitRd)
 907     // Special handling for implicit use (e.g. PC).
 908     Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
 909
 910   if (TID.Opcode == ARM::MOVi16) {
 911       // Get immediate from MI.
 912       unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
 913                       ARM::reloc_arm_movw);
 914       // Encode imm which is the same as in emitMOVi32immInstruction().
 915       Binary |= Lo16 & 0xFFF;
 916       Binary |= ((Lo16 >> 12) & 0xF) << 16;
 917       emitWordLE(Binary);
 918       return;
 919   } else if(TID.Opcode == ARM::MOVTi16) {
 920       unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
 921                        ARM::reloc_arm_movt) >> 16);
 922       Binary |= Hi16 & 0xFFF;
 923       Binary |= ((Hi16 >> 12) & 0xF) << 16;
 924       emitWordLE(Binary);
 925       return;
 926   } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
 927       uint32_t v = ~MI.getOperand(2).getImm();
 928       int32_t lsb = CountTrailingZeros_32(v);
 929       int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
 930       // Instr{20-16} = msb, Instr{11-7} = lsb
 931       Binary |= (msb & 0x1F) << 16;
 932       Binary |= (lsb & 0x1F) << 7;
 933       emitWordLE(Binary);
 934       return;
 935   } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
 936       // Encode Rn in Instr{0-3}
 937       Binary |= getMachineOpValue(MI, OpIdx++);
 938
 939       uint32_t lsb = MI.getOperand(OpIdx++).getImm();
 940       uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
 941
 942       // Instr{20-16} = widthm1, Instr{11-7} = lsb
 943       Binary |= (widthm1 & 0x1F) << 16;
 944       Binary |= (lsb & 0x1F) << 7;
 945       emitWordLE(Binary);
 946       return;
 947   }
 948
 949   // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
 950   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
 951     ++OpIdx;
 952
 953   // Encode first non-shifter register operand if there is one.
 954   bool isUnary = TID.TSFlags & ARMII::UnaryDP;
 955   if (!isUnary) {
 956     if (ImplicitRn)
 957       // Special handling for implicit use (e.g. PC).
 958       Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
 959     else {
 960       Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
 961       ++OpIdx;
 962     }
 963   }
 964
 965   // Encode shifter operand.
 966   const MachineOperand &MO = MI.getOperand(OpIdx);
 967   if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
 968     // Encode SoReg.
 969     emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
 970     return;
 971   }
 972
 973   if (MO.isReg()) {
 974     // Encode register Rm.
 975     emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
 976     return;
 977   }
 978
 979   // Encode so_imm.
 980   Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
 981
 982   emitWordLE(Binary);
 983 }
 984
 985 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
 986                                               unsigned ImplicitRd,
 987                                               unsigned ImplicitRn) {
 988   const TargetInstrDesc &TID = MI.getDesc();
 989   unsigned Form = TID.TSFlags & ARMII::FormMask;
 990   bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
 991
 992   // Part of binary is determined by TableGn.
 993   unsigned Binary = getBinaryCodeForInstr(MI);
 994
 995   // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
 996   if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
 997       MI.getOpcode() == ARM::STRi12) {
 998     emitWordLE(Binary);
 999     return;
1000   }
1001
1002   // Set the conditional execution predicate
1003   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1004
1005   unsigned OpIdx = 0;
1006
1007   // Operand 0 of a pre- and post-indexed store is the address base
1008   // writeback. Skip it.
1009   bool Skipped = false;
1010   if (IsPrePost && Form == ARMII::StFrm) {
1011     ++OpIdx;
1012     Skipped = true;
1013   }
1014
1015   // Set first operand
1016   if (ImplicitRd)
1017     // Special handling for implicit use (e.g. PC).
1018     Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1019   else
1020     Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1021
1022   // Set second operand
1023   if (ImplicitRn)
1024     // Special handling for implicit use (e.g. PC).
1025     Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1026   else
1027     Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1028
1029   // If this is a two-address operand, skip it. e.g. LDR_PRE.
1030   if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1031     ++OpIdx;
1032
1033   const MachineOperand &MO2 = MI.getOperand(OpIdx);
1034   unsigned AM2Opc = (ImplicitRn == ARM::PC)
1035     ? 0 : MI.getOperand(OpIdx+1).getImm();
1036
1037   // Set bit U(23) according to sign of immed value (positive or negative).
1038   Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1039              ARMII::U_BitShift);
1040   if (!MO2.getReg()) { // is immediate
1041     if (ARM_AM::getAM2Offset(AM2Opc))
1042       // Set the value of offset_12 field
1043       Binary |= ARM_AM::getAM2Offset(AM2Opc);
1044     emitWordLE(Binary);
1045     return;
1046   }
1047
1048   // Set bit I(25), because this is not in immediate encoding.
1049   Binary |= 1 << ARMII::I_BitShift;
1050   assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1051   // Set bit[3:0] to the corresponding Rm register
1052   Binary |= getARMRegisterNumbering(MO2.getReg());
1053
1054   // If this instr is in scaled register offset/index instruction, set
1055   // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1056   if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1057     Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1058     Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1059   }
1060
1061   emitWordLE(Binary);
1062 }
1063
1064 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1065                                                   unsigned ImplicitRn) {
1066   const TargetInstrDesc &TID = MI.getDesc();
1067   unsigned Form = TID.TSFlags & ARMII::FormMask;
1068   bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1069
1070   // Part of binary is determined by TableGn.
1071   unsigned Binary = getBinaryCodeForInstr(MI);
1072
1073   // Set the conditional execution predicate
1074   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1075
1076   unsigned OpIdx = 0;
1077
1078   // Operand 0 of a pre- and post-indexed store is the address base
1079   // writeback. Skip it.
1080   bool Skipped = false;
1081   if (IsPrePost && Form == ARMII::StMiscFrm) {
1082     ++OpIdx;
1083     Skipped = true;
1084   }
1085
1086   // Set first operand
1087   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1088
1089   // Skip LDRD and STRD's second operand.
1090   if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1091     ++OpIdx;
1092
1093   // Set second operand
1094   if (ImplicitRn)
1095     // Special handling for implicit use (e.g. PC).
1096     Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1097   else
1098     Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1099
1100   // If this is a two-address operand, skip it. e.g. LDRH_POST.
1101   if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1102     ++OpIdx;
1103
1104   const MachineOperand &MO2 = MI.getOperand(OpIdx);
1105   unsigned AM3Opc = (ImplicitRn == ARM::PC)
1106     ? 0 : MI.getOperand(OpIdx+1).getImm();
1107
1108   // Set bit U(23) according to sign of immed value (positive or negative)
1109   Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1110              ARMII::U_BitShift);
1111
1112   // If this instr is in register offset/index encoding, set bit[3:0]
1113   // to the corresponding Rm register.
1114   if (MO2.getReg()) {
1115     Binary |= getARMRegisterNumbering(MO2.getReg());
1116     emitWordLE(Binary);
1117     return;
1118   }
1119
1120   // This instr is in immediate offset/index encoding, set bit 22 to 1.
1121   Binary |= 1 << ARMII::AM3_I_BitShift;
1122   if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1123     // Set operands
1124     Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1125     Binary |= (ImmOffs & 0xF);                      // immedL
1126   }
1127
1128   emitWordLE(Binary);
1129 }
1130
1131 static unsigned getAddrModeUPBits(unsigned Mode) {
1132   unsigned Binary = 0;
1133
1134   // Set addressing mode by modifying bits U(23) and P(24)
1135   // IA - Increment after  - bit U = 1 and bit P = 0
1136   // IB - Increment before - bit U = 1 and bit P = 1
1137   // DA - Decrement after  - bit U = 0 and bit P = 0
1138   // DB - Decrement before - bit U = 0 and bit P = 1
1139   switch (Mode) {
1140   default: llvm_unreachable("Unknown addressing sub-mode!");
1141   case ARM_AM::da:                                     break;
1142   case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1143   case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1144   case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1145   }
1146
1147   return Binary;
1148 }
1149
1150 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1151   const TargetInstrDesc &TID = MI.getDesc();
1152   bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1153
1154   // Part of binary is determined by TableGn.
1155   unsigned Binary = getBinaryCodeForInstr(MI);
1156
1157   // Set the conditional execution predicate
1158   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1159
1160   // Skip operand 0 of an instruction with base register update.
1161   unsigned OpIdx = 0;
1162   if (IsUpdating)
1163     ++OpIdx;
1164
1165   // Set base address operand
1166   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1167
1168   // Set addressing mode by modifying bits U(23) and P(24)
1169   const MachineOperand &MO = MI.getOperand(OpIdx++);
1170   Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1171
1172   // Set bit W(21)
1173   if (IsUpdating)
1174     Binary |= 0x1 << ARMII::W_BitShift;
1175
1176   // Set registers
1177   for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1178     const MachineOperand &MO = MI.getOperand(i);
1179     if (!MO.isReg() || MO.isImplicit())
1180       break;
1181     unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1182     assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1183            RegNum < 16);
1184     Binary |= 0x1 << RegNum;
1185   }
1186
1187   emitWordLE(Binary);
1188 }
1189
1190 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1191   const TargetInstrDesc &TID = MI.getDesc();
1192
1193   // Part of binary is determined by TableGn.
1194   unsigned Binary = getBinaryCodeForInstr(MI);
1195
1196   // Set the conditional execution predicate
1197   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1198
1199   // Encode S bit if MI modifies CPSR.
1200   Binary |= getAddrModeSBit(MI, TID);
1201
1202   // 32x32->64bit operations have two destination registers. The number
1203   // of register definitions will tell us if that's what we're dealing with.
1204   unsigned OpIdx = 0;
1205   if (TID.getNumDefs() == 2)
1206     Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1207
1208   // Encode Rd
1209   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1210
1211   // Encode Rm
1212   Binary |= getMachineOpValue(MI, OpIdx++);
1213
1214   // Encode Rs
1215   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1216
1217   // Many multiple instructions (e.g. MLA) have three src operands. Encode
1218   // it as Rn (for multiply, that's in the same offset as RdLo.
1219   if (TID.getNumOperands() > OpIdx &&
1220       !TID.OpInfo[OpIdx].isPredicate() &&
1221       !TID.OpInfo[OpIdx].isOptionalDef())
1222     Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1223
1224   emitWordLE(Binary);
1225 }
1226
1227 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1228   const TargetInstrDesc &TID = MI.getDesc();
1229
1230   // Part of binary is determined by TableGn.
1231   unsigned Binary = getBinaryCodeForInstr(MI);
1232
1233   // Set the conditional execution predicate
1234   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1235
1236   unsigned OpIdx = 0;
1237
1238   // Encode Rd
1239   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1240
1241   const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1242   const MachineOperand &MO2 = MI.getOperand(OpIdx);
1243   if (MO2.isReg()) {
1244     // Two register operand form.
1245     // Encode Rn.
1246     Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1247
1248     // Encode Rm.
1249     Binary |= getMachineOpValue(MI, MO2);
1250     ++OpIdx;
1251   } else {
1252     Binary |= getMachineOpValue(MI, MO1);
1253   }
1254
1255   // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1256   if (MI.getOperand(OpIdx).isImm() &&
1257       !TID.OpInfo[OpIdx].isPredicate() &&
1258       !TID.OpInfo[OpIdx].isOptionalDef())
1259     Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1260
1261   emitWordLE(Binary);
1262 }
1263
1264 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1265   const TargetInstrDesc &TID = MI.getDesc();
1266
1267   // Part of binary is determined by TableGn.
1268   unsigned Binary = getBinaryCodeForInstr(MI);
1269
1270   // Set the conditional execution predicate
1271   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1272
1273   unsigned OpIdx = 0;
1274
1275   // Encode Rd
1276   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1277
1278   const MachineOperand &MO = MI.getOperand(OpIdx++);
1279   if (OpIdx == TID.getNumOperands() ||
1280       TID.OpInfo[OpIdx].isPredicate() ||
1281       TID.OpInfo[OpIdx].isOptionalDef()) {
1282     // Encode Rm and it's done.
1283     Binary |= getMachineOpValue(MI, MO);
1284     emitWordLE(Binary);
1285     return;
1286   }
1287
1288   // Encode Rn.
1289   Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1290
1291   // Encode Rm.
1292   Binary |= getMachineOpValue(MI, OpIdx++);
1293
1294   // Encode shift_imm.
1295   unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1296   if (TID.Opcode == ARM::PKHTB) {
1297     assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1298     if (ShiftAmt == 32)
1299       ShiftAmt = 0;
1300   }
1301   assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1302   Binary |= ShiftAmt << ARMII::ShiftShift;
1303
1304   emitWordLE(Binary);
1305 }
1306
1307 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1308   const TargetInstrDesc &TID = MI.getDesc();
1309
1310   // Part of binary is determined by TableGen.
1311   unsigned Binary = getBinaryCodeForInstr(MI);
1312
1313   // Set the conditional execution predicate
1314   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1315
1316   // Encode Rd
1317   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1318
1319   // Encode saturate bit position.
1320   unsigned Pos = MI.getOperand(1).getImm();
1321   if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1322     Pos -= 1;
1323   assert((Pos < 16 || (Pos < 32 &&
1324                        TID.Opcode != ARM::SSAT16 &&
1325                        TID.Opcode != ARM::USAT16)) &&
1326          "saturate bit position out of range");
1327   Binary |= Pos << 16;
1328
1329   // Encode Rm
1330   Binary |= getMachineOpValue(MI, 2);
1331
1332   // Encode shift_imm.
1333   if (TID.getNumOperands() == 4) {
1334     unsigned ShiftOp = MI.getOperand(3).getImm();
1335     ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1336     if (Opc == ARM_AM::asr)
1337       Binary |= (1 << 6);
1338     unsigned ShiftAmt = MI.getOperand(3).getImm();
1339     if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1340       ShiftAmt = 0;
1341     assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1342     Binary |= ShiftAmt << ARMII::ShiftShift;
1343   }
1344
1345   emitWordLE(Binary);
1346 }
1347
1348 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1349   const TargetInstrDesc &TID = MI.getDesc();
1350
1351   if (TID.Opcode == ARM::TPsoft) {
1352     llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1353   }
1354
1355   // Part of binary is determined by TableGn.
1356   unsigned Binary = getBinaryCodeForInstr(MI);
1357
1358   // Set the conditional execution predicate
1359   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1360
1361   // Set signed_immed_24 field
1362   Binary |= getMachineOpValue(MI, 0);
1363
1364   emitWordLE(Binary);
1365 }
1366
1367 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1368   // Remember the base address of the inline jump table.
1369   uintptr_t JTBase = MCE.getCurrentPCValue();
1370   JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1371   DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1372                << '\n');
1373
1374   // Now emit the jump table entries.
1375   const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1376   for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1377     if (IsPIC)
1378       // DestBB address - JT base.
1379       emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1380     else
1381       // Absolute DestBB address.
1382       emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1383     emitWordLE(0);
1384   }
1385 }
1386
1387 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1388   const TargetInstrDesc &TID = MI.getDesc();
1389
1390   // Handle jump tables.
1391   if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1392     // First emit a ldr pc, [] instruction.
1393     emitDataProcessingInstruction(MI, ARM::PC);
1394
1395     // Then emit the inline jump table.
1396     unsigned JTIndex =
1397       (TID.Opcode == ARM::BR_JTr)
1398       ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1399     emitInlineJumpTable(JTIndex);
1400     return;
1401   } else if (TID.Opcode == ARM::BR_JTm) {
1402     // First emit a ldr pc, [] instruction.
1403     emitLoadStoreInstruction(MI, ARM::PC);
1404
1405     // Then emit the inline jump table.
1406     emitInlineJumpTable(MI.getOperand(3).getIndex());
1407     return;
1408   }
1409
1410   // Part of binary is determined by TableGn.
1411   unsigned Binary = getBinaryCodeForInstr(MI);
1412
1413   // Set the conditional execution predicate
1414   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1415
1416   if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1417     // The return register is LR.
1418     Binary |= getARMRegisterNumbering(ARM::LR);
1419   else
1420     // otherwise, set the return register
1421     Binary |= getMachineOpValue(MI, 0);
1422
1423   emitWordLE(Binary);
1424 }
1425
1426 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1427   unsigned RegD = MI.getOperand(OpIdx).getReg();
1428   unsigned Binary = 0;
1429   bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1430   RegD = getARMRegisterNumbering(RegD);
1431   if (!isSPVFP)
1432     Binary |=   RegD               << ARMII::RegRdShift;
1433   else {
1434     Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1435     Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1436   }
1437   return Binary;
1438 }
1439
1440 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1441   unsigned RegN = MI.getOperand(OpIdx).getReg();
1442   unsigned Binary = 0;
1443   bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1444   RegN = getARMRegisterNumbering(RegN);
1445   if (!isSPVFP)
1446     Binary |=   RegN               << ARMII::RegRnShift;
1447   else {
1448     Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1449     Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1450   }
1451   return Binary;
1452 }
1453
1454 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1455   unsigned RegM = MI.getOperand(OpIdx).getReg();
1456   unsigned Binary = 0;
1457   bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1458   RegM = getARMRegisterNumbering(RegM);
1459   if (!isSPVFP)
1460     Binary |=   RegM;
1461   else {
1462     Binary |= ((RegM & 0x1E) >> 1);
1463     Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1464   }
1465   return Binary;
1466 }
1467
1468 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1469   const TargetInstrDesc &TID = MI.getDesc();
1470
1471   // Part of binary is determined by TableGn.
1472   unsigned Binary = getBinaryCodeForInstr(MI);
1473
1474   // Set the conditional execution predicate
1475   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1476
1477   unsigned OpIdx = 0;
1478   assert((Binary & ARMII::D_BitShift) == 0 &&
1479          (Binary & ARMII::N_BitShift) == 0 &&
1480          (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1481
1482   // Encode Dd / Sd.
1483   Binary |= encodeVFPRd(MI, OpIdx++);
1484
1485   // If this is a two-address operand, skip it, e.g. FMACD.
1486   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1487     ++OpIdx;
1488
1489   // Encode Dn / Sn.
1490   if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1491     Binary |= encodeVFPRn(MI, OpIdx++);
1492
1493   if (OpIdx == TID.getNumOperands() ||
1494       TID.OpInfo[OpIdx].isPredicate() ||
1495       TID.OpInfo[OpIdx].isOptionalDef()) {
1496     // FCMPEZD etc. has only one operand.
1497     emitWordLE(Binary);
1498     return;
1499   }
1500
1501   // Encode Dm / Sm.
1502   Binary |= encodeVFPRm(MI, OpIdx);
1503
1504   emitWordLE(Binary);
1505 }
1506
1507 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1508   const TargetInstrDesc &TID = MI.getDesc();
1509   unsigned Form = TID.TSFlags & ARMII::FormMask;
1510
1511   // Part of binary is determined by TableGn.
1512   unsigned Binary = getBinaryCodeForInstr(MI);
1513
1514   // Set the conditional execution predicate
1515   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1516
1517   switch (Form) {
1518   default: break;
1519   case ARMII::VFPConv1Frm:
1520   case ARMII::VFPConv2Frm:
1521   case ARMII::VFPConv3Frm:
1522     // Encode Dd / Sd.
1523     Binary |= encodeVFPRd(MI, 0);
1524     break;
1525   case ARMII::VFPConv4Frm:
1526     // Encode Dn / Sn.
1527     Binary |= encodeVFPRn(MI, 0);
1528     break;
1529   case ARMII::VFPConv5Frm:
1530     // Encode Dm / Sm.
1531     Binary |= encodeVFPRm(MI, 0);
1532     break;
1533   }
1534
1535   switch (Form) {
1536   default: break;
1537   case ARMII::VFPConv1Frm:
1538     // Encode Dm / Sm.
1539     Binary |= encodeVFPRm(MI, 1);
1540     break;
1541   case ARMII::VFPConv2Frm:
1542   case ARMII::VFPConv3Frm:
1543     // Encode Dn / Sn.
1544     Binary |= encodeVFPRn(MI, 1);
1545     break;
1546   case ARMII::VFPConv4Frm:
1547   case ARMII::VFPConv5Frm:
1548     // Encode Dd / Sd.
1549     Binary |= encodeVFPRd(MI, 1);
1550     break;
1551   }
1552
1553   if (Form == ARMII::VFPConv5Frm)
1554     // Encode Dn / Sn.
1555     Binary |= encodeVFPRn(MI, 2);
1556   else if (Form == ARMII::VFPConv3Frm)
1557     // Encode Dm / Sm.
1558     Binary |= encodeVFPRm(MI, 2);
1559
1560   emitWordLE(Binary);
1561 }
1562
1563 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1564   // Part of binary is determined by TableGn.
1565   unsigned Binary = getBinaryCodeForInstr(MI);
1566
1567   // Set the conditional execution predicate
1568   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1569
1570   unsigned OpIdx = 0;
1571
1572   // Encode Dd / Sd.
1573   Binary |= encodeVFPRd(MI, OpIdx++);
1574
1575   // Encode address base.
1576   const MachineOperand &Base = MI.getOperand(OpIdx++);
1577   Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1578
1579   // If there is a non-zero immediate offset, encode it.
1580   if (Base.isReg()) {
1581     const MachineOperand &Offset = MI.getOperand(OpIdx);
1582     if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1583       if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1584         Binary |= 1 << ARMII::U_BitShift;
1585       Binary |= ImmOffs;
1586       emitWordLE(Binary);
1587       return;
1588     }
1589   }
1590
1591   // If immediate offset is omitted, default to +0.
1592   Binary |= 1 << ARMII::U_BitShift;
1593
1594   emitWordLE(Binary);
1595 }
1596
1597 void
1598 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1599   const TargetInstrDesc &TID = MI.getDesc();
1600   bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1601
1602   // Part of binary is determined by TableGn.
1603   unsigned Binary = getBinaryCodeForInstr(MI);
1604
1605   // Set the conditional execution predicate
1606   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1607
1608   // Skip operand 0 of an instruction with base register update.
1609   unsigned OpIdx = 0;
1610   if (IsUpdating)
1611     ++OpIdx;
1612
1613   // Set base address operand
1614   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1615
1616   // Set addressing mode by modifying bits U(23) and P(24)
1617   const MachineOperand &MO = MI.getOperand(OpIdx++);
1618   Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1619
1620   // Set bit W(21)
1621   if (IsUpdating)
1622     Binary |= 0x1 << ARMII::W_BitShift;
1623
1624   // First register is encoded in Dd.
1625   Binary |= encodeVFPRd(MI, OpIdx+2);
1626
1627   // Count the number of registers.
1628   unsigned NumRegs = 1;
1629   for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1630     const MachineOperand &MO = MI.getOperand(i);
1631     if (!MO.isReg() || MO.isImplicit())
1632       break;
1633     ++NumRegs;
1634   }
1635   // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1636   // Otherwise, it will be 0, in the case of 32-bit registers.
1637   if(Binary & 0x100)
1638     Binary |= NumRegs * 2;
1639   else
1640     Binary |= NumRegs;
1641
1642   emitWordLE(Binary);
1643 }
1644
1645 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1646   unsigned RegD = MI.getOperand(OpIdx).getReg();
1647   unsigned Binary = 0;
1648   RegD = getARMRegisterNumbering(RegD);
1649   Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1650   Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1651   return Binary;
1652 }
1653
1654 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1655   unsigned RegN = MI.getOperand(OpIdx).getReg();
1656   unsigned Binary = 0;
1657   RegN = getARMRegisterNumbering(RegN);
1658   Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1659   Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1660   return Binary;
1661 }
1662
1663 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1664   unsigned RegM = MI.getOperand(OpIdx).getReg();
1665   unsigned Binary = 0;
1666   RegM = getARMRegisterNumbering(RegM);
1667   Binary |= (RegM & 0xf);
1668   Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1669   return Binary;
1670 }
1671
1672 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1673 /// data-processing instruction to the corresponding Thumb encoding.
1674 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1675   assert((Binary & 0xfe000000) == 0xf2000000 &&
1676          "not an ARM NEON data-processing instruction");
1677   unsigned UBit = (Binary >> 24) & 1;
1678   return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1679 }
1680
1681 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1682   unsigned Binary = getBinaryCodeForInstr(MI);
1683
1684   unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1685   const TargetInstrDesc &TID = MI.getDesc();
1686   if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1687     RegTOpIdx = 0;
1688     RegNOpIdx = 1;
1689     LnOpIdx = 2;
1690   } else { // ARMII::NSetLnFrm
1691     RegTOpIdx = 2;
1692     RegNOpIdx = 0;
1693     LnOpIdx = 3;
1694   }
1695
1696   // Set the conditional execution predicate
1697   Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1698
1699   unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1700   RegT = getARMRegisterNumbering(RegT);
1701   Binary |= (RegT << ARMII::RegRdShift);
1702   Binary |= encodeNEONRn(MI, RegNOpIdx);
1703
1704   unsigned LaneShift;
1705   if ((Binary & (1 << 22)) != 0)
1706     LaneShift = 0; // 8-bit elements
1707   else if ((Binary & (1 << 5)) != 0)
1708     LaneShift = 1; // 16-bit elements
1709   else
1710     LaneShift = 2; // 32-bit elements
1711
1712   unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1713   unsigned Opc1 = Lane >> 2;
1714   unsigned Opc2 = Lane & 3;
1715   assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1716   Binary |= (Opc1 << 21);
1717   Binary |= (Opc2 << 5);
1718
1719   emitWordLE(Binary);
1720 }
1721
1722 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1723   unsigned Binary = getBinaryCodeForInstr(MI);
1724
1725   // Set the conditional execution predicate
1726   Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1727
1728   unsigned RegT = MI.getOperand(1).getReg();
1729   RegT = getARMRegisterNumbering(RegT);
1730   Binary |= (RegT << ARMII::RegRdShift);
1731   Binary |= encodeNEONRn(MI, 0);
1732   emitWordLE(Binary);
1733 }
1734
1735 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1736   unsigned Binary = getBinaryCodeForInstr(MI);
1737   // Destination register is encoded in Dd.
1738   Binary |= encodeNEONRd(MI, 0);
1739   // Immediate fields: Op, Cmode, I, Imm3, Imm4
1740   unsigned Imm = MI.getOperand(1).getImm();
1741   unsigned Op = (Imm >> 12) & 1;
1742   unsigned Cmode = (Imm >> 8) & 0xf;
1743   unsigned I = (Imm >> 7) & 1;
1744   unsigned Imm3 = (Imm >> 4) & 0x7;
1745   unsigned Imm4 = Imm & 0xf;
1746   Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1747   if (IsThumb)
1748     Binary = convertNEONDataProcToThumb(Binary);
1749   emitWordLE(Binary);
1750 }
1751
1752 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1753   const TargetInstrDesc &TID = MI.getDesc();
1754   unsigned Binary = getBinaryCodeForInstr(MI);
1755   // Destination register is encoded in Dd; source register in Dm.
1756   unsigned OpIdx = 0;
1757   Binary |= encodeNEONRd(MI, OpIdx++);
1758   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1759     ++OpIdx;
1760   Binary |= encodeNEONRm(MI, OpIdx);
1761   if (IsThumb)
1762     Binary = convertNEONDataProcToThumb(Binary);
1763   // FIXME: This does not handle VDUPfdf or VDUPfqf.
1764   emitWordLE(Binary);
1765 }
1766
1767 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1768   const TargetInstrDesc &TID = MI.getDesc();
1769   unsigned Binary = getBinaryCodeForInstr(MI);
1770   // Destination register is encoded in Dd; source registers in Dn and Dm.
1771   unsigned OpIdx = 0;
1772   Binary |= encodeNEONRd(MI, OpIdx++);
1773   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1774     ++OpIdx;
1775   Binary |= encodeNEONRn(MI, OpIdx++);
1776   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1777     ++OpIdx;
1778   Binary |= encodeNEONRm(MI, OpIdx);
1779   if (IsThumb)
1780     Binary = convertNEONDataProcToThumb(Binary);
1781   // FIXME: This does not handle VMOVDneon or VMOVQ.
1782   emitWordLE(Binary);
1783 }
1784
1785 #include "ARMGenCodeEmitter.inc"