lib/Target/ARM/ARMFastISel.cpp

   1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the ARM-specific support for the FastISel class. Some
  11 // of the target-specific code is generated by tablegen in the file
  12 // ARMGenFastISel.inc, which is #included here.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "ARM.h"
  17 #include "ARMBaseInstrInfo.h"
  18 #include "ARMCallingConv.h"
  19 #include "ARMRegisterInfo.h"
  20 #include "ARMTargetMachine.h"
  21 #include "ARMSubtarget.h"
  22 #include "ARMConstantPoolValue.h"
  23 #include "llvm/CallingConv.h"
  24 #include "llvm/DerivedTypes.h"
  25 #include "llvm/GlobalVariable.h"
  26 #include "llvm/Instructions.h"
  27 #include "llvm/IntrinsicInst.h"
  28 #include "llvm/Module.h"
  29 #include "llvm/CodeGen/Analysis.h"
  30 #include "llvm/CodeGen/FastISel.h"
  31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
  32 #include "llvm/CodeGen/MachineInstrBuilder.h"
  33 #include "llvm/CodeGen/MachineModuleInfo.h"
  34 #include "llvm/CodeGen/MachineConstantPool.h"
  35 #include "llvm/CodeGen/MachineFrameInfo.h"
  36 #include "llvm/CodeGen/MachineMemOperand.h"
  37 #include "llvm/CodeGen/MachineRegisterInfo.h"
  38 #include "llvm/CodeGen/PseudoSourceValue.h"
  39 #include "llvm/Support/CallSite.h"
  40 #include "llvm/Support/CommandLine.h"
  41 #include "llvm/Support/ErrorHandling.h"
  42 #include "llvm/Support/GetElementPtrTypeIterator.h"
  43 #include "llvm/Target/TargetData.h"
  44 #include "llvm/Target/TargetInstrInfo.h"
  45 #include "llvm/Target/TargetLowering.h"
  46 #include "llvm/Target/TargetMachine.h"
  47 #include "llvm/Target/TargetOptions.h"
  48 using namespace llvm;
  49
  50 static cl::opt<bool>
  51 DisableARMFastISel("disable-arm-fast-isel",
  52                     cl::desc("Turn off experimental ARM fast-isel support"),
  53                     cl::init(false), cl::Hidden);
  54
  55 namespace {
  56
  57 class ARMFastISel : public FastISel {
  58
  59   /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
  60   /// make the right decision when generating code for different targets.
  61   const ARMSubtarget *Subtarget;
  62   const TargetMachine &TM;
  63   const TargetInstrInfo &TII;
  64   const TargetLowering &TLI;
  65   ARMFunctionInfo *AFI;
  66
  67   // Convenience variables to avoid some queries.
  68   bool isThumb;
  69   LLVMContext *Context;
  70
  71   public:
  72     explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
  73     : FastISel(funcInfo),
  74       TM(funcInfo.MF->getTarget()),
  75       TII(*TM.getInstrInfo()),
  76       TLI(*TM.getTargetLowering()) {
  77       Subtarget = &TM.getSubtarget<ARMSubtarget>();
  78       AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
  79       isThumb = AFI->isThumbFunction();
  80       Context = &funcInfo.Fn->getContext();
  81     }
  82
  83     // Code from FastISel.cpp.
  84     virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
  85                                    const TargetRegisterClass *RC);
  86     virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
  87                                     const TargetRegisterClass *RC,
  88                                     unsigned Op0, bool Op0IsKill);
  89     virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
  90                                      const TargetRegisterClass *RC,
  91                                      unsigned Op0, bool Op0IsKill,
  92                                      unsigned Op1, bool Op1IsKill);
  93     virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
  94                                      const TargetRegisterClass *RC,
  95                                      unsigned Op0, bool Op0IsKill,
  96                                      uint64_t Imm);
  97     virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
  98                                      const TargetRegisterClass *RC,
  99                                      unsigned Op0, bool Op0IsKill,
 100                                      const ConstantFP *FPImm);
 101     virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
 102                                     const TargetRegisterClass *RC,
 103                                     uint64_t Imm);
 104     virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
 105                                       const TargetRegisterClass *RC,
 106                                       unsigned Op0, bool Op0IsKill,
 107                                       unsigned Op1, bool Op1IsKill,
 108                                       uint64_t Imm);
 109     virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
 110                                                 unsigned Op0, bool Op0IsKill,
 111                                                 uint32_t Idx);
 112
 113     // Backend specific FastISel code.
 114     virtual bool TargetSelectInstruction(const Instruction *I);
 115     virtual unsigned TargetMaterializeConstant(const Constant *C);
 116     virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
 117
 118   #include "ARMGenFastISel.inc"
 119
 120     // Instruction selection routines.
 121   private:
 122     bool SelectLoad(const Instruction *I);
 123     bool SelectStore(const Instruction *I);
 124     bool SelectBranch(const Instruction *I);
 125     bool SelectCmp(const Instruction *I);
 126     bool SelectFPExt(const Instruction *I);
 127     bool SelectFPTrunc(const Instruction *I);
 128     bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
 129     bool SelectSIToFP(const Instruction *I);
 130     bool SelectFPToSI(const Instruction *I);
 131     bool SelectSDiv(const Instruction *I);
 132     bool SelectSRem(const Instruction *I);
 133     bool SelectCall(const Instruction *I);
 134     bool SelectSelect(const Instruction *I);
 135     bool SelectRet(const Instruction *I);
 136
 137     // Utility routines.
 138   private:
 139     bool isTypeLegal(const Type *Ty, MVT &VT);
 140     bool isLoadTypeLegal(const Type *Ty, MVT &VT);
 141     bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Base, int Offset);
 142     bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Base, int Offset);
 143     bool ARMComputeRegOffset(const Value *Obj, unsigned &Base, int &Offset);
 144     void ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT);
 145     unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
 146     unsigned ARMMaterializeInt(const Constant *C, EVT VT);
 147     unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
 148     unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
 149     unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
 150
 151     // Call handling routines.
 152   private:
 153     bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
 154                         unsigned &ResultReg);
 155     CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
 156     bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
 157                          SmallVectorImpl<unsigned> &ArgRegs,
 158                          SmallVectorImpl<MVT> &ArgVTs,
 159                          SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
 160                          SmallVectorImpl<unsigned> &RegArgs,
 161                          CallingConv::ID CC,
 162                          unsigned &NumBytes);
 163     bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
 164                     const Instruction *I, CallingConv::ID CC,
 165                     unsigned &NumBytes);
 166     bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
 167
 168     // OptionalDef handling routines.
 169   private:
 170     bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
 171     const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
 172 };
 173
 174 } // end anonymous namespace
 175
 176 #include "ARMGenCallingConv.inc"
 177
 178 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
 179 // we don't care about implicit defs here, just places we'll need to add a
 180 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
 181 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
 182   const TargetInstrDesc &TID = MI->getDesc();
 183   if (!TID.hasOptionalDef())
 184     return false;
 185
 186   // Look to see if our OptionalDef is defining CPSR or CCR.
 187   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 188     const MachineOperand &MO = MI->getOperand(i);
 189     if (!MO.isReg() || !MO.isDef()) continue;
 190     if (MO.getReg() == ARM::CPSR)
 191       *CPSR = true;
 192   }
 193   return true;
 194 }
 195
 196 // If the machine is predicable go ahead and add the predicate operands, if
 197 // it needs default CC operands add those.
 198 // TODO: If we want to support thumb1 then we'll need to deal with optional
 199 // CPSR defs that need to be added before the remaining operands. See s_cc_out
 200 // for descriptions why.
 201 const MachineInstrBuilder &
 202 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
 203   MachineInstr *MI = &*MIB;
 204
 205   // Do we use a predicate?
 206   if (TII.isPredicable(MI))
 207     AddDefaultPred(MIB);
 208
 209   // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
 210   // defines CPSR. All other OptionalDefines in ARM are the CCR register.
 211   bool CPSR = false;
 212   if (DefinesOptionalPredicate(MI, &CPSR)) {
 213     if (CPSR)
 214       AddDefaultT1CC(MIB);
 215     else
 216       AddDefaultCC(MIB);
 217   }
 218   return MIB;
 219 }
 220
 221 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
 222                                     const TargetRegisterClass* RC) {
 223   unsigned ResultReg = createResultReg(RC);
 224   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 225
 226   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
 227   return ResultReg;
 228 }
 229
 230 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
 231                                      const TargetRegisterClass *RC,
 232                                      unsigned Op0, bool Op0IsKill) {
 233   unsigned ResultReg = createResultReg(RC);
 234   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 235
 236   if (II.getNumDefs() >= 1)
 237     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
 238                    .addReg(Op0, Op0IsKill * RegState::Kill));
 239   else {
 240     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
 241                    .addReg(Op0, Op0IsKill * RegState::Kill));
 242     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 243                    TII.get(TargetOpcode::COPY), ResultReg)
 244                    .addReg(II.ImplicitDefs[0]));
 245   }
 246   return ResultReg;
 247 }
 248
 249 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
 250                                       const TargetRegisterClass *RC,
 251                                       unsigned Op0, bool Op0IsKill,
 252                                       unsigned Op1, bool Op1IsKill) {
 253   unsigned ResultReg = createResultReg(RC);
 254   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 255
 256   if (II.getNumDefs() >= 1)
 257     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
 258                    .addReg(Op0, Op0IsKill * RegState::Kill)
 259                    .addReg(Op1, Op1IsKill * RegState::Kill));
 260   else {
 261     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
 262                    .addReg(Op0, Op0IsKill * RegState::Kill)
 263                    .addReg(Op1, Op1IsKill * RegState::Kill));
 264     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 265                            TII.get(TargetOpcode::COPY), ResultReg)
 266                    .addReg(II.ImplicitDefs[0]));
 267   }
 268   return ResultReg;
 269 }
 270
 271 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
 272                                       const TargetRegisterClass *RC,
 273                                       unsigned Op0, bool Op0IsKill,
 274                                       uint64_t Imm) {
 275   unsigned ResultReg = createResultReg(RC);
 276   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 277
 278   if (II.getNumDefs() >= 1)
 279     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
 280                    .addReg(Op0, Op0IsKill * RegState::Kill)
 281                    .addImm(Imm));
 282   else {
 283     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
 284                    .addReg(Op0, Op0IsKill * RegState::Kill)
 285                    .addImm(Imm));
 286     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 287                            TII.get(TargetOpcode::COPY), ResultReg)
 288                    .addReg(II.ImplicitDefs[0]));
 289   }
 290   return ResultReg;
 291 }
 292
 293 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
 294                                       const TargetRegisterClass *RC,
 295                                       unsigned Op0, bool Op0IsKill,
 296                                       const ConstantFP *FPImm) {
 297   unsigned ResultReg = createResultReg(RC);
 298   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 299
 300   if (II.getNumDefs() >= 1)
 301     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
 302                    .addReg(Op0, Op0IsKill * RegState::Kill)
 303                    .addFPImm(FPImm));
 304   else {
 305     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
 306                    .addReg(Op0, Op0IsKill * RegState::Kill)
 307                    .addFPImm(FPImm));
 308     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 309                            TII.get(TargetOpcode::COPY), ResultReg)
 310                    .addReg(II.ImplicitDefs[0]));
 311   }
 312   return ResultReg;
 313 }
 314
 315 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
 316                                        const TargetRegisterClass *RC,
 317                                        unsigned Op0, bool Op0IsKill,
 318                                        unsigned Op1, bool Op1IsKill,
 319                                        uint64_t Imm) {
 320   unsigned ResultReg = createResultReg(RC);
 321   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 322
 323   if (II.getNumDefs() >= 1)
 324     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
 325                    .addReg(Op0, Op0IsKill * RegState::Kill)
 326                    .addReg(Op1, Op1IsKill * RegState::Kill)
 327                    .addImm(Imm));
 328   else {
 329     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
 330                    .addReg(Op0, Op0IsKill * RegState::Kill)
 331                    .addReg(Op1, Op1IsKill * RegState::Kill)
 332                    .addImm(Imm));
 333     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 334                            TII.get(TargetOpcode::COPY), ResultReg)
 335                    .addReg(II.ImplicitDefs[0]));
 336   }
 337   return ResultReg;
 338 }
 339
 340 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
 341                                      const TargetRegisterClass *RC,
 342                                      uint64_t Imm) {
 343   unsigned ResultReg = createResultReg(RC);
 344   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 345
 346   if (II.getNumDefs() >= 1)
 347     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
 348                    .addImm(Imm));
 349   else {
 350     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
 351                    .addImm(Imm));
 352     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 353                            TII.get(TargetOpcode::COPY), ResultReg)
 354                    .addReg(II.ImplicitDefs[0]));
 355   }
 356   return ResultReg;
 357 }
 358
 359 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
 360                                                  unsigned Op0, bool Op0IsKill,
 361                                                  uint32_t Idx) {
 362   unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
 363   assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
 364          "Cannot yet extract from physregs");
 365   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
 366                          DL, TII.get(TargetOpcode::COPY), ResultReg)
 367                  .addReg(Op0, getKillRegState(Op0IsKill), Idx));
 368   return ResultReg;
 369 }
 370
 371 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
 372 // checks from the various callers.
 373 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
 374   if (VT == MVT::f64) return 0;
 375
 376   unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
 377   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 378                           TII.get(ARM::VMOVRS), MoveReg)
 379                   .addReg(SrcReg));
 380   return MoveReg;
 381 }
 382
 383 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
 384   if (VT == MVT::i64) return 0;
 385
 386   unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
 387   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 388                           TII.get(ARM::VMOVSR), MoveReg)
 389                   .addReg(SrcReg));
 390   return MoveReg;
 391 }
 392
 393 // For double width floating point we need to materialize two constants
 394 // (the high and the low) into integer registers then use a move to get
 395 // the combined constant into an FP reg.
 396 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
 397   const APFloat Val = CFP->getValueAPF();
 398   bool is64bit = VT == MVT::f64;
 399
 400   // This checks to see if we can use VFP3 instructions to materialize
 401   // a constant, otherwise we have to go through the constant pool.
 402   if (TLI.isFPImmLegal(Val, VT)) {
 403     unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
 404     unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
 405     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
 406                             DestReg)
 407                     .addFPImm(CFP));
 408     return DestReg;
 409   }
 410
 411   // Require VFP2 for loading fp constants.
 412   if (!Subtarget->hasVFP2()) return false;
 413
 414   // MachineConstantPool wants an explicit alignment.
 415   unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
 416   if (Align == 0) {
 417     // TODO: Figure out if this is correct.
 418     Align = TD.getTypeAllocSize(CFP->getType());
 419   }
 420   unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
 421   unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
 422   unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
 423
 424   // The extra reg is for addrmode5.
 425   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
 426                           DestReg)
 427                   .addConstantPoolIndex(Idx)
 428                   .addReg(0));
 429   return DestReg;
 430 }
 431
 432 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
 433
 434   // For now 32-bit only.
 435   if (VT != MVT::i32) return false;
 436
 437   unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
 438
 439   // If we can do this in a single instruction without a constant pool entry
 440   // do so now.
 441   const ConstantInt *CI = cast<ConstantInt>(C);
 442   if (isUInt<16>(CI->getSExtValue())) {
 443     unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
 444     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 445                             TII.get(Opc), DestReg)
 446                     .addImm(CI->getSExtValue()));
 447     return DestReg;
 448   }
 449
 450   // MachineConstantPool wants an explicit alignment.
 451   unsigned Align = TD.getPrefTypeAlignment(C->getType());
 452   if (Align == 0) {
 453     // TODO: Figure out if this is correct.
 454     Align = TD.getTypeAllocSize(C->getType());
 455   }
 456   unsigned Idx = MCP.getConstantPoolIndex(C, Align);
 457
 458   if (isThumb)
 459     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 460                             TII.get(ARM::t2LDRpci), DestReg)
 461                     .addConstantPoolIndex(Idx));
 462   else
 463     // The extra reg and immediate are for addrmode2.
 464     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 465                             TII.get(ARM::LDRcp), DestReg)
 466                     .addConstantPoolIndex(Idx)
 467                     .addImm(0));
 468
 469   return DestReg;
 470 }
 471
 472 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
 473   // For now 32-bit only.
 474   if (VT != MVT::i32) return 0;
 475
 476   Reloc::Model RelocM = TM.getRelocationModel();
 477
 478   // TODO: No external globals for now.
 479   if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
 480
 481   // TODO: Need more magic for ARM PIC.
 482   if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
 483
 484   // MachineConstantPool wants an explicit alignment.
 485   unsigned Align = TD.getPrefTypeAlignment(GV->getType());
 486   if (Align == 0) {
 487     // TODO: Figure out if this is correct.
 488     Align = TD.getTypeAllocSize(GV->getType());
 489   }
 490
 491   // Grab index.
 492   unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
 493   unsigned Id = AFI->createConstPoolEntryUId();
 494   ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
 495                                                        ARMCP::CPValue, PCAdj);
 496   unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
 497
 498   // Load value.
 499   MachineInstrBuilder MIB;
 500   unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
 501   if (isThumb) {
 502     unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
 503     MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
 504           .addConstantPoolIndex(Idx);
 505     if (RelocM == Reloc::PIC_)
 506       MIB.addImm(Id);
 507   } else {
 508     // The extra reg and immediate are for addrmode2.
 509     MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
 510                   DestReg)
 511           .addConstantPoolIndex(Idx)
 512           .addReg(0).addImm(0);
 513   }
 514   AddOptionalDefs(MIB);
 515   return DestReg;
 516 }
 517
 518 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
 519   EVT VT = TLI.getValueType(C->getType(), true);
 520
 521   // Only handle simple types.
 522   if (!VT.isSimple()) return 0;
 523
 524   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
 525     return ARMMaterializeFP(CFP, VT);
 526   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
 527     return ARMMaterializeGV(GV, VT);
 528   else if (isa<ConstantInt>(C))
 529     return ARMMaterializeInt(C, VT);
 530
 531   return 0;
 532 }
 533
 534 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
 535   // Don't handle dynamic allocas.
 536   if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
 537
 538   MVT VT;
 539   if (!isLoadTypeLegal(AI->getType(), VT)) return false;
 540
 541   DenseMap<const AllocaInst*, int>::iterator SI =
 542     FuncInfo.StaticAllocaMap.find(AI);
 543
 544   // This will get lowered later into the correct offsets and registers
 545   // via rewriteXFrameIndex.
 546   if (SI != FuncInfo.StaticAllocaMap.end()) {
 547     TargetRegisterClass* RC = TLI.getRegClassFor(VT);
 548     unsigned ResultReg = createResultReg(RC);
 549     unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
 550     AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
 551                             TII.get(Opc), ResultReg)
 552                             .addFrameIndex(SI->second)
 553                             .addImm(0));
 554     return ResultReg;
 555   }
 556
 557   return 0;
 558 }
 559
 560 bool ARMFastISel::isTypeLegal(const Type *Ty, MVT &VT) {
 561   EVT evt = TLI.getValueType(Ty, true);
 562
 563   // Only handle simple types.
 564   if (evt == MVT::Other || !evt.isSimple()) return false;
 565   VT = evt.getSimpleVT();
 566
 567   // Handle all legal types, i.e. a register that will directly hold this
 568   // value.
 569   return TLI.isTypeLegal(VT);
 570 }
 571
 572 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, MVT &VT) {
 573   if (isTypeLegal(Ty, VT)) return true;
 574
 575   // If this is a type than can be sign or zero-extended to a basic operation
 576   // go ahead and accept it now.
 577   if (VT == MVT::i8 || VT == MVT::i16)
 578     return true;
 579
 580   return false;
 581 }
 582
 583 // Computes the Reg+Offset to get to an object.
 584 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
 585                                       int &Offset) {
 586   // Some boilerplate from the X86 FastISel.
 587   const User *U = NULL;
 588   unsigned Opcode = Instruction::UserOp1;
 589   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
 590     // Don't walk into other basic blocks; it's possible we haven't
 591     // visited them yet, so the instructions may not yet be assigned
 592     // virtual registers.
 593     if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
 594       return false;
 595     Opcode = I->getOpcode();
 596     U = I;
 597   } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
 598     Opcode = C->getOpcode();
 599     U = C;
 600   }
 601
 602   if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
 603     if (Ty->getAddressSpace() > 255)
 604       // Fast instruction selection doesn't support the special
 605       // address spaces.
 606       return false;
 607
 608   switch (Opcode) {
 609     default:
 610     break;
 611     case Instruction::BitCast: {
 612       // Look through bitcasts.
 613       return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
 614     }
 615     case Instruction::IntToPtr: {
 616       // Look past no-op inttoptrs.
 617       if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
 618         return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
 619       break;
 620     }
 621     case Instruction::PtrToInt: {
 622       // Look past no-op ptrtoints.
 623       if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
 624         return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
 625       break;
 626     }
 627     case Instruction::GetElementPtr: {
 628       int SavedOffset = Offset;
 629       unsigned SavedBase = Base;
 630       int TmpOffset = Offset;
 631
 632       // Iterate through the GEP folding the constants into offsets where
 633       // we can.
 634       gep_type_iterator GTI = gep_type_begin(U);
 635       for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
 636            i != e; ++i, ++GTI) {
 637         const Value *Op = *i;
 638         if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
 639           const StructLayout *SL = TD.getStructLayout(STy);
 640           unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
 641           TmpOffset += SL->getElementOffset(Idx);
 642         } else {
 643           uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
 644           SmallVector<const Value *, 4> Worklist;
 645           Worklist.push_back(Op);
 646           do {
 647             Op = Worklist.pop_back_val();
 648             if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
 649               // Constant-offset addressing.
 650               TmpOffset += CI->getSExtValue() * S;
 651             } else if (isa<AddOperator>(Op) &&
 652                        isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
 653               // An add with a constant operand. Fold the constant.
 654               ConstantInt *CI =
 655                 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
 656               TmpOffset += CI->getSExtValue() * S;
 657               // Add the other operand back to the work list.
 658               Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
 659             } else
 660               goto unsupported_gep;
 661           } while (!Worklist.empty());
 662         }
 663       }
 664
 665       // Try to grab the base operand now.
 666       Offset = TmpOffset;
 667       if (ARMComputeRegOffset(U->getOperand(0), Base, Offset)) return true;
 668
 669       // We failed, restore everything and try the other options.
 670       Offset = SavedOffset;
 671       Base = SavedBase;
 672
 673       unsupported_gep:
 674       break;
 675     }
 676     case Instruction::Alloca: {
 677       const AllocaInst *AI = cast<AllocaInst>(Obj);
 678       unsigned Reg = TargetMaterializeAlloca(AI);
 679
 680       if (Reg == 0) return false;
 681
 682       Base = Reg;
 683       return true;
 684     }
 685   }
 686
 687   // Materialize the global variable's address into a reg which can
 688   // then be used later to load the variable.
 689   if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
 690     unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
 691     if (Tmp == 0) return false;
 692
 693     Base = Tmp;
 694     return true;
 695   }
 696
 697   // Try to get this in a register if nothing else has worked.
 698   if (Base == 0) Base = getRegForValue(Obj);
 699   return Base != 0;
 700 }
 701
 702 void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
 703
 704   assert(VT.isSimple() && "Non-simple types are invalid here!");
 705
 706   bool needsLowering = false;
 707   switch (VT.getSimpleVT().SimpleTy) {
 708     default:
 709       assert(false && "Unhandled load/store type!");
 710     case MVT::i1:
 711     case MVT::i8:
 712     case MVT::i16:
 713     case MVT::i32:
 714       // Integer loads/stores handle 12-bit offsets.
 715       needsLowering = ((Offset & 0xfff) != Offset);
 716       break;
 717     case MVT::f32:
 718     case MVT::f64:
 719       // Floating point operands handle 8-bit offsets.
 720       needsLowering = ((Offset & 0xff) != Offset);
 721       break;
 722   }
 723
 724   // Since the offset is too large for the load/store instruction
 725   // get the reg+offset into a register.
 726   if (needsLowering) {
 727     ARMCC::CondCodes Pred = ARMCC::AL;
 728     unsigned PredReg = 0;
 729
 730     TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
 731       ARM::GPRRegisterClass;
 732     unsigned BaseReg = createResultReg(RC);
 733
 734     if (!isThumb)
 735       emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 736                               BaseReg, Base, Offset, Pred, PredReg,
 737                               static_cast<const ARMBaseInstrInfo&>(TII));
 738     else {
 739       assert(AFI->isThumb2Function());
 740       emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 741                              BaseReg, Base, Offset, Pred, PredReg,
 742                              static_cast<const ARMBaseInstrInfo&>(TII));
 743     }
 744     Offset = 0;
 745     Base = BaseReg;
 746   }
 747 }
 748
 749 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
 750                               unsigned Base, int Offset) {
 751
 752   assert(VT.isSimple() && "Non-simple types are invalid here!");
 753   unsigned Opc;
 754   TargetRegisterClass *RC;
 755   bool isFloat = false;
 756   switch (VT.getSimpleVT().SimpleTy) {
 757     default:
 758       // This is mostly going to be Neon/vector support.
 759       return false;
 760     case MVT::i16:
 761       Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
 762       RC = ARM::GPRRegisterClass;
 763       break;
 764     case MVT::i8:
 765       Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
 766       RC = ARM::GPRRegisterClass;
 767       break;
 768     case MVT::i32:
 769       Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
 770       RC = ARM::GPRRegisterClass;
 771       break;
 772     case MVT::f32:
 773       Opc = ARM::VLDRS;
 774       RC = TLI.getRegClassFor(VT);
 775       isFloat = true;
 776       break;
 777     case MVT::f64:
 778       Opc = ARM::VLDRD;
 779       RC = TLI.getRegClassFor(VT);
 780       isFloat = true;
 781       break;
 782   }
 783
 784   ResultReg = createResultReg(RC);
 785
 786   ARMSimplifyRegOffset(Base, Offset, VT);
 787
 788   // addrmode5 output depends on the selection dag addressing dividing the
 789   // offset by 4 that it then later multiplies. Do this here as well.
 790   if (isFloat)
 791     Offset /= 4;
 792
 793   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 794                           TII.get(Opc), ResultReg)
 795                   .addReg(Base).addImm(Offset));
 796   return true;
 797 }
 798
 799 bool ARMFastISel::SelectLoad(const Instruction *I) {
 800   // Verify we have a legal type before going any further.
 801   MVT VT;
 802   if (!isLoadTypeLegal(I->getType(), VT))
 803     return false;
 804
 805   // Our register and offset with innocuous defaults.
 806   unsigned Base = 0;
 807   int Offset = 0;
 808
 809   // See if we can handle this as Reg + Offset
 810   if (!ARMComputeRegOffset(I->getOperand(0), Base, Offset))
 811     return false;
 812
 813   unsigned ResultReg;
 814   if (!ARMEmitLoad(VT, ResultReg, Base, Offset)) return false;
 815
 816   UpdateValueMap(I, ResultReg);
 817   return true;
 818 }
 819
 820 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
 821                                unsigned Base, int Offset) {
 822   unsigned StrOpc;
 823   bool isFloat = false;
 824   bool needReg0Op = false;
 825   switch (VT.getSimpleVT().SimpleTy) {
 826     default: return false;
 827     case MVT::i1: {
 828       unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
 829                                                ARM::GPRRegisterClass);
 830       unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
 831       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 832                               TII.get(Opc), Res)
 833                       .addReg(SrcReg).addImm(1));
 834       SrcReg = Res;
 835     } // Fallthrough here.
 836     case MVT::i8:
 837       StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
 838       break;
 839     case MVT::i16:
 840       StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
 841       needReg0Op = true;
 842       break;
 843     case MVT::i32:
 844       StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
 845       break;
 846     case MVT::f32:
 847       if (!Subtarget->hasVFP2()) return false;
 848       StrOpc = ARM::VSTRS;
 849       isFloat = true;
 850       break;
 851     case MVT::f64:
 852       if (!Subtarget->hasVFP2()) return false;
 853       StrOpc = ARM::VSTRD;
 854       isFloat = true;
 855       break;
 856   }
 857
 858   ARMSimplifyRegOffset(Base, Offset, VT);
 859
 860   // addrmode5 output depends on the selection dag addressing dividing the
 861   // offset by 4 that it then later multiplies. Do this here as well.
 862   if (isFloat)
 863     Offset /= 4;
 864
 865   // FIXME: The 'needReg0Op' bit goes away once STRH is converted to
 866   // not use the mega-addrmode stuff.
 867   if (!needReg0Op)
 868     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 869                             TII.get(StrOpc))
 870                     .addReg(SrcReg).addReg(Base).addImm(Offset));
 871   else
 872     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
 873                             TII.get(StrOpc))
 874                     .addReg(SrcReg).addReg(Base).addReg(0).addImm(Offset));
 875
 876   return true;
 877 }
 878
 879 bool ARMFastISel::SelectStore(const Instruction *I) {
 880   Value *Op0 = I->getOperand(0);
 881   unsigned SrcReg = 0;
 882
 883   // Yay type legalization
 884   MVT VT;
 885   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
 886     return false;
 887
 888   // Get the value to be stored into a register.
 889   SrcReg = getRegForValue(Op0);
 890   if (SrcReg == 0)
 891     return false;
 892
 893   // Our register and offset with innocuous defaults.
 894   unsigned Base = 0;
 895   int Offset = 0;
 896
 897   // See if we can handle this as Reg + Offset
 898   if (!ARMComputeRegOffset(I->getOperand(1), Base, Offset))
 899     return false;
 900
 901   if (!ARMEmitStore(VT, SrcReg, Base, Offset)) return false;
 902
 903   return true;
 904 }
 905
 906 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
 907   switch (Pred) {
 908     // Needs two compares...
 909     case CmpInst::FCMP_ONE:
 910     case CmpInst::FCMP_UEQ:
 911     default:
 912       // AL is our "false" for now. The other two need more compares.
 913       return ARMCC::AL;
 914     case CmpInst::ICMP_EQ:
 915     case CmpInst::FCMP_OEQ:
 916       return ARMCC::EQ;
 917     case CmpInst::ICMP_SGT:
 918     case CmpInst::FCMP_OGT:
 919       return ARMCC::GT;
 920     case CmpInst::ICMP_SGE:
 921     case CmpInst::FCMP_OGE:
 922       return ARMCC::GE;
 923     case CmpInst::ICMP_UGT:
 924     case CmpInst::FCMP_UGT:
 925       return ARMCC::HI;
 926     case CmpInst::FCMP_OLT:
 927       return ARMCC::MI;
 928     case CmpInst::ICMP_ULE:
 929     case CmpInst::FCMP_OLE:
 930       return ARMCC::LS;
 931     case CmpInst::FCMP_ORD:
 932       return ARMCC::VC;
 933     case CmpInst::FCMP_UNO:
 934       return ARMCC::VS;
 935     case CmpInst::FCMP_UGE:
 936       return ARMCC::PL;
 937     case CmpInst::ICMP_SLT:
 938     case CmpInst::FCMP_ULT:
 939       return ARMCC::LT;
 940     case CmpInst::ICMP_SLE:
 941     case CmpInst::FCMP_ULE:
 942       return ARMCC::LE;
 943     case CmpInst::FCMP_UNE:
 944     case CmpInst::ICMP_NE:
 945       return ARMCC::NE;
 946     case CmpInst::ICMP_UGE:
 947       return ARMCC::HS;
 948     case CmpInst::ICMP_ULT:
 949       return ARMCC::LO;
 950   }
 951 }
 952
 953 bool ARMFastISel::SelectBranch(const Instruction *I) {
 954   const BranchInst *BI = cast<BranchInst>(I);
 955   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
 956   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
 957
 958   // Simple branch support.
 959
 960   // If we can, avoid recomputing the compare - redoing it could lead to wonky
 961   // behavior.
 962   // TODO: Factor this out.
 963   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
 964     if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
 965       MVT VT;
 966       const Type *Ty = CI->getOperand(0)->getType();
 967       if (!isTypeLegal(Ty, VT))
 968         return false;
 969
 970       bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
 971       if (isFloat && !Subtarget->hasVFP2())
 972         return false;
 973
 974       unsigned CmpOpc;
 975       unsigned CondReg;
 976       switch (VT.SimpleTy) {
 977         default: return false;
 978         // TODO: Verify compares.
 979         case MVT::f32:
 980           CmpOpc = ARM::VCMPES;
 981           CondReg = ARM::FPSCR;
 982           break;
 983         case MVT::f64:
 984           CmpOpc = ARM::VCMPED;
 985           CondReg = ARM::FPSCR;
 986           break;
 987         case MVT::i32:
 988           CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
 989           CondReg = ARM::CPSR;
 990           break;
 991       }
 992
 993       // Get the compare predicate.
 994       ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
 995
 996       // We may not handle every CC for now.
 997       if (ARMPred == ARMCC::AL) return false;
 998
 999       unsigned Arg1 = getRegForValue(CI->getOperand(0));
1000       if (Arg1 == 0) return false;
1001
1002       unsigned Arg2 = getRegForValue(CI->getOperand(1));
1003       if (Arg2 == 0) return false;
1004
1005       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1006                               TII.get(CmpOpc))
1007                       .addReg(Arg1).addReg(Arg2));
1008
1009       // For floating point we need to move the result to a comparison register
1010       // that we can then use for branches.
1011       if (isFloat)
1012         AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1013                                 TII.get(ARM::FMSTAT)));
1014
1015       unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1016       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1017       .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1018       FastEmitBranch(FBB, DL);
1019       FuncInfo.MBB->addSuccessor(TBB);
1020       return true;
1021     }
1022   }
1023
1024   unsigned CmpReg = getRegForValue(BI->getCondition());
1025   if (CmpReg == 0) return false;
1026
1027   // Re-set the flags just in case.
1028   unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
1029   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1030                   .addReg(CmpReg).addImm(0));
1031
1032   unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1033   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1034                   .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
1035   FastEmitBranch(FBB, DL);
1036   FuncInfo.MBB->addSuccessor(TBB);
1037   return true;
1038 }
1039
1040 bool ARMFastISel::SelectCmp(const Instruction *I) {
1041   const CmpInst *CI = cast<CmpInst>(I);
1042
1043   MVT VT;
1044   const Type *Ty = CI->getOperand(0)->getType();
1045   if (!isTypeLegal(Ty, VT))
1046     return false;
1047
1048   bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1049   if (isFloat && !Subtarget->hasVFP2())
1050     return false;
1051
1052   unsigned CmpOpc;
1053   unsigned CondReg;
1054   switch (VT.SimpleTy) {
1055     default: return false;
1056     // TODO: Verify compares.
1057     case MVT::f32:
1058       CmpOpc = ARM::VCMPES;
1059       CondReg = ARM::FPSCR;
1060       break;
1061     case MVT::f64:
1062       CmpOpc = ARM::VCMPED;
1063       CondReg = ARM::FPSCR;
1064       break;
1065     case MVT::i32:
1066       CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1067       CondReg = ARM::CPSR;
1068       break;
1069   }
1070
1071   // Get the compare predicate.
1072   ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1073
1074   // We may not handle every CC for now.
1075   if (ARMPred == ARMCC::AL) return false;
1076
1077   unsigned Arg1 = getRegForValue(CI->getOperand(0));
1078   if (Arg1 == 0) return false;
1079
1080   unsigned Arg2 = getRegForValue(CI->getOperand(1));
1081   if (Arg2 == 0) return false;
1082
1083   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1084                   .addReg(Arg1).addReg(Arg2));
1085
1086   // For floating point we need to move the result to a comparison register
1087   // that we can then use for branches.
1088   if (isFloat)
1089     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1090                             TII.get(ARM::FMSTAT)));
1091
1092   // Now set a register based on the comparison. Explicitly set the predicates
1093   // here.
1094   unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1095   TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1096                                     : ARM::GPRRegisterClass;
1097   unsigned DestReg = createResultReg(RC);
1098   Constant *Zero
1099     = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1100   unsigned ZeroReg = TargetMaterializeConstant(Zero);
1101   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1102           .addReg(ZeroReg).addImm(1)
1103           .addImm(ARMPred).addReg(CondReg);
1104
1105   UpdateValueMap(I, DestReg);
1106   return true;
1107 }
1108
1109 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1110   // Make sure we have VFP and that we're extending float to double.
1111   if (!Subtarget->hasVFP2()) return false;
1112
1113   Value *V = I->getOperand(0);
1114   if (!I->getType()->isDoubleTy() ||
1115       !V->getType()->isFloatTy()) return false;
1116
1117   unsigned Op = getRegForValue(V);
1118   if (Op == 0) return false;
1119
1120   unsigned Result = createResultReg(ARM::DPRRegisterClass);
1121   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1122                           TII.get(ARM::VCVTDS), Result)
1123                   .addReg(Op));
1124   UpdateValueMap(I, Result);
1125   return true;
1126 }
1127
1128 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1129   // Make sure we have VFP and that we're truncating double to float.
1130   if (!Subtarget->hasVFP2()) return false;
1131
1132   Value *V = I->getOperand(0);
1133   if (!(I->getType()->isFloatTy() &&
1134         V->getType()->isDoubleTy())) return false;
1135
1136   unsigned Op = getRegForValue(V);
1137   if (Op == 0) return false;
1138
1139   unsigned Result = createResultReg(ARM::SPRRegisterClass);
1140   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1141                           TII.get(ARM::VCVTSD), Result)
1142                   .addReg(Op));
1143   UpdateValueMap(I, Result);
1144   return true;
1145 }
1146
1147 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1148   // Make sure we have VFP.
1149   if (!Subtarget->hasVFP2()) return false;
1150
1151   MVT DstVT;
1152   const Type *Ty = I->getType();
1153   if (!isTypeLegal(Ty, DstVT))
1154     return false;
1155
1156   unsigned Op = getRegForValue(I->getOperand(0));
1157   if (Op == 0) return false;
1158
1159   // The conversion routine works on fp-reg to fp-reg and the operand above
1160   // was an integer, move it to the fp registers if possible.
1161   unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1162   if (FP == 0) return false;
1163
1164   unsigned Opc;
1165   if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1166   else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1167   else return 0;
1168
1169   unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1170   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1171                           ResultReg)
1172                   .addReg(FP));
1173   UpdateValueMap(I, ResultReg);
1174   return true;
1175 }
1176
1177 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1178   // Make sure we have VFP.
1179   if (!Subtarget->hasVFP2()) return false;
1180
1181   MVT DstVT;
1182   const Type *RetTy = I->getType();
1183   if (!isTypeLegal(RetTy, DstVT))
1184     return false;
1185
1186   unsigned Op = getRegForValue(I->getOperand(0));
1187   if (Op == 0) return false;
1188
1189   unsigned Opc;
1190   const Type *OpTy = I->getOperand(0)->getType();
1191   if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1192   else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1193   else return 0;
1194
1195   // f64->s32 or f32->s32 both need an intermediate f32 reg.
1196   unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1197   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1198                           ResultReg)
1199                   .addReg(Op));
1200
1201   // This result needs to be in an integer register, but the conversion only
1202   // takes place in fp-regs.
1203   unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1204   if (IntReg == 0) return false;
1205
1206   UpdateValueMap(I, IntReg);
1207   return true;
1208 }
1209
1210 bool ARMFastISel::SelectSelect(const Instruction *I) {
1211   MVT VT;
1212   if (!isTypeLegal(I->getType(), VT))
1213     return false;
1214
1215   // Things need to be register sized for register moves.
1216   if (VT != MVT::i32) return false;
1217   const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1218
1219   unsigned CondReg = getRegForValue(I->getOperand(0));
1220   if (CondReg == 0) return false;
1221   unsigned Op1Reg = getRegForValue(I->getOperand(1));
1222   if (Op1Reg == 0) return false;
1223   unsigned Op2Reg = getRegForValue(I->getOperand(2));
1224   if (Op2Reg == 0) return false;
1225
1226   unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1227   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1228                   .addReg(CondReg).addImm(1));
1229   unsigned ResultReg = createResultReg(RC);
1230   unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1231   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1232     .addReg(Op1Reg).addReg(Op2Reg)
1233     .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1234   UpdateValueMap(I, ResultReg);
1235   return true;
1236 }
1237
1238 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1239   MVT VT;
1240   const Type *Ty = I->getType();
1241   if (!isTypeLegal(Ty, VT))
1242     return false;
1243
1244   // If we have integer div support we should have selected this automagically.
1245   // In case we have a real miss go ahead and return false and we'll pick
1246   // it up later.
1247   if (Subtarget->hasDivide()) return false;
1248
1249   // Otherwise emit a libcall.
1250   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1251   if (VT == MVT::i8)
1252     LC = RTLIB::SDIV_I8;
1253   else if (VT == MVT::i16)
1254     LC = RTLIB::SDIV_I16;
1255   else if (VT == MVT::i32)
1256     LC = RTLIB::SDIV_I32;
1257   else if (VT == MVT::i64)
1258     LC = RTLIB::SDIV_I64;
1259   else if (VT == MVT::i128)
1260     LC = RTLIB::SDIV_I128;
1261   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1262
1263   return ARMEmitLibcall(I, LC);
1264 }
1265
1266 bool ARMFastISel::SelectSRem(const Instruction *I) {
1267   MVT VT;
1268   const Type *Ty = I->getType();
1269   if (!isTypeLegal(Ty, VT))
1270     return false;
1271
1272   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1273   if (VT == MVT::i8)
1274     LC = RTLIB::SREM_I8;
1275   else if (VT == MVT::i16)
1276     LC = RTLIB::SREM_I16;
1277   else if (VT == MVT::i32)
1278     LC = RTLIB::SREM_I32;
1279   else if (VT == MVT::i64)
1280     LC = RTLIB::SREM_I64;
1281   else if (VT == MVT::i128)
1282     LC = RTLIB::SREM_I128;
1283   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1284
1285   return ARMEmitLibcall(I, LC);
1286 }
1287
1288 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1289   EVT VT  = TLI.getValueType(I->getType(), true);
1290
1291   // We can get here in the case when we want to use NEON for our fp
1292   // operations, but can't figure out how to. Just use the vfp instructions
1293   // if we have them.
1294   // FIXME: It'd be nice to use NEON instructions.
1295   const Type *Ty = I->getType();
1296   bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1297   if (isFloat && !Subtarget->hasVFP2())
1298     return false;
1299
1300   unsigned Op1 = getRegForValue(I->getOperand(0));
1301   if (Op1 == 0) return false;
1302
1303   unsigned Op2 = getRegForValue(I->getOperand(1));
1304   if (Op2 == 0) return false;
1305
1306   unsigned Opc;
1307   bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1308   switch (ISDOpcode) {
1309     default: return false;
1310     case ISD::FADD:
1311       Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1312       break;
1313     case ISD::FSUB:
1314       Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1315       break;
1316     case ISD::FMUL:
1317       Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1318       break;
1319   }
1320   unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1321   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1322                           TII.get(Opc), ResultReg)
1323                   .addReg(Op1).addReg(Op2));
1324   UpdateValueMap(I, ResultReg);
1325   return true;
1326 }
1327
1328 // Call Handling Code
1329
1330 bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1331                                  EVT SrcVT, unsigned &ResultReg) {
1332   unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1333                            Src, /*TODO: Kill=*/false);
1334
1335   if (RR != 0) {
1336     ResultReg = RR;
1337     return true;
1338   } else
1339     return false;
1340 }
1341
1342 // This is largely taken directly from CCAssignFnForNode - we don't support
1343 // varargs in FastISel so that part has been removed.
1344 // TODO: We may not support all of this.
1345 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1346   switch (CC) {
1347   default:
1348     llvm_unreachable("Unsupported calling convention");
1349   case CallingConv::Fast:
1350     // Ignore fastcc. Silence compiler warnings.
1351     (void)RetFastCC_ARM_APCS;
1352     (void)FastCC_ARM_APCS;
1353     // Fallthrough
1354   case CallingConv::C:
1355     // Use target triple & subtarget features to do actual dispatch.
1356     if (Subtarget->isAAPCS_ABI()) {
1357       if (Subtarget->hasVFP2() &&
1358           FloatABIType == FloatABI::Hard)
1359         return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1360       else
1361         return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1362     } else
1363         return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1364   case CallingConv::ARM_AAPCS_VFP:
1365     return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1366   case CallingConv::ARM_AAPCS:
1367     return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1368   case CallingConv::ARM_APCS:
1369     return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1370   }
1371 }
1372
1373 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1374                                   SmallVectorImpl<unsigned> &ArgRegs,
1375                                   SmallVectorImpl<MVT> &ArgVTs,
1376                                   SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1377                                   SmallVectorImpl<unsigned> &RegArgs,
1378                                   CallingConv::ID CC,
1379                                   unsigned &NumBytes) {
1380   SmallVector<CCValAssign, 16> ArgLocs;
1381   CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1382   CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1383
1384   // Get a count of how many bytes are to be pushed on the stack.
1385   NumBytes = CCInfo.getNextStackOffset();
1386
1387   // Issue CALLSEQ_START
1388   unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1389   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1390                           TII.get(AdjStackDown))
1391                   .addImm(NumBytes));
1392
1393   // Process the args.
1394   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1395     CCValAssign &VA = ArgLocs[i];
1396     unsigned Arg = ArgRegs[VA.getValNo()];
1397     MVT ArgVT = ArgVTs[VA.getValNo()];
1398
1399     // We don't handle NEON parameters yet.
1400     if (VA.getLocVT().isVector() && VA.getLocVT().getSizeInBits() > 64)
1401       return false;
1402
1403     // Handle arg promotion, etc.
1404     switch (VA.getLocInfo()) {
1405       case CCValAssign::Full: break;
1406       case CCValAssign::SExt: {
1407         bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1408                                          Arg, ArgVT, Arg);
1409         assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1410         Emitted = true;
1411         ArgVT = VA.getLocVT();
1412         break;
1413       }
1414       case CCValAssign::ZExt: {
1415         bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1416                                          Arg, ArgVT, Arg);
1417         assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1418         Emitted = true;
1419         ArgVT = VA.getLocVT();
1420         break;
1421       }
1422       case CCValAssign::AExt: {
1423         bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1424                                          Arg, ArgVT, Arg);
1425         if (!Emitted)
1426           Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1427                                       Arg, ArgVT, Arg);
1428         if (!Emitted)
1429           Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1430                                       Arg, ArgVT, Arg);
1431
1432         assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1433         ArgVT = VA.getLocVT();
1434         break;
1435       }
1436       case CCValAssign::BCvt: {
1437         unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BIT_CONVERT, Arg,
1438                                  /*TODO: Kill=*/false);
1439         assert(BC != 0 && "Failed to emit a bitcast!");
1440         Arg = BC;
1441         ArgVT = VA.getLocVT();
1442         break;
1443       }
1444       default: llvm_unreachable("Unknown arg promotion!");
1445     }
1446
1447     // Now copy/store arg to correct locations.
1448     if (VA.isRegLoc() && !VA.needsCustom()) {
1449       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1450               VA.getLocReg())
1451       .addReg(Arg);
1452       RegArgs.push_back(VA.getLocReg());
1453     } else if (VA.needsCustom()) {
1454       // TODO: We need custom lowering for vector (v2f64) args.
1455       if (VA.getLocVT() != MVT::f64) return false;
1456
1457       CCValAssign &NextVA = ArgLocs[++i];
1458
1459       // TODO: Only handle register args for now.
1460       if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1461
1462       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1463                               TII.get(ARM::VMOVRRD), VA.getLocReg())
1464                       .addReg(NextVA.getLocReg(), RegState::Define)
1465                       .addReg(Arg));
1466       RegArgs.push_back(VA.getLocReg());
1467       RegArgs.push_back(NextVA.getLocReg());
1468     } else {
1469       assert(VA.isMemLoc());
1470       // Need to store on the stack.
1471       unsigned Base = ARM::SP;
1472       int Offset = VA.getLocMemOffset();
1473
1474       if (!ARMEmitStore(ArgVT, Arg, Base, Offset)) return false;
1475     }
1476   }
1477   return true;
1478 }
1479
1480 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1481                              const Instruction *I, CallingConv::ID CC,
1482                              unsigned &NumBytes) {
1483   // Issue CALLSEQ_END
1484   unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1485   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1486                           TII.get(AdjStackUp))
1487                   .addImm(NumBytes).addImm(0));
1488
1489   // Now the return value.
1490   if (RetVT != MVT::isVoid) {
1491     SmallVector<CCValAssign, 16> RVLocs;
1492     CCState CCInfo(CC, false, TM, RVLocs, *Context);
1493     CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1494
1495     // Copy all of the result registers out of their specified physreg.
1496     if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1497       // For this move we copy into two registers and then move into the
1498       // double fp reg we want.
1499       EVT DestVT = RVLocs[0].getValVT();
1500       TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1501       unsigned ResultReg = createResultReg(DstRC);
1502       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1503                               TII.get(ARM::VMOVDRR), ResultReg)
1504                       .addReg(RVLocs[0].getLocReg())
1505                       .addReg(RVLocs[1].getLocReg()));
1506
1507       UsedRegs.push_back(RVLocs[0].getLocReg());
1508       UsedRegs.push_back(RVLocs[1].getLocReg());
1509
1510       // Finally update the result.
1511       UpdateValueMap(I, ResultReg);
1512     } else {
1513       assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1514       EVT CopyVT = RVLocs[0].getValVT();
1515       TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1516
1517       unsigned ResultReg = createResultReg(DstRC);
1518       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1519               ResultReg).addReg(RVLocs[0].getLocReg());
1520       UsedRegs.push_back(RVLocs[0].getLocReg());
1521
1522       // Finally update the result.
1523       UpdateValueMap(I, ResultReg);
1524     }
1525   }
1526
1527   return true;
1528 }
1529
1530 bool ARMFastISel::SelectRet(const Instruction *I) {
1531   const ReturnInst *Ret = cast<ReturnInst>(I);
1532   const Function &F = *I->getParent()->getParent();
1533
1534   if (!FuncInfo.CanLowerReturn)
1535     return false;
1536
1537   if (F.isVarArg())
1538     return false;
1539
1540   CallingConv::ID CC = F.getCallingConv();
1541   if (Ret->getNumOperands() > 0) {
1542     SmallVector<ISD::OutputArg, 4> Outs;
1543     GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1544                   Outs, TLI);
1545
1546     // Analyze operands of the call, assigning locations to each operand.
1547     SmallVector<CCValAssign, 16> ValLocs;
1548     CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
1549     CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1550
1551     const Value *RV = Ret->getOperand(0);
1552     unsigned Reg = getRegForValue(RV);
1553     if (Reg == 0)
1554       return false;
1555
1556     // Only handle a single return value for now.
1557     if (ValLocs.size() != 1)
1558       return false;
1559
1560     CCValAssign &VA = ValLocs[0];
1561
1562     // Don't bother handling odd stuff for now.
1563     if (VA.getLocInfo() != CCValAssign::Full)
1564       return false;
1565     // Only handle register returns for now.
1566     if (!VA.isRegLoc())
1567       return false;
1568     // TODO: For now, don't try to handle cases where getLocInfo()
1569     // says Full but the types don't match.
1570     if (VA.getValVT() != TLI.getValueType(RV->getType()))
1571       return false;
1572
1573     // Make the copy.
1574     unsigned SrcReg = Reg + VA.getValNo();
1575     unsigned DstReg = VA.getLocReg();
1576     const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1577     // Avoid a cross-class copy. This is very unlikely.
1578     if (!SrcRC->contains(DstReg))
1579       return false;
1580     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1581             DstReg).addReg(SrcReg);
1582
1583     // Mark the register as live out of the function.
1584     MRI.addLiveOut(VA.getLocReg());
1585   }
1586
1587   unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
1588   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1589                           TII.get(RetOpc)));
1590   return true;
1591 }
1592
1593 // A quick function that will emit a call for a named libcall in F with the
1594 // vector of passed arguments for the Instruction in I. We can assume that we
1595 // can emit a call for any libcall we can produce. This is an abridged version
1596 // of the full call infrastructure since we won't need to worry about things
1597 // like computed function pointers or strange arguments at call sites.
1598 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1599 // with X86.
1600 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1601   CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1602
1603   // Handle *simple* calls for now.
1604   const Type *RetTy = I->getType();
1605   MVT RetVT;
1606   if (RetTy->isVoidTy())
1607     RetVT = MVT::isVoid;
1608   else if (!isTypeLegal(RetTy, RetVT))
1609     return false;
1610
1611   // For now we're using BLX etc on the assumption that we have v5t ops.
1612   if (!Subtarget->hasV5TOps()) return false;
1613
1614   // Set up the argument vectors.
1615   SmallVector<Value*, 8> Args;
1616   SmallVector<unsigned, 8> ArgRegs;
1617   SmallVector<MVT, 8> ArgVTs;
1618   SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1619   Args.reserve(I->getNumOperands());
1620   ArgRegs.reserve(I->getNumOperands());
1621   ArgVTs.reserve(I->getNumOperands());
1622   ArgFlags.reserve(I->getNumOperands());
1623   for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1624     Value *Op = I->getOperand(i);
1625     unsigned Arg = getRegForValue(Op);
1626     if (Arg == 0) return false;
1627
1628     const Type *ArgTy = Op->getType();
1629     MVT ArgVT;
1630     if (!isTypeLegal(ArgTy, ArgVT)) return false;
1631
1632     ISD::ArgFlagsTy Flags;
1633     unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1634     Flags.setOrigAlign(OriginalAlignment);
1635
1636     Args.push_back(Op);
1637     ArgRegs.push_back(Arg);
1638     ArgVTs.push_back(ArgVT);
1639     ArgFlags.push_back(Flags);
1640   }
1641
1642   // Handle the arguments now that we've gotten them.
1643   SmallVector<unsigned, 4> RegArgs;
1644   unsigned NumBytes;
1645   if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1646     return false;
1647
1648   // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1649   // TODO: Turn this into the table of arm call ops.
1650   MachineInstrBuilder MIB;
1651   unsigned CallOpc;
1652   if(isThumb)
1653     CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1654   else
1655     CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1656   MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1657         .addExternalSymbol(TLI.getLibcallName(Call));
1658
1659   // Add implicit physical register uses to the call.
1660   for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1661     MIB.addReg(RegArgs[i]);
1662
1663   // Finish off the call including any return values.
1664   SmallVector<unsigned, 4> UsedRegs;
1665   if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1666
1667   // Set all unused physreg defs as dead.
1668   static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1669
1670   return true;
1671 }
1672
1673 bool ARMFastISel::SelectCall(const Instruction *I) {
1674   const CallInst *CI = cast<CallInst>(I);
1675   const Value *Callee = CI->getCalledValue();
1676
1677   // Can't handle inline asm or worry about intrinsics yet.
1678   if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1679
1680   // Only handle global variable Callees that are direct calls.
1681   const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1682   if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
1683     return false;
1684
1685   // Check the calling convention.
1686   ImmutableCallSite CS(CI);
1687   CallingConv::ID CC = CS.getCallingConv();
1688
1689   // TODO: Avoid some calling conventions?
1690
1691   // Let SDISel handle vararg functions.
1692   const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1693   const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1694   if (FTy->isVarArg())
1695     return false;
1696
1697   // Handle *simple* calls for now.
1698   const Type *RetTy = I->getType();
1699   MVT RetVT;
1700   if (RetTy->isVoidTy())
1701     RetVT = MVT::isVoid;
1702   else if (!isTypeLegal(RetTy, RetVT))
1703     return false;
1704
1705   // For now we're using BLX etc on the assumption that we have v5t ops.
1706   // TODO: Maybe?
1707   if (!Subtarget->hasV5TOps()) return false;
1708
1709   // Set up the argument vectors.
1710   SmallVector<Value*, 8> Args;
1711   SmallVector<unsigned, 8> ArgRegs;
1712   SmallVector<MVT, 8> ArgVTs;
1713   SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1714   Args.reserve(CS.arg_size());
1715   ArgRegs.reserve(CS.arg_size());
1716   ArgVTs.reserve(CS.arg_size());
1717   ArgFlags.reserve(CS.arg_size());
1718   for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1719        i != e; ++i) {
1720     unsigned Arg = getRegForValue(*i);
1721
1722     if (Arg == 0)
1723       return false;
1724     ISD::ArgFlagsTy Flags;
1725     unsigned AttrInd = i - CS.arg_begin() + 1;
1726     if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1727       Flags.setSExt();
1728     if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1729       Flags.setZExt();
1730
1731          // FIXME: Only handle *easy* calls for now.
1732     if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1733         CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1734         CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1735         CS.paramHasAttr(AttrInd, Attribute::ByVal))
1736       return false;
1737
1738     const Type *ArgTy = (*i)->getType();
1739     MVT ArgVT;
1740     if (!isTypeLegal(ArgTy, ArgVT))
1741       return false;
1742     unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1743     Flags.setOrigAlign(OriginalAlignment);
1744
1745     Args.push_back(*i);
1746     ArgRegs.push_back(Arg);
1747     ArgVTs.push_back(ArgVT);
1748     ArgFlags.push_back(Flags);
1749   }
1750
1751   // Handle the arguments now that we've gotten them.
1752   SmallVector<unsigned, 4> RegArgs;
1753   unsigned NumBytes;
1754   if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1755     return false;
1756
1757   // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1758   // TODO: Turn this into the table of arm call ops.
1759   MachineInstrBuilder MIB;
1760   unsigned CallOpc;
1761   if(isThumb)
1762     CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1763   else
1764     CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1765   MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1766               .addGlobalAddress(GV, 0, 0);
1767
1768   // Add implicit physical register uses to the call.
1769   for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1770     MIB.addReg(RegArgs[i]);
1771
1772   // Finish off the call including any return values.
1773   SmallVector<unsigned, 4> UsedRegs;
1774   if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1775
1776   // Set all unused physreg defs as dead.
1777   static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1778
1779   return true;
1780
1781 }
1782
1783 // TODO: SoftFP support.
1784 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1785
1786   switch (I->getOpcode()) {
1787     case Instruction::Load:
1788       return SelectLoad(I);
1789     case Instruction::Store:
1790       return SelectStore(I);
1791     case Instruction::Br:
1792       return SelectBranch(I);
1793     case Instruction::ICmp:
1794     case Instruction::FCmp:
1795       return SelectCmp(I);
1796     case Instruction::FPExt:
1797       return SelectFPExt(I);
1798     case Instruction::FPTrunc:
1799       return SelectFPTrunc(I);
1800     case Instruction::SIToFP:
1801       return SelectSIToFP(I);
1802     case Instruction::FPToSI:
1803       return SelectFPToSI(I);
1804     case Instruction::FAdd:
1805       return SelectBinaryOp(I, ISD::FADD);
1806     case Instruction::FSub:
1807       return SelectBinaryOp(I, ISD::FSUB);
1808     case Instruction::FMul:
1809       return SelectBinaryOp(I, ISD::FMUL);
1810     case Instruction::SDiv:
1811       return SelectSDiv(I);
1812     case Instruction::SRem:
1813       return SelectSRem(I);
1814     case Instruction::Call:
1815       return SelectCall(I);
1816     case Instruction::Select:
1817       return SelectSelect(I);
1818     case Instruction::Ret:
1819       return SelectRet(I);
1820     default: break;
1821   }
1822   return false;
1823 }
1824
1825 namespace llvm {
1826   llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1827     // Completely untested on non-darwin.
1828     const TargetMachine &TM = funcInfo.MF->getTarget();
1829
1830     // Darwin and thumb1 only for now.
1831     const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
1832     if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
1833         !DisableARMFastISel)
1834       return new ARMFastISel(funcInfo);
1835     return 0;
1836   }
1837 }