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Fixed some bugs.
[llvm/zpu.git] / lib / Target / ARM / ARMISelDAGToDAG.cpp
blobee3ffef0e5ff47850447e8ba23df801d7c30715f
1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines an instruction selector for the ARM target.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "arm-isel"
15 #include "ARM.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36
37 using namespace llvm;
38
39 static cl::opt<bool>
40 DisableShifterOp("disable-shifter-op", cl::Hidden,
41 cl::desc("Disable isel of shifter-op"),
42 cl::init(false));
43
44 //===--------------------------------------------------------------------===//
45 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
46 /// instructions for SelectionDAG operations.
47 ///
48 namespace {
49
50 enum AddrMode2Type {
51 AM2_BASE, // Simple AM2 (+-imm12)
52 AM2_SHOP // Shifter-op AM2
53 };
54
55 class ARMDAGToDAGISel : public SelectionDAGISel {
56 ARMBaseTargetMachine &TM;
57
58 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
59 /// make the right decision when generating code for different targets.
60 const ARMSubtarget *Subtarget;
61
62 public:
63 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
64 CodeGenOpt::Level OptLevel)
65 : SelectionDAGISel(tm, OptLevel), TM(tm),
66 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
67 }
68
69 virtual const char *getPassName() const {
70 return "ARM Instruction Selection";
71 }
72
73 /// getI32Imm - Return a target constant of type i32 with the specified
74 /// value.
75 inline SDValue getI32Imm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, MVT::i32);
77 }
78
79 SDNode *Select(SDNode *N);
80
81 bool isShifterOpProfitable(const SDValue &Shift,
82 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
83 bool SelectShifterOperandReg(SDValue N, SDValue &A,
84 SDValue &B, SDValue &C);
85 bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
86 SDValue &B, SDValue &C);
87 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
88 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
89
90 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
91 SDValue &Offset, SDValue &Opc);
92 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
93 SDValue &Opc) {
94 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
95 }
96
97 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
98 SDValue &Opc) {
99 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
100 }
101
102 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
103 SDValue &Opc) {
104 SelectAddrMode2Worker(N, Base, Offset, Opc);
105 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
106 // This always matches one way or another.
107 return true;
108 }
109
110 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
111 SDValue &Offset, SDValue &Opc);
112 bool SelectAddrMode3(SDValue N, SDValue &Base,
113 SDValue &Offset, SDValue &Opc);
114 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
115 SDValue &Offset, SDValue &Opc);
116 bool SelectAddrMode5(SDValue N, SDValue &Base,
117 SDValue &Offset);
118 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
119
120 bool SelectAddrModePC(SDValue N, SDValue &Offset,
121 SDValue &Label);
122
123 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
124 bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
125 SDValue &Base, SDValue &OffImm,
126 SDValue &Offset);
127 bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
128 SDValue &OffImm, SDValue &Offset);
129 bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
130 SDValue &OffImm, SDValue &Offset);
131 bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
132 SDValue &OffImm, SDValue &Offset);
133 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
134
135 bool SelectT2ShifterOperandReg(SDValue N,
136 SDValue &BaseReg, SDValue &Opc);
137 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
138 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
139 SDValue &OffImm);
140 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
141 SDValue &OffImm);
142 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
143 SDValue &OffReg, SDValue &ShImm);
144
145 inline bool Pred_so_imm(SDNode *inN) const {
146 ConstantSDNode *N = cast<ConstantSDNode>(inN);
147 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
148 }
149
150 inline bool Pred_t2_so_imm(SDNode *inN) const {
151 ConstantSDNode *N = cast<ConstantSDNode>(inN);
152 return ARM_AM::getT2SOImmVal(N->getZExtValue()) != -1;
153 }
154
155 // Include the pieces autogenerated from the target description.
156 #include "ARMGenDAGISel.inc"
157
158 private:
159 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
160 /// ARM.
161 SDNode *SelectARMIndexedLoad(SDNode *N);
162 SDNode *SelectT2IndexedLoad(SDNode *N);
163
164 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
165 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
166 /// loads of D registers and even subregs and odd subregs of Q registers.
167 /// For NumVecs <= 2, QOpcodes1 is not used.
168 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
169 unsigned *QOpcodes0, unsigned *QOpcodes1);
170
171 /// SelectVST - Select NEON store intrinsics. NumVecs should
172 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
173 /// stores of D registers and even subregs and odd subregs of Q registers.
174 /// For NumVecs <= 2, QOpcodes1 is not used.
175 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
176 unsigned *QOpcodes0, unsigned *QOpcodes1);
177
178 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
179 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
180 /// load/store of D registers and Q registers.
181 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
182 unsigned *DOpcodes, unsigned *QOpcodes);
183
184 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
185 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
186 /// generated to force the table registers to be consecutive.
187 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
188
189 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
190 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
191
192 /// SelectCMOVOp - Select CMOV instructions for ARM.
193 SDNode *SelectCMOVOp(SDNode *N);
194 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
195 ARMCC::CondCodes CCVal, SDValue CCR,
196 SDValue InFlag);
197 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
198 ARMCC::CondCodes CCVal, SDValue CCR,
199 SDValue InFlag);
200 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
201 ARMCC::CondCodes CCVal, SDValue CCR,
202 SDValue InFlag);
203 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
204 ARMCC::CondCodes CCVal, SDValue CCR,
205 SDValue InFlag);
206
207 SDNode *SelectConcatVector(SDNode *N);
208
209 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
210 /// inline asm expressions.
211 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
212 char ConstraintCode,
213 std::vector<SDValue> &OutOps);
214
215 // Form pairs of consecutive S, D, or Q registers.
216 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
217 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
218 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
219
220 // Form sequences of 4 consecutive S, D, or Q registers.
221 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
222 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
223 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
224
225 // Get the alignment operand for a NEON VLD or VST instruction.
226 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
227 };
228 }
229
230 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
231 /// operand. If so Imm will receive the 32-bit value.
232 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
233 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
234 Imm = cast<ConstantSDNode>(N)->getZExtValue();
235 return true;
236 }
237 return false;
238 }
239
240 // isInt32Immediate - This method tests to see if a constant operand.
241 // If so Imm will receive the 32 bit value.
242 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
243 return isInt32Immediate(N.getNode(), Imm);
244 }
245
246 // isOpcWithIntImmediate - This method tests to see if the node is a specific
247 // opcode and that it has a immediate integer right operand.
248 // If so Imm will receive the 32 bit value.
249 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
250 return N->getOpcode() == Opc &&
251 isInt32Immediate(N->getOperand(1).getNode(), Imm);
252 }
253
254
255 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
256 ARM_AM::ShiftOpc ShOpcVal,
257 unsigned ShAmt) {
258 if (!Subtarget->isCortexA9())
259 return true;
260 if (Shift.hasOneUse())
261 return true;
262 // R << 2 is free.
263 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
264 }
265
266 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
267 SDValue &BaseReg,
268 SDValue &ShReg,
269 SDValue &Opc) {
270 if (DisableShifterOp)
271 return false;
272
273 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
274
275 // Don't match base register only case. That is matched to a separate
276 // lower complexity pattern with explicit register operand.
277 if (ShOpcVal == ARM_AM::no_shift) return false;
278
279 BaseReg = N.getOperand(0);
280 unsigned ShImmVal = 0;
281 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
282 ShReg = CurDAG->getRegister(0, MVT::i32);
283 ShImmVal = RHS->getZExtValue() & 31;
284 } else {
285 ShReg = N.getOperand(1);
286 if (!isShifterOpProfitable(N, ShOpcVal, ShImmVal))
287 return false;
288 }
289 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
290 MVT::i32);
291 return true;
292 }
293
294 bool ARMDAGToDAGISel::SelectShiftShifterOperandReg(SDValue N,
295 SDValue &BaseReg,
296 SDValue &ShReg,
297 SDValue &Opc) {
298 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
299
300 // Don't match base register only case. That is matched to a separate
301 // lower complexity pattern with explicit register operand.
302 if (ShOpcVal == ARM_AM::no_shift) return false;
303
304 BaseReg = N.getOperand(0);
305 unsigned ShImmVal = 0;
306 // Do not check isShifterOpProfitable. This must return true.
307 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
308 ShReg = CurDAG->getRegister(0, MVT::i32);
309 ShImmVal = RHS->getZExtValue() & 31;
310 } else {
311 ShReg = N.getOperand(1);
312 }
313 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
314 MVT::i32);
315 return true;
316 }
317
318 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
319 SDValue &Base,
320 SDValue &OffImm) {
321 // Match simple R + imm12 operands.
322
323 // Base only.
324 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
325 if (N.getOpcode() == ISD::FrameIndex) {
326 // Match frame index...
327 int FI = cast<FrameIndexSDNode>(N)->getIndex();
328 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
329 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
330 return true;
331 } else if (N.getOpcode() == ARMISD::Wrapper &&
332 !(Subtarget->useMovt() &&
333 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
334 Base = N.getOperand(0);
335 } else
336 Base = N;
337 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
338 return true;
339 }
340
341 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
342 int RHSC = (int)RHS->getZExtValue();
343 if (N.getOpcode() == ISD::SUB)
344 RHSC = -RHSC;
345
346 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
347 Base = N.getOperand(0);
348 if (Base.getOpcode() == ISD::FrameIndex) {
349 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
350 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
351 }
352 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
353 return true;
354 }
355 }
356
357 // Base only.
358 Base = N;
359 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
360 return true;
361 }
362
363
364
365 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
366 SDValue &Opc) {
367 if (N.getOpcode() == ISD::MUL &&
368 (!Subtarget->isCortexA9() || N.hasOneUse())) {
369 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
370 // X * [3,5,9] -> X + X * [2,4,8] etc.
371 int RHSC = (int)RHS->getZExtValue();
372 if (RHSC & 1) {
373 RHSC = RHSC & ~1;
374 ARM_AM::AddrOpc AddSub = ARM_AM::add;
375 if (RHSC < 0) {
376 AddSub = ARM_AM::sub;
377 RHSC = - RHSC;
378 }
379 if (isPowerOf2_32(RHSC)) {
380 unsigned ShAmt = Log2_32(RHSC);
381 Base = Offset = N.getOperand(0);
382 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
383 ARM_AM::lsl),
384 MVT::i32);
385 return true;
386 }
387 }
388 }
389 }
390
391 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB)
392 return false;
393
394 // Leave simple R +/- imm12 operands for LDRi12
395 if (N.getOpcode() == ISD::ADD) {
396 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
397 int RHSC = (int)RHS->getZExtValue();
398 if ((RHSC >= 0 && RHSC < 0x1000) ||
399 (RHSC < 0 && RHSC > -0x1000)) // 12 bits.
400 return false;
401 }
402 }
403
404 if (Subtarget->isCortexA9() && !N.hasOneUse())
405 // Compute R +/- (R << N) and reuse it.
406 return false;
407
408 // Otherwise this is R +/- [possibly shifted] R.
409 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
410 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
411 unsigned ShAmt = 0;
412
413 Base = N.getOperand(0);
414 Offset = N.getOperand(1);
415
416 if (ShOpcVal != ARM_AM::no_shift) {
417 // Check to see if the RHS of the shift is a constant, if not, we can't fold
418 // it.
419 if (ConstantSDNode *Sh =
420 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
421 ShAmt = Sh->getZExtValue();
422 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
423 Offset = N.getOperand(1).getOperand(0);
424 else {
425 ShAmt = 0;
426 ShOpcVal = ARM_AM::no_shift;
427 }
428 } else {
429 ShOpcVal = ARM_AM::no_shift;
430 }
431 }
432
433 // Try matching (R shl C) + (R).
434 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
435 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
436 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
437 if (ShOpcVal != ARM_AM::no_shift) {
438 // Check to see if the RHS of the shift is a constant, if not, we can't
439 // fold it.
440 if (ConstantSDNode *Sh =
441 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
442 ShAmt = Sh->getZExtValue();
443 if (!Subtarget->isCortexA9() ||
444 (N.hasOneUse() &&
445 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
446 Offset = N.getOperand(0).getOperand(0);
447 Base = N.getOperand(1);
448 } else {
449 ShAmt = 0;
450 ShOpcVal = ARM_AM::no_shift;
451 }
452 } else {
453 ShOpcVal = ARM_AM::no_shift;
454 }
455 }
456 }
457
458 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
459 MVT::i32);
460 return true;
461 }
462
463
464
465
466 //-----
467
468 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
469 SDValue &Base,
470 SDValue &Offset,
471 SDValue &Opc) {
472 if (N.getOpcode() == ISD::MUL &&
473 (!Subtarget->isCortexA9() || N.hasOneUse())) {
474 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
475 // X * [3,5,9] -> X + X * [2,4,8] etc.
476 int RHSC = (int)RHS->getZExtValue();
477 if (RHSC & 1) {
478 RHSC = RHSC & ~1;
479 ARM_AM::AddrOpc AddSub = ARM_AM::add;
480 if (RHSC < 0) {
481 AddSub = ARM_AM::sub;
482 RHSC = - RHSC;
483 }
484 if (isPowerOf2_32(RHSC)) {
485 unsigned ShAmt = Log2_32(RHSC);
486 Base = Offset = N.getOperand(0);
487 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
488 ARM_AM::lsl),
489 MVT::i32);
490 return AM2_SHOP;
491 }
492 }
493 }
494 }
495
496 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
497 Base = N;
498 if (N.getOpcode() == ISD::FrameIndex) {
499 int FI = cast<FrameIndexSDNode>(N)->getIndex();
500 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
501 } else if (N.getOpcode() == ARMISD::Wrapper &&
502 !(Subtarget->useMovt() &&
503 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
504 Base = N.getOperand(0);
505 }
506 Offset = CurDAG->getRegister(0, MVT::i32);
507 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
508 ARM_AM::no_shift),
509 MVT::i32);
510 return AM2_BASE;
511 }
512
513 // Match simple R +/- imm12 operands.
514 if (N.getOpcode() == ISD::ADD) {
515 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
516 int RHSC = (int)RHS->getZExtValue();
517 if ((RHSC >= 0 && RHSC < 0x1000) ||
518 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
519 Base = N.getOperand(0);
520 if (Base.getOpcode() == ISD::FrameIndex) {
521 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
522 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
523 }
524 Offset = CurDAG->getRegister(0, MVT::i32);
525
526 ARM_AM::AddrOpc AddSub = ARM_AM::add;
527 if (RHSC < 0) {
528 AddSub = ARM_AM::sub;
529 RHSC = - RHSC;
530 }
531 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
532 ARM_AM::no_shift),
533 MVT::i32);
534 return AM2_BASE;
535 }
536 }
537 }
538
539 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
540 // Compute R +/- (R << N) and reuse it.
541 Base = N;
542 Offset = CurDAG->getRegister(0, MVT::i32);
543 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
544 ARM_AM::no_shift),
545 MVT::i32);
546 return AM2_BASE;
547 }
548
549 // Otherwise this is R +/- [possibly shifted] R.
550 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
551 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
552 unsigned ShAmt = 0;
553
554 Base = N.getOperand(0);
555 Offset = N.getOperand(1);
556
557 if (ShOpcVal != ARM_AM::no_shift) {
558 // Check to see if the RHS of the shift is a constant, if not, we can't fold
559 // it.
560 if (ConstantSDNode *Sh =
561 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
562 ShAmt = Sh->getZExtValue();
563 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
564 Offset = N.getOperand(1).getOperand(0);
565 else {
566 ShAmt = 0;
567 ShOpcVal = ARM_AM::no_shift;
568 }
569 } else {
570 ShOpcVal = ARM_AM::no_shift;
571 }
572 }
573
574 // Try matching (R shl C) + (R).
575 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
576 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
577 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
578 if (ShOpcVal != ARM_AM::no_shift) {
579 // Check to see if the RHS of the shift is a constant, if not, we can't
580 // fold it.
581 if (ConstantSDNode *Sh =
582 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
583 ShAmt = Sh->getZExtValue();
584 if (!Subtarget->isCortexA9() ||
585 (N.hasOneUse() &&
586 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
587 Offset = N.getOperand(0).getOperand(0);
588 Base = N.getOperand(1);
589 } else {
590 ShAmt = 0;
591 ShOpcVal = ARM_AM::no_shift;
592 }
593 } else {
594 ShOpcVal = ARM_AM::no_shift;
595 }
596 }
597 }
598
599 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
600 MVT::i32);
601 return AM2_SHOP;
602 }
603
604 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
605 SDValue &Offset, SDValue &Opc) {
606 unsigned Opcode = Op->getOpcode();
607 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
608 ? cast<LoadSDNode>(Op)->getAddressingMode()
609 : cast<StoreSDNode>(Op)->getAddressingMode();
610 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
611 ? ARM_AM::add : ARM_AM::sub;
612 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
613 int Val = (int)C->getZExtValue();
614 if (Val >= 0 && Val < 0x1000) { // 12 bits.
615 Offset = CurDAG->getRegister(0, MVT::i32);
616 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
617 ARM_AM::no_shift),
618 MVT::i32);
619 return true;
620 }
621 }
622
623 Offset = N;
624 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
625 unsigned ShAmt = 0;
626 if (ShOpcVal != ARM_AM::no_shift) {
627 // Check to see if the RHS of the shift is a constant, if not, we can't fold
628 // it.
629 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
630 ShAmt = Sh->getZExtValue();
631 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
632 Offset = N.getOperand(0);
633 else {
634 ShAmt = 0;
635 ShOpcVal = ARM_AM::no_shift;
636 }
637 } else {
638 ShOpcVal = ARM_AM::no_shift;
639 }
640 }
641
642 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
643 MVT::i32);
644 return true;
645 }
646
647
648 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
649 SDValue &Base, SDValue &Offset,
650 SDValue &Opc) {
651 if (N.getOpcode() == ISD::SUB) {
652 // X - C is canonicalize to X + -C, no need to handle it here.
653 Base = N.getOperand(0);
654 Offset = N.getOperand(1);
655 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
656 return true;
657 }
658
659 if (N.getOpcode() != ISD::ADD) {
660 Base = N;
661 if (N.getOpcode() == ISD::FrameIndex) {
662 int FI = cast<FrameIndexSDNode>(N)->getIndex();
663 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
664 }
665 Offset = CurDAG->getRegister(0, MVT::i32);
666 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
667 return true;
668 }
669
670 // If the RHS is +/- imm8, fold into addr mode.
671 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
672 int RHSC = (int)RHS->getZExtValue();
673 if ((RHSC >= 0 && RHSC < 256) ||
674 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
675 Base = N.getOperand(0);
676 if (Base.getOpcode() == ISD::FrameIndex) {
677 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
678 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
679 }
680 Offset = CurDAG->getRegister(0, MVT::i32);
681
682 ARM_AM::AddrOpc AddSub = ARM_AM::add;
683 if (RHSC < 0) {
684 AddSub = ARM_AM::sub;
685 RHSC = - RHSC;
686 }
687 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
688 return true;
689 }
690 }
691
692 Base = N.getOperand(0);
693 Offset = N.getOperand(1);
694 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
695 return true;
696 }
697
698 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
699 SDValue &Offset, SDValue &Opc) {
700 unsigned Opcode = Op->getOpcode();
701 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
702 ? cast<LoadSDNode>(Op)->getAddressingMode()
703 : cast<StoreSDNode>(Op)->getAddressingMode();
704 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
705 ? ARM_AM::add : ARM_AM::sub;
706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
707 int Val = (int)C->getZExtValue();
708 if (Val >= 0 && Val < 256) {
709 Offset = CurDAG->getRegister(0, MVT::i32);
710 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
711 return true;
712 }
713 }
714
715 Offset = N;
716 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
717 return true;
718 }
719
720 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
721 SDValue &Base, SDValue &Offset) {
722 if (N.getOpcode() != ISD::ADD) {
723 Base = N;
724 if (N.getOpcode() == ISD::FrameIndex) {
725 int FI = cast<FrameIndexSDNode>(N)->getIndex();
726 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
727 } else if (N.getOpcode() == ARMISD::Wrapper &&
728 !(Subtarget->useMovt() &&
729 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
730 Base = N.getOperand(0);
731 }
732 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
733 MVT::i32);
734 return true;
735 }
736
737 // If the RHS is +/- imm8, fold into addr mode.
738 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
739 int RHSC = (int)RHS->getZExtValue();
740 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
741 RHSC >>= 2;
742 if ((RHSC >= 0 && RHSC < 256) ||
743 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
744 Base = N.getOperand(0);
745 if (Base.getOpcode() == ISD::FrameIndex) {
746 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
747 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
748 }
749
750 ARM_AM::AddrOpc AddSub = ARM_AM::add;
751 if (RHSC < 0) {
752 AddSub = ARM_AM::sub;
753 RHSC = - RHSC;
754 }
755 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
756 MVT::i32);
757 return true;
758 }
759 }
760 }
761
762 Base = N;
763 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
764 MVT::i32);
765 return true;
766 }
767
768 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
769 SDValue &Align) {
770 Addr = N;
771
772 unsigned Alignment = 0;
773 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
774 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
775 // The maximum alignment is equal to the memory size being referenced.
776 unsigned LSNAlign = LSN->getAlignment();
777 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
778 if (LSNAlign > MemSize && MemSize > 1)
779 Alignment = MemSize;
780 } else {
781 // All other uses of addrmode6 are for intrinsics. For now just record
782 // the raw alignment value; it will be refined later based on the legal
783 // alignment operands for the intrinsic.
784 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
785 }
786
787 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
788 return true;
789 }
790
791 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
792 SDValue &Offset, SDValue &Label) {
793 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
794 Offset = N.getOperand(0);
795 SDValue N1 = N.getOperand(1);
796 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
797 MVT::i32);
798 return true;
799 }
800 return false;
801 }
802
803 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
804 SDValue &Base, SDValue &Offset){
805 // FIXME dl should come from the parent load or store, not the address
806 if (N.getOpcode() != ISD::ADD) {
807 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
808 if (!NC || !NC->isNullValue())
809 return false;
810
811 Base = Offset = N;
812 return true;
813 }
814
815 Base = N.getOperand(0);
816 Offset = N.getOperand(1);
817 return true;
818 }
819
820 bool
821 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
822 unsigned Scale, SDValue &Base,
823 SDValue &OffImm, SDValue &Offset) {
824 if (Scale == 4) {
825 SDValue TmpBase, TmpOffImm;
826 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
827 return false; // We want to select tLDRspi / tSTRspi instead.
828 if (N.getOpcode() == ARMISD::Wrapper &&
829 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
830 return false; // We want to select tLDRpci instead.
831 }
832
833 if (N.getOpcode() != ISD::ADD) {
834 if (N.getOpcode() == ARMISD::Wrapper &&
835 !(Subtarget->useMovt() &&
836 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
837 Base = N.getOperand(0);
838 } else
839 Base = N;
840
841 Offset = CurDAG->getRegister(0, MVT::i32);
842 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
843 return true;
844 }
845
846 // Thumb does not have [sp, r] address mode.
847 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
848 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
849 if ((LHSR && LHSR->getReg() == ARM::SP) ||
850 (RHSR && RHSR->getReg() == ARM::SP)) {
851 Base = N;
852 Offset = CurDAG->getRegister(0, MVT::i32);
853 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
854 return true;
855 }
856
857 // If the RHS is + imm5 * scale, fold into addr mode.
858 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
859 int RHSC = (int)RHS->getZExtValue();
860 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
861 RHSC /= Scale;
862 if (RHSC >= 0 && RHSC < 32) {
863 Base = N.getOperand(0);
864 Offset = CurDAG->getRegister(0, MVT::i32);
865 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
866 return true;
867 }
868 }
869 }
870
871 Base = N.getOperand(0);
872 Offset = N.getOperand(1);
873 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
874 return true;
875 }
876
877 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
878 SDValue &Base, SDValue &OffImm,
879 SDValue &Offset) {
880 return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
881 }
882
883 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
884 SDValue &Base, SDValue &OffImm,
885 SDValue &Offset) {
886 return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
887 }
888
889 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
890 SDValue &Base, SDValue &OffImm,
891 SDValue &Offset) {
892 return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
893 }
894
895 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
896 SDValue &Base, SDValue &OffImm) {
897 if (N.getOpcode() == ISD::FrameIndex) {
898 int FI = cast<FrameIndexSDNode>(N)->getIndex();
899 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
900 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
901 return true;
902 }
903
904 if (N.getOpcode() != ISD::ADD)
905 return false;
906
907 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
908 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
909 (LHSR && LHSR->getReg() == ARM::SP)) {
910 // If the RHS is + imm8 * scale, fold into addr mode.
911 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
912 int RHSC = (int)RHS->getZExtValue();
913 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
914 RHSC >>= 2;
915 if (RHSC >= 0 && RHSC < 256) {
916 Base = N.getOperand(0);
917 if (Base.getOpcode() == ISD::FrameIndex) {
918 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
919 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
920 }
921 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
922 return true;
923 }
924 }
925 }
926 }
927
928 return false;
929 }
930
931 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
932 SDValue &Opc) {
933 if (DisableShifterOp)
934 return false;
935
936 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
937
938 // Don't match base register only case. That is matched to a separate
939 // lower complexity pattern with explicit register operand.
940 if (ShOpcVal == ARM_AM::no_shift) return false;
941
942 BaseReg = N.getOperand(0);
943 unsigned ShImmVal = 0;
944 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
945 ShImmVal = RHS->getZExtValue() & 31;
946 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
947 return true;
948 }
949
950 return false;
951 }
952
953 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
954 SDValue &Base, SDValue &OffImm) {
955 // Match simple R + imm12 operands.
956
957 // Base only.
958 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
959 if (N.getOpcode() == ISD::FrameIndex) {
960 // Match frame index...
961 int FI = cast<FrameIndexSDNode>(N)->getIndex();
962 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
963 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
964 return true;
965 } else if (N.getOpcode() == ARMISD::Wrapper &&
966 !(Subtarget->useMovt() &&
967 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
968 Base = N.getOperand(0);
969 if (Base.getOpcode() == ISD::TargetConstantPool)
970 return false; // We want to select t2LDRpci instead.
971 } else
972 Base = N;
973 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
974 return true;
975 }
976
977 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
978 if (SelectT2AddrModeImm8(N, Base, OffImm))
979 // Let t2LDRi8 handle (R - imm8).
980 return false;
981
982 int RHSC = (int)RHS->getZExtValue();
983 if (N.getOpcode() == ISD::SUB)
984 RHSC = -RHSC;
985
986 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
987 Base = N.getOperand(0);
988 if (Base.getOpcode() == ISD::FrameIndex) {
989 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
990 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
991 }
992 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
993 return true;
994 }
995 }
996
997 // Base only.
998 Base = N;
999 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1000 return true;
1001 }
1002
1003 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1004 SDValue &Base, SDValue &OffImm) {
1005 // Match simple R - imm8 operands.
1006 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
1007 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1008 int RHSC = (int)RHS->getSExtValue();
1009 if (N.getOpcode() == ISD::SUB)
1010 RHSC = -RHSC;
1011
1012 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1013 Base = N.getOperand(0);
1014 if (Base.getOpcode() == ISD::FrameIndex) {
1015 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1016 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1017 }
1018 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1019 return true;
1020 }
1021 }
1022 }
1023
1024 return false;
1025 }
1026
1027 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1028 SDValue &OffImm){
1029 unsigned Opcode = Op->getOpcode();
1030 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1031 ? cast<LoadSDNode>(Op)->getAddressingMode()
1032 : cast<StoreSDNode>(Op)->getAddressingMode();
1033 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
1034 int RHSC = (int)RHS->getZExtValue();
1035 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
1036 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1037 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1038 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1039 return true;
1040 }
1041 }
1042
1043 return false;
1044 }
1045
1046 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1047 SDValue &Base,
1048 SDValue &OffReg, SDValue &ShImm) {
1049 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1050 if (N.getOpcode() != ISD::ADD)
1051 return false;
1052
1053 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1054 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1055 int RHSC = (int)RHS->getZExtValue();
1056 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1057 return false;
1058 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1059 return false;
1060 }
1061
1062 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1063 // Compute R + (R << [1,2,3]) and reuse it.
1064 Base = N;
1065 return false;
1066 }
1067
1068 // Look for (R + R) or (R + (R << [1,2,3])).
1069 unsigned ShAmt = 0;
1070 Base = N.getOperand(0);
1071 OffReg = N.getOperand(1);
1072
1073 // Swap if it is ((R << c) + R).
1074 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
1075 if (ShOpcVal != ARM_AM::lsl) {
1076 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
1077 if (ShOpcVal == ARM_AM::lsl)
1078 std::swap(Base, OffReg);
1079 }
1080
1081 if (ShOpcVal == ARM_AM::lsl) {
1082 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1083 // it.
1084 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1085 ShAmt = Sh->getZExtValue();
1086 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1087 OffReg = OffReg.getOperand(0);
1088 else {
1089 ShAmt = 0;
1090 ShOpcVal = ARM_AM::no_shift;
1091 }
1092 } else {
1093 ShOpcVal = ARM_AM::no_shift;
1094 }
1095 }
1096
1097 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1098
1099 return true;
1100 }
1101
1102 //===--------------------------------------------------------------------===//
1103
1104 /// getAL - Returns a ARMCC::AL immediate node.
1105 static inline SDValue getAL(SelectionDAG *CurDAG) {
1106 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1107 }
1108
1109 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1110 LoadSDNode *LD = cast<LoadSDNode>(N);
1111 ISD::MemIndexedMode AM = LD->getAddressingMode();
1112 if (AM == ISD::UNINDEXED)
1113 return NULL;
1114
1115 EVT LoadedVT = LD->getMemoryVT();
1116 SDValue Offset, AMOpc;
1117 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1118 unsigned Opcode = 0;
1119 bool Match = false;
1120 if (LoadedVT == MVT::i32 &&
1121 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1122 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
1123 Match = true;
1124 } else if (LoadedVT == MVT::i16 &&
1125 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1126 Match = true;
1127 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1128 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1129 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1130 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1131 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1132 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1133 Match = true;
1134 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1135 }
1136 } else {
1137 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1138 Match = true;
1139 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
1140 }
1141 }
1142 }
1143
1144 if (Match) {
1145 SDValue Chain = LD->getChain();
1146 SDValue Base = LD->getBasePtr();
1147 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1148 CurDAG->getRegister(0, MVT::i32), Chain };
1149 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1150 MVT::Other, Ops, 6);
1151 }
1152
1153 return NULL;
1154 }
1155
1156 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1157 LoadSDNode *LD = cast<LoadSDNode>(N);
1158 ISD::MemIndexedMode AM = LD->getAddressingMode();
1159 if (AM == ISD::UNINDEXED)
1160 return NULL;
1161
1162 EVT LoadedVT = LD->getMemoryVT();
1163 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1164 SDValue Offset;
1165 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1166 unsigned Opcode = 0;
1167 bool Match = false;
1168 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1169 switch (LoadedVT.getSimpleVT().SimpleTy) {
1170 case MVT::i32:
1171 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1172 break;
1173 case MVT::i16:
1174 if (isSExtLd)
1175 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1176 else
1177 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1178 break;
1179 case MVT::i8:
1180 case MVT::i1:
1181 if (isSExtLd)
1182 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1183 else
1184 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1185 break;
1186 default:
1187 return NULL;
1188 }
1189 Match = true;
1190 }
1191
1192 if (Match) {
1193 SDValue Chain = LD->getChain();
1194 SDValue Base = LD->getBasePtr();
1195 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1196 CurDAG->getRegister(0, MVT::i32), Chain };
1197 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1198 MVT::Other, Ops, 5);
1199 }
1200
1201 return NULL;
1202 }
1203
1204 /// PairSRegs - Form a D register from a pair of S registers.
1205 ///
1206 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1207 DebugLoc dl = V0.getNode()->getDebugLoc();
1208 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1209 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1210 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1211 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1212 }
1213
1214 /// PairDRegs - Form a quad register from a pair of D registers.
1215 ///
1216 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1217 DebugLoc dl = V0.getNode()->getDebugLoc();
1218 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1219 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1220 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1221 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1222 }
1223
1224 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1225 ///
1226 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1227 DebugLoc dl = V0.getNode()->getDebugLoc();
1228 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1229 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1230 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1231 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1232 }
1233
1234 /// QuadSRegs - Form 4 consecutive S registers.
1235 ///
1236 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1237 SDValue V2, SDValue V3) {
1238 DebugLoc dl = V0.getNode()->getDebugLoc();
1239 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1240 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1241 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1242 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1243 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1244 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1245 }
1246
1247 /// QuadDRegs - Form 4 consecutive D registers.
1248 ///
1249 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1250 SDValue V2, SDValue V3) {
1251 DebugLoc dl = V0.getNode()->getDebugLoc();
1252 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1253 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1254 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1255 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1256 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1257 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1258 }
1259
1260 /// QuadQRegs - Form 4 consecutive Q registers.
1261 ///
1262 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1263 SDValue V2, SDValue V3) {
1264 DebugLoc dl = V0.getNode()->getDebugLoc();
1265 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1266 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1267 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1268 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1269 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1270 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1271 }
1272
1273 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1274 /// of a NEON VLD or VST instruction. The supported values depend on the
1275 /// number of registers being loaded.
1276 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1277 bool is64BitVector) {
1278 unsigned NumRegs = NumVecs;
1279 if (!is64BitVector && NumVecs < 3)
1280 NumRegs *= 2;
1281
1282 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1283 if (Alignment >= 32 && NumRegs == 4)
1284 Alignment = 32;
1285 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1286 Alignment = 16;
1287 else if (Alignment >= 8)
1288 Alignment = 8;
1289 else
1290 Alignment = 0;
1291
1292 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1293 }
1294
1295 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1296 unsigned *DOpcodes, unsigned *QOpcodes0,
1297 unsigned *QOpcodes1) {
1298 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1299 DebugLoc dl = N->getDebugLoc();
1300
1301 SDValue MemAddr, Align;
1302 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1303 return NULL;
1304
1305 SDValue Chain = N->getOperand(0);
1306 EVT VT = N->getValueType(0);
1307 bool is64BitVector = VT.is64BitVector();
1308 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1309
1310 unsigned OpcodeIndex;
1311 switch (VT.getSimpleVT().SimpleTy) {
1312 default: llvm_unreachable("unhandled vld type");
1313 // Double-register operations:
1314 case MVT::v8i8: OpcodeIndex = 0; break;
1315 case MVT::v4i16: OpcodeIndex = 1; break;
1316 case MVT::v2f32:
1317 case MVT::v2i32: OpcodeIndex = 2; break;
1318 case MVT::v1i64: OpcodeIndex = 3; break;
1319 // Quad-register operations:
1320 case MVT::v16i8: OpcodeIndex = 0; break;
1321 case MVT::v8i16: OpcodeIndex = 1; break;
1322 case MVT::v4f32:
1323 case MVT::v4i32: OpcodeIndex = 2; break;
1324 case MVT::v2i64: OpcodeIndex = 3;
1325 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1326 break;
1327 }
1328
1329 EVT ResTy;
1330 if (NumVecs == 1)
1331 ResTy = VT;
1332 else {
1333 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1334 if (!is64BitVector)
1335 ResTyElts *= 2;
1336 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1337 }
1338
1339 SDValue Pred = getAL(CurDAG);
1340 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1341 SDValue SuperReg;
1342 if (is64BitVector) {
1343 unsigned Opc = DOpcodes[OpcodeIndex];
1344 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1345 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1346 if (NumVecs == 1)
1347 return VLd;
1348
1349 SuperReg = SDValue(VLd, 0);
1350 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1351 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1352 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
1353 dl, VT, SuperReg);
1354 ReplaceUses(SDValue(N, Vec), D);
1355 }
1356 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1357 return NULL;
1358 }
1359
1360 if (NumVecs <= 2) {
1361 // Quad registers are directly supported for VLD1 and VLD2,
1362 // loading pairs of D regs.
1363 unsigned Opc = QOpcodes0[OpcodeIndex];
1364 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1365 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1366 if (NumVecs == 1)
1367 return VLd;
1368
1369 SuperReg = SDValue(VLd, 0);
1370 Chain = SDValue(VLd, 1);
1371
1372 } else {
1373 // Otherwise, quad registers are loaded with two separate instructions,
1374 // where one loads the even registers and the other loads the odd registers.
1375 EVT AddrTy = MemAddr.getValueType();
1376
1377 // Load the even subregs.
1378 unsigned Opc = QOpcodes0[OpcodeIndex];
1379 SDValue ImplDef =
1380 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1381 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1382 SDNode *VLdA =
1383 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7);
1384 Chain = SDValue(VLdA, 2);
1385
1386 // Load the odd subregs.
1387 Opc = QOpcodes1[OpcodeIndex];
1388 const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0),
1389 Pred, Reg0, Chain };
1390 SDNode *VLdB =
1391 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7);
1392 SuperReg = SDValue(VLdB, 0);
1393 Chain = SDValue(VLdB, 2);
1394 }
1395
1396 // Extract out the Q registers.
1397 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1398 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1399 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1400 dl, VT, SuperReg);
1401 ReplaceUses(SDValue(N, Vec), Q);
1402 }
1403 ReplaceUses(SDValue(N, NumVecs), Chain);
1404 return NULL;
1405 }
1406
1407 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1408 unsigned *DOpcodes, unsigned *QOpcodes0,
1409 unsigned *QOpcodes1) {
1410 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1411 DebugLoc dl = N->getDebugLoc();
1412
1413 SDValue MemAddr, Align;
1414 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1415 return NULL;
1416
1417 SDValue Chain = N->getOperand(0);
1418 EVT VT = N->getOperand(3).getValueType();
1419 bool is64BitVector = VT.is64BitVector();
1420 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1421
1422 unsigned OpcodeIndex;
1423 switch (VT.getSimpleVT().SimpleTy) {
1424 default: llvm_unreachable("unhandled vst type");
1425 // Double-register operations:
1426 case MVT::v8i8: OpcodeIndex = 0; break;
1427 case MVT::v4i16: OpcodeIndex = 1; break;
1428 case MVT::v2f32:
1429 case MVT::v2i32: OpcodeIndex = 2; break;
1430 case MVT::v1i64: OpcodeIndex = 3; break;
1431 // Quad-register operations:
1432 case MVT::v16i8: OpcodeIndex = 0; break;
1433 case MVT::v8i16: OpcodeIndex = 1; break;
1434 case MVT::v4f32:
1435 case MVT::v4i32: OpcodeIndex = 2; break;
1436 case MVT::v2i64: OpcodeIndex = 3;
1437 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1438 break;
1439 }
1440
1441 SDValue Pred = getAL(CurDAG);
1442 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1443
1444 SmallVector<SDValue, 7> Ops;
1445 Ops.push_back(MemAddr);
1446 Ops.push_back(Align);
1447
1448 if (is64BitVector) {
1449 if (NumVecs == 1) {
1450 Ops.push_back(N->getOperand(3));
1451 } else {
1452 SDValue RegSeq;
1453 SDValue V0 = N->getOperand(0+3);
1454 SDValue V1 = N->getOperand(1+3);
1455
1456 // Form a REG_SEQUENCE to force register allocation.
1457 if (NumVecs == 2)
1458 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1459 else {
1460 SDValue V2 = N->getOperand(2+3);
1461 // If it's a vld3, form a quad D-register and leave the last part as
1462 // an undef.
1463 SDValue V3 = (NumVecs == 3)
1464 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1465 : N->getOperand(3+3);
1466 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1467 }
1468 Ops.push_back(RegSeq);
1469 }
1470 Ops.push_back(Pred);
1471 Ops.push_back(Reg0); // predicate register
1472 Ops.push_back(Chain);
1473 unsigned Opc = DOpcodes[OpcodeIndex];
1474 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1475 }
1476
1477 if (NumVecs <= 2) {
1478 // Quad registers are directly supported for VST1 and VST2.
1479 unsigned Opc = QOpcodes0[OpcodeIndex];
1480 if (NumVecs == 1) {
1481 Ops.push_back(N->getOperand(3));
1482 } else {
1483 // Form a QQ register.
1484 SDValue Q0 = N->getOperand(3);
1485 SDValue Q1 = N->getOperand(4);
1486 Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0));
1487 }
1488 Ops.push_back(Pred);
1489 Ops.push_back(Reg0); // predicate register
1490 Ops.push_back(Chain);
1491 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1492 }
1493
1494 // Otherwise, quad registers are stored with two separate instructions,
1495 // where one stores the even registers and the other stores the odd registers.
1496
1497 // Form the QQQQ REG_SEQUENCE.
1498 SDValue V0 = N->getOperand(0+3);
1499 SDValue V1 = N->getOperand(1+3);
1500 SDValue V2 = N->getOperand(2+3);
1501 SDValue V3 = (NumVecs == 3)
1502 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1503 : N->getOperand(3+3);
1504 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1505
1506 // Store the even D registers.
1507 Ops.push_back(Reg0); // post-access address offset
1508 Ops.push_back(RegSeq);
1509 Ops.push_back(Pred);
1510 Ops.push_back(Reg0); // predicate register
1511 Ops.push_back(Chain);
1512 unsigned Opc = QOpcodes0[OpcodeIndex];
1513 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1514 MVT::Other, Ops.data(), 7);
1515 Chain = SDValue(VStA, 1);
1516
1517 // Store the odd D registers.
1518 Ops[0] = SDValue(VStA, 0); // MemAddr
1519 Ops[6] = Chain;
1520 Opc = QOpcodes1[OpcodeIndex];
1521 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1522 MVT::Other, Ops.data(), 7);
1523 Chain = SDValue(VStB, 1);
1524 ReplaceUses(SDValue(N, 0), Chain);
1525 return NULL;
1526 }
1527
1528 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1529 unsigned NumVecs, unsigned *DOpcodes,
1530 unsigned *QOpcodes) {
1531 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1532 DebugLoc dl = N->getDebugLoc();
1533
1534 SDValue MemAddr, Align;
1535 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1536 return NULL;
1537
1538 SDValue Chain = N->getOperand(0);
1539 unsigned Lane =
1540 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1541 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1542 bool is64BitVector = VT.is64BitVector();
1543
1544 unsigned Alignment = 0;
1545 if (NumVecs != 3) {
1546 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1547 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1548 if (Alignment > NumBytes)
1549 Alignment = NumBytes;
1550 // Alignment must be a power of two; make sure of that.
1551 Alignment = (Alignment & -Alignment);
1552 if (Alignment == 1)
1553 Alignment = 0;
1554 }
1555 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1556
1557 unsigned OpcodeIndex;
1558 switch (VT.getSimpleVT().SimpleTy) {
1559 default: llvm_unreachable("unhandled vld/vst lane type");
1560 // Double-register operations:
1561 case MVT::v8i8: OpcodeIndex = 0; break;
1562 case MVT::v4i16: OpcodeIndex = 1; break;
1563 case MVT::v2f32:
1564 case MVT::v2i32: OpcodeIndex = 2; break;
1565 // Quad-register operations:
1566 case MVT::v8i16: OpcodeIndex = 0; break;
1567 case MVT::v4f32:
1568 case MVT::v4i32: OpcodeIndex = 1; break;
1569 }
1570
1571 SDValue Pred = getAL(CurDAG);
1572 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1573
1574 SmallVector<SDValue, 7> Ops;
1575 Ops.push_back(MemAddr);
1576 Ops.push_back(Align);
1577
1578 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1579 QOpcodes[OpcodeIndex]);
1580
1581 SDValue SuperReg;
1582 SDValue V0 = N->getOperand(0+3);
1583 SDValue V1 = N->getOperand(1+3);
1584 if (NumVecs == 2) {
1585 if (is64BitVector)
1586 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1587 else
1588 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1589 } else {
1590 SDValue V2 = N->getOperand(2+3);
1591 SDValue V3 = (NumVecs == 3)
1592 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1593 : N->getOperand(3+3);
1594 if (is64BitVector)
1595 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1596 else
1597 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1598 }
1599 Ops.push_back(SuperReg);
1600 Ops.push_back(getI32Imm(Lane));
1601 Ops.push_back(Pred);
1602 Ops.push_back(Reg0);
1603 Ops.push_back(Chain);
1604
1605 if (!IsLoad)
1606 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 7);
1607
1608 EVT ResTy;
1609 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1610 if (!is64BitVector)
1611 ResTyElts *= 2;
1612 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1613
1614 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other,
1615 Ops.data(), 7);
1616 SuperReg = SDValue(VLdLn, 0);
1617 Chain = SDValue(VLdLn, 1);
1618
1619 // Extract the subregisters.
1620 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1621 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1622 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1623 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1624 ReplaceUses(SDValue(N, Vec),
1625 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1626 ReplaceUses(SDValue(N, NumVecs), Chain);
1627 return NULL;
1628 }
1629
1630 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1631 unsigned Opc) {
1632 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1633 DebugLoc dl = N->getDebugLoc();
1634 EVT VT = N->getValueType(0);
1635 unsigned FirstTblReg = IsExt ? 2 : 1;
1636
1637 // Form a REG_SEQUENCE to force register allocation.
1638 SDValue RegSeq;
1639 SDValue V0 = N->getOperand(FirstTblReg + 0);
1640 SDValue V1 = N->getOperand(FirstTblReg + 1);
1641 if (NumVecs == 2)
1642 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1643 else {
1644 SDValue V2 = N->getOperand(FirstTblReg + 2);
1645 // If it's a vtbl3, form a quad D-register and leave the last part as
1646 // an undef.
1647 SDValue V3 = (NumVecs == 3)
1648 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1649 : N->getOperand(FirstTblReg + 3);
1650 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1651 }
1652
1653 SmallVector<SDValue, 6> Ops;
1654 if (IsExt)
1655 Ops.push_back(N->getOperand(1));
1656 Ops.push_back(RegSeq);
1657 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1658 Ops.push_back(getAL(CurDAG)); // predicate
1659 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1660 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1661 }
1662
1663 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1664 bool isSigned) {
1665 if (!Subtarget->hasV6T2Ops())
1666 return NULL;
1667
1668 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1669 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1670
1671
1672 // For unsigned extracts, check for a shift right and mask
1673 unsigned And_imm = 0;
1674 if (N->getOpcode() == ISD::AND) {
1675 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1676
1677 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1678 if (And_imm & (And_imm + 1))
1679 return NULL;
1680
1681 unsigned Srl_imm = 0;
1682 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1683 Srl_imm)) {
1684 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1685
1686 unsigned Width = CountTrailingOnes_32(And_imm);
1687 unsigned LSB = Srl_imm;
1688 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1689 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1690 CurDAG->getTargetConstant(LSB, MVT::i32),
1691 CurDAG->getTargetConstant(Width, MVT::i32),
1692 getAL(CurDAG), Reg0 };
1693 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1694 }
1695 }
1696 return NULL;
1697 }
1698
1699 // Otherwise, we're looking for a shift of a shift
1700 unsigned Shl_imm = 0;
1701 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1702 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1703 unsigned Srl_imm = 0;
1704 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1705 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1706 unsigned Width = 32 - Srl_imm;
1707 int LSB = Srl_imm - Shl_imm;
1708 if (LSB < 0)
1709 return NULL;
1710 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1711 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1712 CurDAG->getTargetConstant(LSB, MVT::i32),
1713 CurDAG->getTargetConstant(Width, MVT::i32),
1714 getAL(CurDAG), Reg0 };
1715 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1716 }
1717 }
1718 return NULL;
1719 }
1720
1721 SDNode *ARMDAGToDAGISel::
1722 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1723 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1724 SDValue CPTmp0;
1725 SDValue CPTmp1;
1726 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
1727 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1728 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1729 unsigned Opc = 0;
1730 switch (SOShOp) {
1731 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1732 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1733 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1734 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1735 default:
1736 llvm_unreachable("Unknown so_reg opcode!");
1737 break;
1738 }
1739 SDValue SOShImm =
1740 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1741 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1742 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1743 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1744 }
1745 return 0;
1746 }
1747
1748 SDNode *ARMDAGToDAGISel::
1749 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1750 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1751 SDValue CPTmp0;
1752 SDValue CPTmp1;
1753 SDValue CPTmp2;
1754 if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1755 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1756 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1757 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1758 }
1759 return 0;
1760 }
1761
1762 SDNode *ARMDAGToDAGISel::
1763 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1764 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1765 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1766 if (!T)
1767 return 0;
1768
1769 unsigned TrueImm = T->getZExtValue();
1770 bool isSoImm = Pred_t2_so_imm(TrueVal.getNode());
1771 if (isSoImm || TrueImm <= 0xffff) {
1772 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1773 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1774 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1775 return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::t2MOVCCi : ARM::t2MOVCCi16),
1776 MVT::i32, Ops, 5);
1777 }
1778 return 0;
1779 }
1780
1781 SDNode *ARMDAGToDAGISel::
1782 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1783 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1784 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1785 if (!T)
1786 return 0;
1787
1788 unsigned TrueImm = T->getZExtValue();
1789 bool isSoImm = Pred_so_imm(TrueVal.getNode());
1790 if (isSoImm || (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff)) {
1791 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1792 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1793 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1794 return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::MOVCCi : ARM::MOVCCi16),
1795 MVT::i32, Ops, 5);
1796 }
1797 return 0;
1798 }
1799
1800 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1801 EVT VT = N->getValueType(0);
1802 SDValue FalseVal = N->getOperand(0);
1803 SDValue TrueVal = N->getOperand(1);
1804 SDValue CC = N->getOperand(2);
1805 SDValue CCR = N->getOperand(3);
1806 SDValue InFlag = N->getOperand(4);
1807 assert(CC.getOpcode() == ISD::Constant);
1808 assert(CCR.getOpcode() == ISD::Register);
1809 ARMCC::CondCodes CCVal =
1810 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1811
1812 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1813 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1814 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1815 // Pattern complexity = 18 cost = 1 size = 0
1816 SDValue CPTmp0;
1817 SDValue CPTmp1;
1818 SDValue CPTmp2;
1819 if (Subtarget->isThumb()) {
1820 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1821 CCVal, CCR, InFlag);
1822 if (!Res)
1823 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1824 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1825 if (Res)
1826 return Res;
1827 } else {
1828 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1829 CCVal, CCR, InFlag);
1830 if (!Res)
1831 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1832 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1833 if (Res)
1834 return Res;
1835 }
1836
1837 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1838 // (imm:i32)<<P:Pred_so_imm>>:$true,
1839 // (imm:i32):$cc)
1840 // Emits: (MOVCCi:i32 GPR:i32:$false,
1841 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1842 // Pattern complexity = 10 cost = 1 size = 0
1843 if (Subtarget->isThumb()) {
1844 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
1845 CCVal, CCR, InFlag);
1846 if (!Res)
1847 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
1848 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1849 if (Res)
1850 return Res;
1851 } else {
1852 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
1853 CCVal, CCR, InFlag);
1854 if (!Res)
1855 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
1856 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1857 if (Res)
1858 return Res;
1859 }
1860 }
1861
1862 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1863 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1864 // Pattern complexity = 6 cost = 1 size = 0
1865 //
1866 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1867 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1868 // Pattern complexity = 6 cost = 11 size = 0
1869 //
1870 // Also FCPYScc and FCPYDcc.
1871 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1872 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1873 unsigned Opc = 0;
1874 switch (VT.getSimpleVT().SimpleTy) {
1875 default: assert(false && "Illegal conditional move type!");
1876 break;
1877 case MVT::i32:
1878 Opc = Subtarget->isThumb()
1879 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1880 : ARM::MOVCCr;
1881 break;
1882 case MVT::f32:
1883 Opc = ARM::VMOVScc;
1884 break;
1885 case MVT::f64:
1886 Opc = ARM::VMOVDcc;
1887 break;
1888 }
1889 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1890 }
1891
1892 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
1893 // The only time a CONCAT_VECTORS operation can have legal types is when
1894 // two 64-bit vectors are concatenated to a 128-bit vector.
1895 EVT VT = N->getValueType(0);
1896 if (!VT.is128BitVector() || N->getNumOperands() != 2)
1897 llvm_unreachable("unexpected CONCAT_VECTORS");
1898 DebugLoc dl = N->getDebugLoc();
1899 SDValue V0 = N->getOperand(0);
1900 SDValue V1 = N->getOperand(1);
1901 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1902 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1903 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1904 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1905 }
1906
1907 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1908 DebugLoc dl = N->getDebugLoc();
1909
1910 if (N->isMachineOpcode())
1911 return NULL; // Already selected.
1912
1913 switch (N->getOpcode()) {
1914 default: break;
1915 case ISD::Constant: {
1916 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1917 bool UseCP = true;
1918 if (Subtarget->hasThumb2())
1919 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1920 // be done with MOV + MOVT, at worst.
1921 UseCP = 0;
1922 else {
1923 if (Subtarget->isThumb()) {
1924 UseCP = (Val > 255 && // MOV
1925 ~Val > 255 && // MOV + MVN
1926 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1927 } else
1928 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1929 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1930 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1931 }
1932
1933 if (UseCP) {
1934 SDValue CPIdx =
1935 CurDAG->getTargetConstantPool(ConstantInt::get(
1936 Type::getInt32Ty(*CurDAG->getContext()), Val),
1937 TLI.getPointerTy());
1938
1939 SDNode *ResNode;
1940 if (Subtarget->isThumb1Only()) {
1941 SDValue Pred = getAL(CurDAG);
1942 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1943 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1944 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1945 Ops, 4);
1946 } else {
1947 SDValue Ops[] = {
1948 CPIdx,
1949 CurDAG->getTargetConstant(0, MVT::i32),
1950 getAL(CurDAG),
1951 CurDAG->getRegister(0, MVT::i32),
1952 CurDAG->getEntryNode()
1953 };
1954 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1955 Ops, 5);
1956 }
1957 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
1958 return NULL;
1959 }
1960
1961 // Other cases are autogenerated.
1962 break;
1963 }
1964 case ISD::FrameIndex: {
1965 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1966 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1967 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1968 if (Subtarget->isThumb1Only()) {
1969 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1970 CurDAG->getTargetConstant(0, MVT::i32));
1971 } else {
1972 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1973 ARM::t2ADDri : ARM::ADDri);
1974 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1975 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1976 CurDAG->getRegister(0, MVT::i32) };
1977 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1978 }
1979 }
1980 case ISD::SRL:
1981 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1982 return I;
1983 break;
1984 case ISD::SRA:
1985 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
1986 return I;
1987 break;
1988 case ISD::MUL:
1989 if (Subtarget->isThumb1Only())
1990 break;
1991 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1992 unsigned RHSV = C->getZExtValue();
1993 if (!RHSV) break;
1994 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1995 unsigned ShImm = Log2_32(RHSV-1);
1996 if (ShImm >= 32)
1997 break;
1998 SDValue V = N->getOperand(0);
1999 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2000 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2001 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2002 if (Subtarget->isThumb()) {
2003 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2004 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2005 } else {
2006 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2007 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
2008 }
2009 }
2010 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2011 unsigned ShImm = Log2_32(RHSV+1);
2012 if (ShImm >= 32)
2013 break;
2014 SDValue V = N->getOperand(0);
2015 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2016 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2017 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2018 if (Subtarget->isThumb()) {
2019 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2020 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2021 } else {
2022 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2023 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
2024 }
2025 }
2026 }
2027 break;
2028 case ISD::AND: {
2029 // Check for unsigned bitfield extract
2030 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2031 return I;
2032
2033 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2034 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2035 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2036 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2037 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2038 EVT VT = N->getValueType(0);
2039 if (VT != MVT::i32)
2040 break;
2041 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2042 ? ARM::t2MOVTi16
2043 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2044 if (!Opc)
2045 break;
2046 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2048 if (!N1C)
2049 break;
2050 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2051 SDValue N2 = N0.getOperand(1);
2052 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2053 if (!N2C)
2054 break;
2055 unsigned N1CVal = N1C->getZExtValue();
2056 unsigned N2CVal = N2C->getZExtValue();
2057 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2058 (N1CVal & 0xffffU) == 0xffffU &&
2059 (N2CVal & 0xffffU) == 0x0U) {
2060 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2061 MVT::i32);
2062 SDValue Ops[] = { N0.getOperand(0), Imm16,
2063 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2064 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2065 }
2066 }
2067 break;
2068 }
2069 case ARMISD::VMOVRRD:
2070 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2071 N->getOperand(0), getAL(CurDAG),
2072 CurDAG->getRegister(0, MVT::i32));
2073 case ISD::UMUL_LOHI: {
2074 if (Subtarget->isThumb1Only())
2075 break;
2076 if (Subtarget->isThumb()) {
2077 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2078 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2079 CurDAG->getRegister(0, MVT::i32) };
2080 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2081 } else {
2082 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2083 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2084 CurDAG->getRegister(0, MVT::i32) };
2085 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2086 }
2087 }
2088 case ISD::SMUL_LOHI: {
2089 if (Subtarget->isThumb1Only())
2090 break;
2091 if (Subtarget->isThumb()) {
2092 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2093 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2094 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2095 } else {
2096 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2097 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2098 CurDAG->getRegister(0, MVT::i32) };
2099 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2100 }
2101 }
2102 case ISD::LOAD: {
2103 SDNode *ResNode = 0;
2104 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2105 ResNode = SelectT2IndexedLoad(N);
2106 else
2107 ResNode = SelectARMIndexedLoad(N);
2108 if (ResNode)
2109 return ResNode;
2110 // Other cases are autogenerated.
2111 break;
2112 }
2113 case ARMISD::BRCOND: {
2114 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2115 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2116 // Pattern complexity = 6 cost = 1 size = 0
2117
2118 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2119 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2120 // Pattern complexity = 6 cost = 1 size = 0
2121
2122 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2123 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2124 // Pattern complexity = 6 cost = 1 size = 0
2125
2126 unsigned Opc = Subtarget->isThumb() ?
2127 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2128 SDValue Chain = N->getOperand(0);
2129 SDValue N1 = N->getOperand(1);
2130 SDValue N2 = N->getOperand(2);
2131 SDValue N3 = N->getOperand(3);
2132 SDValue InFlag = N->getOperand(4);
2133 assert(N1.getOpcode() == ISD::BasicBlock);
2134 assert(N2.getOpcode() == ISD::Constant);
2135 assert(N3.getOpcode() == ISD::Register);
2136
2137 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2138 cast<ConstantSDNode>(N2)->getZExtValue()),
2139 MVT::i32);
2140 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2141 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2142 MVT::Flag, Ops, 5);
2143 Chain = SDValue(ResNode, 0);
2144 if (N->getNumValues() == 2) {
2145 InFlag = SDValue(ResNode, 1);
2146 ReplaceUses(SDValue(N, 1), InFlag);
2147 }
2148 ReplaceUses(SDValue(N, 0),
2149 SDValue(Chain.getNode(), Chain.getResNo()));
2150 return NULL;
2151 }
2152 case ARMISD::CMOV:
2153 return SelectCMOVOp(N);
2154 case ARMISD::CNEG: {
2155 EVT VT = N->getValueType(0);
2156 SDValue N0 = N->getOperand(0);
2157 SDValue N1 = N->getOperand(1);
2158 SDValue N2 = N->getOperand(2);
2159 SDValue N3 = N->getOperand(3);
2160 SDValue InFlag = N->getOperand(4);
2161 assert(N2.getOpcode() == ISD::Constant);
2162 assert(N3.getOpcode() == ISD::Register);
2163
2164 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2165 cast<ConstantSDNode>(N2)->getZExtValue()),
2166 MVT::i32);
2167 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
2168 unsigned Opc = 0;
2169 switch (VT.getSimpleVT().SimpleTy) {
2170 default: assert(false && "Illegal conditional move type!");
2171 break;
2172 case MVT::f32:
2173 Opc = ARM::VNEGScc;
2174 break;
2175 case MVT::f64:
2176 Opc = ARM::VNEGDcc;
2177 break;
2178 }
2179 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2180 }
2181
2182 case ARMISD::VZIP: {
2183 unsigned Opc = 0;
2184 EVT VT = N->getValueType(0);
2185 switch (VT.getSimpleVT().SimpleTy) {
2186 default: return NULL;
2187 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2188 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2189 case MVT::v2f32:
2190 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2191 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2192 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2193 case MVT::v4f32:
2194 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2195 }
2196 SDValue Pred = getAL(CurDAG);
2197 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2198 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2199 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2200 }
2201 case ARMISD::VUZP: {
2202 unsigned Opc = 0;
2203 EVT VT = N->getValueType(0);
2204 switch (VT.getSimpleVT().SimpleTy) {
2205 default: return NULL;
2206 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2207 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2208 case MVT::v2f32:
2209 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2210 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2211 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2212 case MVT::v4f32:
2213 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2214 }
2215 SDValue Pred = getAL(CurDAG);
2216 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2217 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2218 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2219 }
2220 case ARMISD::VTRN: {
2221 unsigned Opc = 0;
2222 EVT VT = N->getValueType(0);
2223 switch (VT.getSimpleVT().SimpleTy) {
2224 default: return NULL;
2225 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2226 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2227 case MVT::v2f32:
2228 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2229 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2230 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2231 case MVT::v4f32:
2232 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2233 }
2234 SDValue Pred = getAL(CurDAG);
2235 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2236 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2237 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2238 }
2239 case ARMISD::BUILD_VECTOR: {
2240 EVT VecVT = N->getValueType(0);
2241 EVT EltVT = VecVT.getVectorElementType();
2242 unsigned NumElts = VecVT.getVectorNumElements();
2243 if (EltVT == MVT::f64) {
2244 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2245 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2246 }
2247 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2248 if (NumElts == 2)
2249 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2250 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2251 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2252 N->getOperand(2), N->getOperand(3));
2253 }
2254
2255 case ISD::INTRINSIC_VOID:
2256 case ISD::INTRINSIC_W_CHAIN: {
2257 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2258 switch (IntNo) {
2259 default:
2260 break;
2261
2262 case Intrinsic::arm_neon_vld1: {
2263 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2264 ARM::VLD1d32, ARM::VLD1d64 };
2265 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2266 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2267 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
2268 }
2269
2270 case Intrinsic::arm_neon_vld2: {
2271 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2272 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2273 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2274 ARM::VLD2q32Pseudo };
2275 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
2276 }
2277
2278 case Intrinsic::arm_neon_vld3: {
2279 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2280 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2281 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2282 ARM::VLD3q16Pseudo_UPD,
2283 ARM::VLD3q32Pseudo_UPD };
2284 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2285 ARM::VLD3q16oddPseudo_UPD,
2286 ARM::VLD3q32oddPseudo_UPD };
2287 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2288 }
2289
2290 case Intrinsic::arm_neon_vld4: {
2291 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2292 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2293 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2294 ARM::VLD4q16Pseudo_UPD,
2295 ARM::VLD4q32Pseudo_UPD };
2296 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2297 ARM::VLD4q16oddPseudo_UPD,
2298 ARM::VLD4q32oddPseudo_UPD };
2299 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2300 }
2301
2302 case Intrinsic::arm_neon_vld2lane: {
2303 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2304 ARM::VLD2LNd32Pseudo };
2305 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2306 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes);
2307 }
2308
2309 case Intrinsic::arm_neon_vld3lane: {
2310 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2311 ARM::VLD3LNd32Pseudo };
2312 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2313 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes);
2314 }
2315
2316 case Intrinsic::arm_neon_vld4lane: {
2317 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2318 ARM::VLD4LNd32Pseudo };
2319 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2320 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes);
2321 }
2322
2323 case Intrinsic::arm_neon_vst1: {
2324 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2325 ARM::VST1d32, ARM::VST1d64 };
2326 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2327 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2328 return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
2329 }
2330
2331 case Intrinsic::arm_neon_vst2: {
2332 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2333 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2334 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2335 ARM::VST2q32Pseudo };
2336 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
2337 }
2338
2339 case Intrinsic::arm_neon_vst3: {
2340 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2341 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2342 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2343 ARM::VST3q16Pseudo_UPD,
2344 ARM::VST3q32Pseudo_UPD };
2345 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2346 ARM::VST3q16oddPseudo_UPD,
2347 ARM::VST3q32oddPseudo_UPD };
2348 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2349 }
2350
2351 case Intrinsic::arm_neon_vst4: {
2352 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2353 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2354 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2355 ARM::VST4q16Pseudo_UPD,
2356 ARM::VST4q32Pseudo_UPD };
2357 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2358 ARM::VST4q16oddPseudo_UPD,
2359 ARM::VST4q32oddPseudo_UPD };
2360 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2361 }
2362
2363 case Intrinsic::arm_neon_vst2lane: {
2364 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2365 ARM::VST2LNd32Pseudo };
2366 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2367 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes);
2368 }
2369
2370 case Intrinsic::arm_neon_vst3lane: {
2371 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2372 ARM::VST3LNd32Pseudo };
2373 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2374 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes);
2375 }
2376
2377 case Intrinsic::arm_neon_vst4lane: {
2378 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2379 ARM::VST4LNd32Pseudo };
2380 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2381 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes);
2382 }
2383 }
2384 break;
2385 }
2386
2387 case ISD::INTRINSIC_WO_CHAIN: {
2388 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2389 switch (IntNo) {
2390 default:
2391 break;
2392
2393 case Intrinsic::arm_neon_vtbl2:
2394 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2395 case Intrinsic::arm_neon_vtbl3:
2396 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2397 case Intrinsic::arm_neon_vtbl4:
2398 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2399
2400 case Intrinsic::arm_neon_vtbx2:
2401 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2402 case Intrinsic::arm_neon_vtbx3:
2403 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2404 case Intrinsic::arm_neon_vtbx4:
2405 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2406 }
2407 break;
2408 }
2409
2410 case ISD::CONCAT_VECTORS:
2411 return SelectConcatVector(N);
2412 }
2413
2414 return SelectCode(N);
2415 }
2416
2417 bool ARMDAGToDAGISel::
2418 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2419 std::vector<SDValue> &OutOps) {
2420 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2421 // Require the address to be in a register. That is safe for all ARM
2422 // variants and it is hard to do anything much smarter without knowing
2423 // how the operand is used.
2424 OutOps.push_back(Op);
2425 return false;
2426 }
2427
2428 /// createARMISelDag - This pass converts a legalized DAG into a
2429 /// ARM-specific DAG, ready for instruction scheduling.
2430 ///
2431 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2432 CodeGenOpt::Level OptLevel) {
2433 return new ARMDAGToDAGISel(TM, OptLevel);
2434 }
ZPU llvm backend wip